JPH07109592B2 - CPU-IO parallel operation simulation method - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for simulating a microcomputer program on a general-purpose computer different from an actual machine (target machine), and testing / debugging the microcomputer program.
The present invention relates to a CPU-IO parallel operation simulation method for performing a simulation test of a program that controls IO in a state close to a target machine.

[Conventional technology]

Previously, Information Processing Society of Japan Microcomputer Study Group materials
As described in 20-3, this is a method of simulating only the CPU and memory, and when testing a program that controls peripheral IO, IO operation is performed by commands that should set breakpoints, memory settings, etc. To simulate.

[Problems to be solved by the invention]

The above conventional method uses commands for setting breakpoints and memory settings.
To simulate the IO operation, I
It was difficult to set the environment such that the state of O changed. For this reason, there is a problem that timing failure during IO control and detection of both program and IO wait states (hangup) cannot be detected.

An object of the present invention is to detect CPU (program execution) and IO operations in parallel, thereby detecting a defect in the microcomputer software as described above.
It is to provide a CPU-IO parallel operation simulation method.

[Means for solving problems]

When the IO model requests an event (define the time required to execute the IO operation), the purpose of the above is to interrupt the processing of the IO model, store the information of the interruption point, and return the control to the CPU. Registration step and event monitoring step that monitors the occurrence of events during CPU instruction simulation. When an event occurs, CPU instruction execution is interrupted, information saved when an event is requested is restored, and IO model processing is restarted. This is achieved by realizing CPU-IO parallel operation by controlling IO processing-IO processing interruption-CPU processing-CPU processing interruption-IO processing re-execution by the event control step.

[Action]

When the IO model requests an event, the processing of the IO model is interrupted, the information of the interruption point is stored, the event that returns the control to the CPU is registered, the event occurrence is monitored during the instruction simulation of the CPU, and the event occurs. , CPU instruction execution is interrupted, information saved at the time of event request is recovered and I / O
By restarting the processing of the model, CPU-IO parallel operation is realized, and it is possible to easily simulate a hardware abnormality that is difficult to reproduce on an actual machine.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the simulation system of the present invention.

In FIG. 1, 1 is a general-purpose computer, a CPU simulator that simulates a CPU operation of an architecture different from that of the general-purpose computer, 2 is a memory that stores a microprogram executed by the CPU simulator, and 3 is a peripheral device operation simulation IO model, 4 is an IO that simulates the operation of the signal line group between the CPU and peripheral devices
Simulator, 5 is a data file that stores data input / output by peripheral devices, 6 is an event (time lapse request) that the IO model requests during control of the IO model, and CPU
Event registration mechanism that transfers control to the simulator, 7 is an event monitoring mechanism that determines whether the time requested by the event has been reached, 8 is an event control mechanism that transfers control to the IO model when the time requested by the event is reached Is.

FIG. 2 is a flowchart showing a CPU-IO parallel operation simulation method.

The CPU-IO parallel operation simulation method of the present invention will be described with reference to FIG.

First, the microcomputer program is executed by the CPU simulator, and if it is an IO control instruction, the IO simulator is started (20
1). Next, the IO simulator returns the I corresponding to the IO control instruction.
Start the O model (202). The IO model starts IO operation. At this time, when it takes time to execute the IO operation, the IO model requests an event from the IO simulator (20
3). The event request is stored by the event registration mechanism after storing the event value (time until the event arrives) and IO model break point information (IO model state at the time of event request).
Control is forcibly transferred to the CPU simulator (204). The CPU simulator starts instruction execution of the microcomputer program. At this time, the number of instruction execution cycles is counted for each instruction execution, and when the event monitoring time is reached, the event monitoring mechanism of the IO simulator is activated (205). The event monitoring mechanism counts the event value of the registered event, judges whether there is an event that has reached the requested event value, and if there is no corresponding event, returns control to the CPU simulator, and if there is an applicable event, , Activates the event control mechanism (206). The event control mechanism recovers the IO model break point information stored at the time of event request, and transfers control to the IO model (207). For the IO model, set the state after the lapse of time (the state of IO after the end of IO operation)
Return control to the U simulator (208).

Next, IO simulator at the time of event request / occurrence,
The control procedure between the CPU simulator and the IO model will be described in more detail by taking each simulator and model as an example of a software function call.

In general, a function call in software saves CPU register information (program counter value, return address, etc.) in a function local area (generally a stack area) and branches to the call destination address.
Further, at the time of return, it is possible to return to the return address at the time of call by recovering the information in the stack area register saved at the time of call to the register.

At this time, it is possible to freely control the return destination of the function by saving and saving the CPU register information to be saved / recovered. (Note that, depending on the compiler, if the functions are nested, this stack area is pointed by pointers, and the stack nesting relationship can be referred to from upper to lower functions and from lower to higher functions. The present invention is realized as follows by utilizing the characteristics of this software.

In Figure 2, if there is an event request from the IO model (20
3), the event registration mechanism refers to the stack area and IO
Saves CPU register information (information when the IO model was interrupted) when the model called the IO simulator.

Therefore, if you return as it is, control returns to the IO model side, but by referring to the pointers of the stack areas described above, the stack area of a higher level (the stack area of the function at the time (IO) when the IO simulator is called) Restores register information with contents. As a result, the IO simulator returns to the CPU simulator side without returning to the IO model.

Next, when the event monitoring mechanism (206) recognizes the restart time of the IO model, the event control mechanism determines the interruption point information of the IO model saved by the event registration mechanism at the time of the event request (the CPU at the time when the IO model requested the event). Register information) and branch to that address. This allows
It is possible to restart the IO operation (208) after a lapse of time.

As described above, the CPU-IO parallel operation simulation can be performed.

A state diagram of parallel operation of CPU and IO is shown in FIG.

Next, a floppy disk controller (hereinafter FDC
(See abbreviated) will be described with reference to FIG.

First, execute the FDC control microcomputer program on the CPU simulator, and execute the IO control instruction (seek operation instruction to FDC).
When is detected, the IC simulator is started (401). The IO simulator recognizes that the IO control instruction is an instruction to the FDC and activates the FDC model (402). The FDC model recognizes that the IO control instruction is a seek operation instruction,
Set a flag that is in seek operation in the status register that indicates the status of the FDC model. Since it takes time to complete the seek operation, an event is requested to the IO simulator (40
3). The event registration mechanism of the IO simulator registers the time (event value) requested by the FDC model. Furthermore, the state when the FDC model requests an event (contents of the register at the time of event request) is saved, and control is forcibly returned to the CPU simulator (process interruption of the FDC model) (404). CP
The U simulator resumes execution of the FDC control microcomputer program. At this time, the number of instruction cycles is counted every time one instruction is executed, and it is determined whether the event monitoring time has been reached.
If the monitoring time has not been reached, instruction execution is continued, and if the monitoring time has been reached, the event monitoring mechanism of the IO simulator is activated (405). The event monitoring mechanism counts down the event value of the seek operation of the registered FDC model and determines whether the seek operation end time has been reached. If the seek operation end time has not been reached, control is returned to the CPU simulator to continue instruction execution, and if the seek operation end time is reached, the event control mechanism of the IO simulator is activated (406). The event control mechanism restores the state of the FDC model saved at the time of event request, and transfers control to the FDC model (processing interruption of the CPU simulator) (407). The FDC model sets a flag indicating the end of the seek operation in the status register, makes an interrupt request to the IO simulator, and then returns control to the IO simulator (408).

As described above, FDC control microcomputer program and FDC
A parallel motion simulation of the model is realized.

Also, in step 405, while the FDC model is seeking, the FDC control microcomputer program sends data write instructions, etc.
When an IO control command is detected, it is possible to detect a defect in the microcomputer program as an IO control command with an incorrect timing.

In the above embodiment, an example in which the IO model is described in a programming language and implemented as a load program has been described, but in the case of procedure data in which the IO model describes operation specifications according to a certain rule, the parallel operation is simulated as follows. It becomes possible to do.

That is, in step 402, instead of passing control to the FCD model, the procedure data of the FDC model is read and the FDC operation is simulated according to the described contents. Further, in step 404, the position of the procedure data at the time of the event request is stored. Further, in step 407, instead of recovering the state of the FDC model saved at the time of the event request, data reading is restarted from the position of the procedure data stored at the time of the event request.

In the present embodiment, it is possible to test the microcomputer software in a state closer to the actual machine, and it is possible to easily simulate the abnormality of the hardware that is difficult to reproduce in the actual machine, so that the more efficient software test is possible.

In addition, since the software can be developed before the hardware is completed, the development period can be shortened.

〔The invention's effect〕

According to the present invention, a hardware abnormality that is difficult to reproduce in an actual machine can be easily simulated, so that an effect that a more efficient software test is possible can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a simulation system of the present invention, FIG. 2 is a flowchart showing a method of CPU-IO parallel operation simulation, FIG. 3 is a state diagram of CPU-IO parallel operation simulation, and FIG. It is a conceptual diagram which shows the Example of the parallel operation by FDC seek operation. 1 ... CPU simulator, 2 ... memory, 3 ... IO model group, 4 ... IO simulator, 5 ... data file, 6 ... event registration mechanism, 7 ... event monitoring mechanism, 8 ... event control mechanism .

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuji Tanaka 1 Horiyamashita, Hadano City, Kanagawa Pref. Hitachi Computer Computer Engineering Co., Ltd. Examiner Umemura ▲ Kikiki (56) Reference JP 61-239335 (JP, A) JP 62-279421 (JP, A) JP 61-59559 (JP, A) JP 59-229620 (JP, A) JP 56-153456 (JP, A)

Claims (1)

[Claims] 1. On a general-purpose computer, a CPU such as a microprocessor having an architecture different from that of the general-purpose computer, a storage device connected to the CPU, and at least one
In order to simulate the operation of each peripheral device, a CPU simulator that sequentially fetches instructions placed on the storage device and simulates the instruction operation, an IO model that simulates the operation of the peripheral device, the CPU and the In the CPU-IO parallel operation simulation method that tests the software with the IO simulator that simulates the operation of the signal line group that connects the peripheral devices, the restart time of the IO model operation simulation is reserved by the clock that manages the simulation progress. When the event request is issued from the IO model, the operation execution of the IO model is suspended, the interruption point information is temporarily saved, and control is returned to the CPU simulator. To monitor the occurrence of events in CPU-IO parallel operation simulation method, which comprises a step of monitoring an event and an event control step of interrupting the instruction execution of the CPU simulator when an event occurs and restarting the operation execution of the IO model.