JP2773042B2 - In-circuit emulator bus switching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an in-circuit emulator (hereinafter referred to as an IC).
Called E. Target emulation CPU in parentheses)
This is a method for switching the address bus, data bus, and control bus of the CPU from the target side to the ICE internal side when the execution of the target program is stopped. Can be switched with or without.

(B) Conventional Techniques and Problems Next, the configuration of the ICE bus switching unit will be described with reference to FIG.

3 is a bus switching control circuit, 2 is a TCPU, 3 is a bus switching circuit, 4 is a TCPU2 bus, 5 is an ICE internal bus, 6 is a target 20 side bus, 10 is an ICE, and 20 is a target. is there.

ICE10 is a development support device for devices equipped with a CPU.
CP mounted on socket on printed board of target 20
By connecting the probe of ICE10 instead of U, TC
This device debugs the target 20 while controlling the operation of PU2.

In the operation of the CPU, when the execution of the target program is stopped, it is necessary to switch the bus 4 from the bus 6 to the bus 5 after the fetch of the breakpoint interrupt instruction occurs. This is called a stop sequence.

At the start of execution of the target program, it is necessary to switch the bus 4 from the bus 5 to the bus 6 after the fetch of the return instruction in the program in the ICE occurs. This is called a start sequence.

In FIG. 3, the bus 4 is switched to the bus 5 or the bus 6 by the bus switching control circuit 1.

Conventionally, a bank switching method or the like has been used as a bus switching method for this stop sequence.

Next, a model of program execution in the stop sequence will be described with reference to FIG.

F in FIG. 4 is an instruction prefetch cycle, and R / W is a memory read / write fetch cycle.

Next, an outline of a conventional bus switching method will be described with reference to FIG.

Banks 31 to 34 in FIG. 5 indicate memory areas previously secured in the internal memory of the ICE.

In FIG. 5, dR is a double word read cycle, dW is a double word write cycle, and wW is a word write cycle.

In the banks 31 to 34, segment data and the like required by the CPU are set in accordance with the memory access order predicted according to the operation of the CPU.

Taking a stop sequence as an example, in this sequence, it is assumed that memory access uses the ICE internal memory.

First, the memory access is set to be executed from the bank 31. The order of the data set in bank 31 is
It's just one order of predicting CPU behavior.

Normally, when the mode of the CPU is switched or a page function that enables the real memory to be handled in units of pages occurs, a new memory access order occurs, and a new bank must be switched.

In FIG. 5, data for which an access that would cause a paging switch is predicted is set in the bank 31, but the page conversion does not actually occur at the location 21 in FIG. Switch bank to 32.

In other words, the bank 32 is not used, but the bank 32 is accessed in two steps, and page conversion occurs at a location indicated by 302 in FIG. In FIG. 4, there are 22 points. So the bank
Switch to 33. This is called a bank switching method.

Further, the bank 34 is also a bank prepared on the assumption that the page conversion occurs at the location indicated by 23 in FIG. 4, but since the page conversion did not occur in this model, the bank 34 was used.
Does not transition to 34.

As shown in FIGS. 4 and 5, the bank switching method is to completely collect the banks along all the memory access orders of the predicted CPU and complete the switching without losing the context before and after the bus switching. is there.

FIG. 6 is a timing chart of FIG.
When the CPU operates, the bank shown in FIG. 4 is switched between 4001 and 4002 in FIG.

In FIG. 6, 401 to 415 are statuses, and sections (cycles) of 40, 42, and 44 are instruction prefetch, and 41 and
Section 43 indicates memory read / write access.

Now, assuming that the status 401 is the status of the prefetch instruction for the breakpoint interrupt instruction, after the status 402, the bus 4 is switched from the bus 6 to the bus 5, and the memory inside the ICE, in other words, the bank prepared in advance is accessed. Become.

However, this bank switching method has the following problems.

(A) It is necessary to completely predict and collect the memory read / write access order. However, a CPU having a page function may not be able to predict the occurrence of page conversion. Given that contexts may be damaged before and after bus switching and that the number of higher-order microcontrollers will increase in the future, it is certain that CPU mode switching and page conversion will occur frequently. There is a limit to the switching method.

(A) Even a CPU without a page function has a limitation in the internal memory capacity of the ICE 10 and thus a limit on the number of banks, so that it may be difficult to cope with all the predicted access orders.

(C) Object of the Invention The present invention provides an ICE bus switching method that detects the type and condition of a status from a status detection circuit in the case of a stop sequence and switches the bus.

(D) Embodiment of the Invention Next, the flowchart of the embodiment according to the present invention will be described with reference to FIG.
Shown in the figure.

FIG. 1 is a flowchart when the bus switching control circuit 1 of FIG. 3 is in a stop sequence.

In step 51, it is determined whether or not it is a prefetch of a breakpoint interrupt instruction.

In step 52, it is determined whether or not the next status is an interrupt acknowledge cycle.

In step 53, it is determined whether the next status is instruction prefetch.

In step 54, the bus 4 is switched from the bus 6 to the bus 5.

In step 55, it is determined whether or not the prefetch is the fifth time.

In step 56, the bus having the next status is switched from bus 5 to bus 6.

In FIG. 1, a breakpoint interrupt instruction prefetch, the presence or absence of an interrupt acknowledge cycle, a memory read / write access cycle, and an instruction prefetch are detected, and the bus 4 is switched according to the conditions.

The basic point of the operation of FIG. 1 is that instruction prefetch switches the bus 4 from the bus 6 to the bus 5 and memory read / write access switches the bus 4 to the bus 5
Switching from the bus side to the bus 6 side,
In the instruction prefetch within the number of times, the cycle following the prefetch is always a read / write cycle, and forcibly switching to the bus 6 is two points.

Here, the reason for setting the number of times to 5 is that the number of instruction prefetches cannot be specified from the case where it does not occur at all, or the case where it occurs 3 or 4 times, depending on the type of CPU or the operating condition. Five times.

The reason for forcibly switching to the bus 6 is that the bus 4
This is because it is too late to switch to the bus 6 after detecting the status when switching to the bus 6 from the bus 5 side.

FIG. 2 shows a timing chart in the case where the operation of the CPU is exactly the same as that of FIG. 6. As in FIG. 6, 601 to 615 in FIG. 602 is a discarded prefetch, 603 to 609 and 611 to 613 are memory read / write accesses including an interrupt acknowledge cycle, 61
Statuses 0 and 614 respectively indicate instruction prefetch.

2, F is an instruction prefetch cycle, R / W is a memory read / write fetch cycle, X
Represents that the bus 4 is switched to the bus 6 side, and I represents that the bus 4 is switched to the bus 5 side.

Now, when the operation of the bus switching control circuit of FIG. 3 is applied to the operation in this state, it is as follows.

First, a breakpoint instruction pull fetch of status 601 is detected.

Next, an interrupt acknowledge cycle is detected in the statuses 603 and 604 in the section 61.

Here, if the interrupt acknowledgment cycle is not detected and the next instruction prefetch cycle is detected, it is not considered that the interrupt processing routine has been entered, and the process waits for the next breakpoint interrupt instruction prefetch to occur. become. This state is shown at 51 and 52 in FIG.

Next, the operation of the control circuit corresponding to 53 to 56 in FIG. 1 will be described.

In FIG. 1, the detection of the interrupt acknowledge cycle indicates that the control circuit has entered the interrupt processing routine.

Next, when the instruction prefetch is detected, the bus 4 is switched from the bus 6 to the bus 5 for one cycle at that time. In other words, the section 65 in FIG. 2 is a state where the bus 4 is switched to the bus 5 side.

In the next cycle of the instruction prefetch, the control circuit 1 forcibly switches the bus 4 from the bus 5 to the bus 6 without detecting the status.

In this model of program execution, the status 611 in FIG.
Switch to the side forcibly.

However, for example, if the status 611 is instruction prefetch following 610, it is necessary to switch to the bus 5 again.

Actually, in FIG. 1, the instruction prefetch continues after the status number 614 in FIG. 4, and the control circuit performs this function. This state is shown in sections 66 to 68 in FIG.

Here, the section 67 is the time from the start of the cycle of T15 to the detection of the status of 615, but is temporarily switched to the bus 6 side.

As described above, since the number of instruction prefetches is set, the operation of detecting the instruction prefetch occurs up to five times, and from the sixth time, the operation is completely switched to the bus 5 side, and the stop sequence ends.

(E) Effects of the Invention According to the present invention, the following effects can be obtained.

(A) The status detection circuit switches the bus from the target side to the ICE internal side on a cycle-by-cycle basis depending on the status type and conditions. As for, the bus can be switched reliably.

(A) Since it is not necessary to use a bank, the memory consumption inside the ICE is reduced, which contributes to ICE design.

[Brief description of the drawings]

FIG. 1 is a flowchart of an embodiment according to the present invention, and FIG.
1 is a timing chart of FIG. 1, FIG. 3 is a configuration diagram of a bus switching unit of the ICE, FIG. 4 is an explanatory diagram of a model of a program execution in a stop sequence, and FIG. 5 is a schematic explanatory diagram of a conventional bus switching method. FIG. 6 is a timing chart of FIG. 1. Bus switch control circuit 2. TCPU (target emulation CPU) 3. Bus switch circuit 4. TCPU2
, ICE (in-circuit emulator) internal bus, 6 ... target 20 bus, 10 ... ICE, 20
……target.

Claims (1)

(57) [Claims] When the execution of a target program of an in-circuit emulator is stopped, the presence or absence of a breakpoint interrupt instruction prefetch and an interrupt acknowledge cycle, a memory read / write access cycle, and an instruction prefetch cycle are detected. The CPU bus is switched to the bus inside the in-circuit emulator. For memory read / write access, the bus of the target emulation CPU is switched to the target bus. In the instruction prefetch within a preset number of times, the cycle following the prefetch is the target cycle. An in-circuit emulator that switches the emulation CPU bus to the target bus side. Scan switching method.