JP2711159B2 - Processor operation state adjustment method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor operating state adjusting method for adjusting a difference in operating state depending on a type of a processor, for example, emulation operation control in an emulator capable of debugging a user program. The present invention relates to a technology effective when applied to a space switching process between a system space for emulation and a user space for emulation operation.

(Prior art)

An emulator for system debugging and system evaluation in the development of microprocessor-applied equipment enables hardware and software debugging by executing and stopping user programs on a microprocessor equivalent to the microprocessor included in the system. It is assumed that.

The microprocessor in this emulator includes:
There is a user space for operating by being interfaced with the user system, and a system space for operating while being separated from the user system. Emulation execution is controlled by switching these space states.

In the conventional emulator, the state switching from the user space to the system space is performed by an interrupt input due to a break or the like, and the switching from the system space to the user space state is performed in a predetermined sequence when the microprocessor executes a specific instruction. This is performed by detecting the number of bus cycles.

An example of a document describing such an emulator is “SA710M Hardware User's Manual” issued by Sophia Systems on May 10, 1985.

[Problems to be solved by the invention]

Recently, instruction cache memory, RAM (random access memory),
A microprocessor having a built-in ROM (read only memory) or the like and having one microprocessor having various operation modes has been developed. In such a microprocessor, the same instruction is executed depending on whether the instruction execution area is an internal memory or an external memory, or if the operation mode is related to bus cycle control, the operation mode is different. Even so, the execution bus cycle may be different. In other words, the predetermined number of continuous bus cycles resulting from the execution of the above-described specific instruction will differ from each other depending on the operation mode. As a result, normal space switching, particularly switching from the system space to the user space, may not be possible. Have been found by the present inventors.

Such a problem can be solved, for example, by providing dedicated hardware for adjusting the number of bus cycles for each operation mode and switching it according to the operation mode in order to cope with all the operation modes. , Hardware is required only for these types, and an increase in the scale of the hardware and an increase in manufacturing costs are inevitable.

An object of the present invention is to provide a method capable of easily adjusting the operation state of a high-performance processor without increasing hardware.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, the difference in operation state between the operation modes of the processor having a plurality of operation modes is adjusted by the instruction to be executed by the processor.

Here, the adjustment target can be the number of bus cycles of the processor, and for that purpose, a NOP (non-operation) instruction can be inserted into the instruction to be executed by the processor. Further, in the emulation, an instruction to be executed by the processor can be included in a series of instructions for processing for switching between the system space and the user space.

(Operation)

According to the above-described means, the difference in the operation state depending on the operation mode of the processor is adjusted by the execution instruction of the processor, and this enables the adjustment of the operation state of the high-performance processor without increasing the hardware. Act on.

〔Example〕

FIG. 1 shows an emulator to which an embodiment of the present invention is applied.

The emulator shown in the figure is not particularly limited, but includes a microprocessor 1, a system interface 2, a system memory and I / O (input / output) 3,
It includes a proxy memory 4, a space control circuit 5, a trace memory unit 6, a break detection circuit 7, and a user interface 8.

A microprocessor having a function equivalent to that of the microprocessor to be emulated is applied to the microprocessor 1. In the emulator, the microprocessor 1 includes, but is not limited to, a prefetch buffer for prefetching the instruction before executing the instruction, a RAM as a general-purpose memory, and the like. The microprocessor 1 is connected to a 16-bit processor bus 10 and is connected to the system interface 2 and the user interface 8 via the processor bus 10.

The substitute memory 4 substitutes a memory to be included in the user system 9 when the user system 9 is completed, and stores a user program to be debugged. When the program in the proxy memory 4 is executed by the microprocessor 1, it is in the user space state. In this state, the user interface 9 is activated and the user system 9 is connected to the processor bus.
The microprocessor 1 controls operation of the user system 9, that is, emulation. During this emulation operation, the processor bus
Data and addresses on 10 and control information are traced by being sequentially written into the trace memory unit 6.

The break detection circuit 7 allows the microprocessor 1 to set a break condition for stopping the operation of the microprocessor 1 when the control operation state of the microprocessor 1 executing the user program reaches a predetermined state. , And can be arbitrarily changed by the user's specification. The break detection circuit 7 detects a break based on the break condition, and transmits the detection result to the space control circuit 5. During the emulation operation, the system interface 2 is inactive, and the system memory and the I / O 3 are connected to the processor bus 10.
More detached.

On the other hand, while the emulation operation is stopped, the emulation operation is set to the system space state, and the system interface 2 is activated to connect the system memory and the I / O 3 to the processor bus 10. In this state, the microprocessor 1 executes a predetermined emulation operation control by executing a system program stored in the system memory. In this state, the user interface 8 is inactive and the user system 9 is disconnected from the processor bus 10.

Switching of the active / inactive state of the system interface 2 and the user interface 8 is performed by the space control circuit 5. That is, when a break is detected by the break detection circuit 7 during the emulation operation, the space control circuit 5 deactivates the user interface 8 and activates the system interface 2 so that the space interface 5 can be activated from the user space. Enables migration to system space. The space control circuit 5 monitors the state of the processor bus 10 while the emulation operation is stopped, that is, during the emulation operation control by the microprocessor 1, and counts the number of bus cycles based on the occurrence of a predetermined event during execution of the specific instruction. When the predetermined number of bus cycles has been reached, the user interface 8 is activated and the system interface 2 is deactivated, thereby enabling a transition from the system space to the user space. Also, the break detection circuit 7
Is reported to the space control circuit 5 and then input to the microprocessor 1 as an interrupt.

FIG. 2 shows an example of a memory map of the microprocessor 1 in the emulator. As shown in the figure, an external memory space, a built-in memory space, and a built-in I / O space are assigned addresses in an address space represented by a hexadecimal number. The microprocessor 1 basically has an 8-bit configuration, but is connected to a 16-bit processor 10,
Word (16 bits) for internal memory and external memory space
It can be accessed in units and bytes (8 bits), and has a word / byte area switching function by setting the control register in the built-in I / O for the external memory space. By using only the lower part of, access in byte units is performed.

The difference between the upper word / byte area is, as described above,
This affects the number of instruction execution bus cycles of the microprocessor 1. In other words, even when the same instruction is executed in the byte area, one word access is equivalent to two byte accesses, so that the number of bus cycles increases as compared with the execution in the word area. Therefore, in this embodiment, when switching from the system space to the user space, the number of bus cycles is adjusted as follows.

FIG. 3 shows a switching control circuit for controlling the switching from the system space to the user space in the space control circuit 5. The switching control circuit includes a flip-flop circuit 51 that uses a CONT1W signal, which will be described later, as an input signal. ▲
And a counter 52 for counting ▼). The count output of the counter 52 (in this embodiment, QB among the outputs QA to QC is used) is a switching signal to the user space (this is a USER signal).
Signal).

FIG. 4A shows an instruction executed in the byte area when the system space is shifted to the user space, and FIG. 5A shows a bus cycle operation timing at the time of executing the instruction.

When an operation mode in which the data interface between the processor bus 10 and the microprocessor 1 is performed in byte units is set, in other words, when a byte area is used in executing an instruction, for example, the microprocessor 1
A series of instructions for switching the operation space from the system space to the user space include a MOVE (move) instruction and an RTE (return exception) instruction. By executing the instructions in that order, the microprocessor 1 Operable according to the program. That is, the MOVE instruction is executed by the microprocessor 1 to access the predetermined address CONT1 of the destination, and when the access of this CONT1 is detected by the space control circuit 5, the CONT1W signal in FIG. Is set to "1", and the number of bus cycles thereafter is counted by the counter 52. US when the specified number of bus cycles is detected
The ER signal is output, and switching from the unstack cycle in the execution of the RTE instruction to the user space is performed. Then, after the execution of the RTE instruction, the execution of the user program is started.

Here, the format of an instruction executed by the microprocessor 1 is, for example, a maximum of one word. Assuming that the designation field of the instruction code and the designation field of the operand are each one byte, the instruction execution in the byte area is performed in byte units. The instruction code and its instruction information are sequentially prefetched into a prefetch buffer in the microprocessor 1 and decoded and executed in word units on a first-in first-out basis. In the example of FIG. 5A, during the execution period of the MOVE instruction, there are two prefetch cycles in byte units and one write cycle for writing the contents of the source register to the destination register.

FIG. 4B shows an instruction executed in the word area when the instruction is moved from the system space to the user space, and FIG. 5B shows a bus cycle operation timing when the instruction is executed.

When an operation mode in which the data interface between the processor bus 10 and the microprocessor 1 is performed in word units is set,
When the MOVE instruction is executed, during this MOVE instruction execution period,
Since the last prefetch cycle indicated by 12 in FIG.
This will interfere with the detection of the predetermined number of bus cycles in 52. That is, despite the small number of prefetch cycles, smooth space control cannot be performed if the same number of bus cycles as in the case of instruction execution in the byte area is counted. For example, switching the system interface 2 to the inactive state and the user interface 8 to the active state is performed.
It is performed in the middle of the RTE instruction. In this embodiment, therefore, an instruction fetch is performed between the MOVE instruction and the RTE instruction, but a NOP (non-operation) instruction having substantially no meaning is inserted, so that a prefetch instruction 13 shown in FIG. 5B is inserted. Cycles are ensured so that the apparent number of bus cycles is equal to that of the instruction execution in the byte area. If the number of bus cycles is equal between the byte area and the word area in this manner, the space control circuit 5 does not need to provide dedicated hardware for adjusting the number of bus cycles, and can perform the conventional counting operation from the system space to the user space. Switching control can be performed. The number of NOP instructions for equalizing the apparent number of bus cycles is appropriately determined according to the format configuration of the instructions executed by the microprocessor 1 and the like.

According to the above embodiment, the following effects can be obtained.

(1) By including the NOP instruction in the instruction executed in the word area, it is possible to adjust the difference in the number of bus cycles between the case of executing the instruction in the byte area and the case of executing the instruction in the word area. In the circuit 5, the space switching control from the system space to the user space can be smoothly performed by the conventional bus cycle counting operation regardless of the byte area and the word area.

(2) Moreover, the adjustment of the number of bus cycles is easily realized by inserting the NOP instruction, and does not require dedicated hardware for adjusting the number of bus cycles. Therefore, an increase in hardware scale and an increase in manufacturing cost do not occur.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and can be variously modified without departing from the gist thereof.

For example, the bus cycle itself may be adjusted by inserting a wait state.

Further, in the above embodiment, the adjustment target is described as the number of bus cycles. However, it indicates the operation state of the microprocessor, and if it is changed by the execution of an instruction, the adjustment is not limited to the number of bus cycles. Can be adjusted. In the above embodiment, the case where the unstack area at the time of space switching is arranged in the user space is described, but the stack area may be the system space.

Further, depending on the system to which the present invention is applied, NOP
The operation state of the processor may be adjusted by inserting or deleting a predetermined instruction such as an instruction, or by changing the number of the instructions.

In the above description, the case where the invention made by the inventor is mainly applied to the emulator which is the background of application has been described. However, the present invention is not limited to this, and a plurality of operation modes are selected. The present invention can be widely applied to a data processing system including a processor that can be executed by a computer.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, since the difference in the operation state according to the operation mode of the processor is adjusted by the execution instruction of the processor, the operation state of the processor can be easily adjusted without increasing the hardware.

[Brief description of the drawings]

FIG. 1 is a block diagram of an emulator to which the method of one embodiment of the present invention is applied, FIG. 2 is an explanatory diagram of a memory map of a microprocessor in the emulator, and FIG. 3 is a block diagram of a main part of a space control circuit in the emulator. FIG. 4A is an explanatory view of an instruction executed in the byte area in the emulator, FIG. 4B is an explanatory view of an instruction executed in the word area in the emulator, and FIG. 5A is an instruction execution shown in FIG. 4A. FIG. 5B is a timing diagram of the bus cycle operation at the time of executing the instruction shown in FIG. 4B. 1 ... microprocessor, 2 ... system interface, 5 ... space control circuit, 6 ... trace memory unit,
7: Break detection circuit, 8: User interface.

 ────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yuji Ota 5-20-1, Kamizuhoncho, Kodaira-shi, Tokyo Inside Musashi Plant of Hitachi, Ltd. (56) References JP-A-63-192139 (JP, A) JP-A-63-255755 (JP, A)

Claims (2)

(57) [Claims] 1. A processor operating state adjusting method for adjusting an operating state of a processor which enables access in a first plurality of bit units and a second plurality of bit units having a smaller number of bits, the method comprising: By causing the processor to fetch an instruction having substantially no meaning during the access in the first plurality of bits, the number of bus cycles in the access in the first plurality of bits is reduced by the second plurality of bits. A processor operating state adjusting method, comprising adjusting the operating state of the processor according to the number of bus cycles in bit-wise access. 2. When a break is detected during an emulation operation by a processor, the user interface is deactivated and the system interface is activated, thereby shifting from the user space to the system space and emulating the processor. While the operation is stopped, the state of the processor bus is monitored, the number of bus cycles is counted based on the occurrence of a predetermined event during the execution of a specific instruction, and when the predetermined bus cycle number is reached, the user interface is activated. A processor operating state adjusting method in a space switching process for shifting from a system space to a user space by deactivating a system interface, wherein a data interface between the processor bus and the processor is provided in a first plurality of bits. Action mode to be performed When the instruction is set in the operation mode, by causing the processor to fetch an instruction having substantially no meaning during the access in the operation mode, the apparent number of bus cycles can be made smaller than that of the first plurality of bits. A processor operating state adjusting method, wherein the operating state of the processor is adjusted according to the number of bus cycles in a second access in units of a plurality of bits having a small number of bits.