JPS6022772B2 - Simulated failure control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a pseudo-fault that causes a temporary or permanent pseudo-fault at a specified location in a data processing device at a specified timing when a specified instruction or microinstruction is executed in the data processing device. This relates to generation control methods.

In data processing equipment, error detection and
It has various fault handling functions such as correction, re-execution, and interrupt.

These fault handling functions are realized by hardware and software, and prevent the effects of faults from spreading, and perform relief processing for temporary or fixed faults. In order to ensure that the failure handling operation is correctly executed when a failure occurs in the data processing device, it is necessary to verify in advance the normality of the failure handling functions of hardware and software.

As an effective means for this purpose, a method has been considered in which a pseudo fault is generated at a designated location of the data processing device, thereby activating a fault handling operation and testing its normality. Conventionally, there are various methods for generating a pseudo failure during operation of a data processing device, such as the following.

A: A method in which a pseudo failure instruction is provided and a trigger is issued to set a failure when the instruction is executed.

B: A method in which an address (instruction address or microinstruction address) at which a fault is to occur is set in advance, and a trigger is issued to set a fault when an instruction equal to the address is executed.

C. A field for generating a pseudo failure is provided in a microinstruction, and the occurrence of a failure is controlled by this field when the microinstruction is executed. However, in methods A and B above, it is necessary to simulate a temporary failure that will result in successful re-execution;
It is also difficult to specify the location and timing of pseudo-failure occurrence.

Furthermore, in the C method, it is necessary to provide a field for controlling the occurrence of a pseudo-failure in the microinstruction, which leads to an increase in hardware. Furthermore, in methods A and C, it is necessary to insert in advance an instruction (or microinstruction) for generating a pseudo-failure into a program in which a failure is to occur, and thus lacks flexibility in pseudo-fault generation control. The present invention has been made to solve the above-mentioned problems, and its purpose is to effectively generate temporary and permanent pseudo-failures during the operation of a data processing device.

Recently, consideration has been given to integrating conventional console functions and maintenance/diagnosis functions and having a sub-processing unit, which is a storage program type information processing unit independent of the data processing unit, perform these functions. However, it is an object of the present invention to utilize the processing functions of the sub-processing device to perform pseudo failure occurrence control. Therefore, the pseudo fault occurrence control method according to the present invention does not require processing such as inserting special instructions into the running program, and can change the pseudo fault occurrence location, timing, etc. at any time depending on the program. It is characterized by flexible control. A detailed explanation will be given below based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a data processing system to which the present invention is applied.

Symbol 1 in the figure represents a data processing device (hereinafter referred to as CPU) that should cause a pseudo failure, and symbol 2 represents a storage program type information processing device (hereinafter referred to as system management device SMP) that is independent of the CPUI. represent. Further, 3 is an instruction address register (mountain R), 4 is a memory (LM), 5 is an address comparison circuit, 6 is a timing generation circuit, 7 is a control flip-flop (SF), 8 is a counter, 9 is a comparison circuit, 10 Fault indication flip-flop (EIF), 1
1 is a mask fault indication flip-flop (MEIF), 1
2 is a stop address register (SAR), 13 is a timing data register (TDR), 14 is an error address register (EAR), 15 is an interface to SMP, 16 is an interface to CPU, 17 is a control unit,
18 is a memory.

SARI2, TDR13, EARl4, address comparison circuit 5, counter 8, comparison circuit 9, and SF7 are added to the CPUI for the purpose of the present invention.
holds the instruction address that causes the pseudo failure, and TDR
13 holds timing data for generating a pseudo failure.

The EAR14 also holds an EIF address for selecting a specific one of the EIF group (EIF display flip-flop) provided in correspondence with the fault detection mechanism, and the address comparison circuit 5 compares the currently executed instruction address and the stop address. In addition, the counter 8 and the comparison circuit 9 control the timing of failure occurrence, and the SF7 controls the operation of the counter 8. In addition, the CPU It is assumed that they have evacuated.

When a failure occurs in the CPUI, the SMP2 analyzes an interrupt from the CPUI and performs necessary failure handling operations. As one of the fault processing functions, the SM circle 2 has a pseudo fault occurrence control function, and the SARI 2 and TDR 1 in the CPU
3. By setting appropriate data in each register of EAR14, pseudo failure occurrence control can be performed. The detailed operation of pseudo failure occurrence control in the data processing system shown in FIG. 1 will be described below.

FIG. 2 is a flowchart showing the operation of the CPUI, and FIG. 3 is a flowchart showing the operation of the SMP2.

Further, FIG. 4 is a time chart showing an example of instruction execution processing in the CPUI. First, the operation of the CPUI will be explained.

Instruction processing in the CPUI can be broadly divided into static size processing (S) and instruction execution processing (E). In the process S, a command is issued, an operand is determined, and an operand is issued. In process E, processes corresponding to each command are executed. Usually, as shown in FIG. 4a, processing B
The processing S of the next instruction is being controlled in advance while it is being executed.
When a branch instruction is executed, advance control may be disrupted as shown in FIG. 4b. Instruction address register (IAR) 3
is transparently updated to the next instruction address to be executed at the beginning of processing E (the beginning of processing S of the next instruction), and the memory (
LM) The command is issued from 4. In this embodiment, the contents of IAR3 are updated at each timing To.
In order for the pseudo failure control operation to be performed in the ZCPUI, the data necessary for the occurrence of the pseudo failure must be transferred from the SMP2 to the SARI 2,
It must be set in each register of TDR13 and EAR14. At this time, the CPUI compares the contents of IAR3 and SARI2 at every timing T of processing S in address comparison circuit 5. When the address contents match, the signal 22 is turned on and the flip-flop (SF) 7 is set. SF7 is provided to control the supply of a timing clock to the counter 8. The counter 8 is incremented every time the timing clock is generated while the SF7 is on.

When the execution of the instruction advances by the number of clocks specified by TDR13 from the timing T, the comparator circuit 9 turns on the signal 26 and forcibly sets the failure indicating flip-flop (EIF) 10 specified by EARl4. . A plurality of EIFs exist in the CPUI corresponding to failure detection mechanisms, and when any one of the EIFs is set, the master failure indication flip-flop (ME') 11 is set.

When MEIF I becomes normal, it stops generating the timing clock, freezes the internal state, and notifies the SMP 2 of the occurrence of a failure using an interrupt signal 29. mountain R3
If the contents of SAR12 and SAR12 do not match at timing T, counter 8 is not activated. In this case, it is checked whether the CPUI is in chain execution mode at the end of instruction execution. The re-execution mode indicates that the CPUI is in the state of re-executing instructions after a failure occurs, and the CPU
It is used to control the operation of the PUI and to notify the SMP 2 of the success of re-execution when a temporary failure is relieved by re-execution. Re-execution mode at the end of instruction execution - If this mode is selected, the timing clock is stopped at the end of instructions and an interrupt is generated to SMP2.

If it is not in execution mode, IAR3 is updated to the next instruction address and processing continues. Next, the operation of the SMP2 when an interrupt request is generated from the CPU will be explained. SM yen 2 is C
When accepting an interrupt request from the PUI, it calls the error handling program (ERP) and passes control. ERP is SMP
The necessary failure processing is executed on the dedicated memory 18 of 2. First, internal information when the CPU clock is stopped is collected as failure information. Next, it is determined whether the accepted interrupt request is due to failure detection or successful re-execution. If the cause of the interrupt is a successful re-execution, the process branches to a temporary failure handling routine within the ERP.

In the temporary failure processing routine, after processing such as collection of failure information, a CPU helistart signal is supplied. At this time, IAR3 is updated to the instruction address to be executed next to the instruction to be re-executed, and processing is restarted. If the cause of the interrupt is failure detection, collect and analyze the failure information,
Determine whether re-execution is possible.

If possible, count up the number of re-executions. The number of re-executions is information used to determine whether the failure is temporary or permanent, and the failure will be detected each time even if the re-execution is performed a pre-specified number of times (N). If so, the ERP determines that the failure is permanent. Next, it is checked whether there is a pseudo-failure request.

In this embodiment, the contents of the pseudo failure mode flipflop set from the control panel of the SMP2 are examined. Determine whether there is a pseudo failure control request. The lined area in FIG. 3a is the processing related to the pseudo-failure repulsion control. The processing contents of pseudo-failure occurrence control include ■temporary failure setting function, ■fixed failure setting function, and ■continuous failure setting control function.

These functions are performed by the SAR12 in the CPUI in the pseudo failure setting routine which is a subroutine of the ERP.
, TDR13, and EARl4, and by specifying the number of times (n) of pseudo failure occurrence. n is a value that does not exceed the specified number of re-executions N, and indicates that a pseudo failure will continue to be set at the same location while re-executing n times. When a pseudo-failure occurrence control request is made, it is checked whether the number of re-executions up to now is greater than n.

If it is equal to or smaller than n, return to step (3) in Figure 3a, and after confirming that the number of re-executions is not greater than N, perform pre-re-execution processing such as restoring information necessary for re-execution, Provides a restart signal to the CPUI. If it is larger than n, the process branches to a pseudo failure setting routine and performs the following processing. The instruction address, timing, and fault display flip-flop address in which a pseudo fault should occur are stored in the CPUI, respectively, in SARI2, TDR13, and EAR1.
4, and also specifies the number of pseudo failure occurrences n. Furthermore, if there is no need to set a pseudo failure, the contents of each of the above registers are reset. Data used for register settings, etc. is stored in advance in the data area of the ERP or in a file used by the ERP. When these processes are completed, the process returns to step (2) in FIG. 3a, and it is checked whether the number of re-executions exceeds N or not.

If the number exceeds N, it is determined that the failure is a fixed failure, and the process branches to a fixed failure handling routine. If N' is equal to or less than 4, after the re-execution pre-processing, a CPU helistart signal is supplied to cause re-execution. The current re-execution ends normally because the pseudo failure setting data has already been updated or reset, and the SMP 2 is notified as a re-execution success interrupt as described above.

Thereafter, when the CPUI receives the SMP2 restart signal, it resumes processing the next instruction address. Therefore, by updating the setting data one after another in the pseudo fault setting routine, it is possible to continuously control the occurrence of pseudo faults.

Further, by specifying the number of pseudo fault occurrences n equal to N, a fixed fault can be simulated. Furthermore, the duration of the temporary failure can be controlled by specifying n. As another embodiment of the present invention, only the processing inside the broken line in FIG. 3a is performed by SMP.
2, and other failure handling functions and re-execution functions are controlled by C.
There is a method of including it in the PUI function.

``Another embodiment is a method in which a microinstruction address is used as a stop address.

- That is, the SMP2 specifies the microinstruction address, microinstruction control timing, and fault display flip-flop address as pseudo fault setting data. A microinstruction usually consists of multiple microfields, and the microoperations corresponding to each field are sequentially controlled by the microinstruction control timing. Therefore, by specifying the micro-instruction control timing, it is possible to cause a pseudo-failure in the hardware corresponding to each micro-operation. 0
As is clear from the above description, the pseudo failure occurrence control method according to the present invention has the following effects.

(1) A temporary or fixed pseudo failure can be set at a specified address of any program running in a data processing device at a specified location in the data processing device layer at a specified timing.

Therefore, it is effective for debugging and confirming the normality of hardware and software that execute fault handling functions. 0
'2) The pseudo-fault setting data (stop address, timing data, fault display flip-flop address) allows fine-grained control of the location and timing of pseudo-fault occurrence.

'3' Continuously set pseudo failure settings by program.
control, and efficient generation of simulated failures.

Furthermore, by specifying the number of re-executions to cause a pseudo failure, the duration of a temporary failure can be controlled. {41 By using a storage program type information processing device that is independent of the conventional data processing device that executes the console function and maintenance diagnosis function, the pseudo-failure occurrence control function can be realized with a small amount of additional hardware. be able to.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of an embodiment of a data processing system to which the present invention is applied, Fig. 2 is a flow chart showing the operation of the data processing device, and Figs. 3a and 3b show control over the occurrence of pseudo faults. FIG. 4 is a flowchart showing the operations of the system management device to be performed, and FIG. 4 is a diagram showing a time chart of command processing. 1...Data processing unit (CPU), 2...System management unit (SMP), 3...Instruction address register (
Mountain R), 4...Memory (LM), 5...Address comparison circuit, 6...Timing generation circuit, 7...Control flip-flop (SF), 8...Counter, 9...Comparison circuit,
10... Fault indication flip-flop (EIF), 11... Master failure indication flip-flop (MEIF), 12... Stop address register (SAR), 1 3... Timing data register (TDR), 1 4... Error address register ( EAR), 15... SMP interface, 16... CPU interface, 17... Control, 18... Memory. Figure O Figure O 2 Figure O 3 (q) Figure O 3 b Figure Fang 4

Claims (1)

[Claims] 1 Register EAR that specifies the location where the pseudo fault is set, register TDR that specifies the timing of the pseudo fault occurrence, register S that specifies the instruction address that causes the pseudo fault to occur.
An apparatus comprising a data processing apparatus having an AR and a storage program type sub-information processing apparatus connected to the data processing apparatus and capable of setting arbitrary values in each of the registers, which is independent of the data processing apparatus, A circuit is provided that compares the instruction address to be executed in the processing device with the contents of the register SAR, and a comparison match in the circuit specifies an instruction that causes a pseudo failure, and the timing indicated by the register TDR in the process of executing the instruction. generates a pseudo fault at the location indicated by the register EAR, and causes an interrupt to the sub information processing device each time the pseudo fault occurs, thereby causing the sub information processing device to perform a pseudo fault at the location indicated by the register EAR, TDR, and SAR. A simulation characterized in that the occurrence of a pseudo failure is simulated by program control of a sub-information processing device and the duration of the pseudo failure is controlled by resetting data for setting the pseudo failure. Failure occurrence control method.