JPH02307224A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH02307224A
JPH02307224A JP12933089A JP12933089A JPH02307224A JP H02307224 A JPH02307224 A JP H02307224A JP 12933089 A JP12933089 A JP 12933089A JP 12933089 A JP12933089 A JP 12933089A JP H02307224 A JPH02307224 A JP H02307224A
Authority
JP
Japan
Prior art keywords
film
groove
insulating film
electrode wiring
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12933089A
Other languages
Japanese (ja)
Inventor
Yasuhito Momotake
百武 康仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12933089A priority Critical patent/JPH02307224A/en
Publication of JPH02307224A publication Critical patent/JPH02307224A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain metal electrode wirings having extremely small grain boundary and uniform orientation by providing a semiconductor substrate, an insulating film formed on the main face side of the substrate, a groove formed on the film, and electrode wirings formed on the groove. CONSTITUTION:A semiconductor substrate 4, an insulating film 5 formed on the main face side of the substrate 4, a groove 6 formed on the film 5, and electrode wirings 10 formed on the groove 6 are provided. The film 5 is formed on the main face of the substrate 4, the groove 6 is formed on the film 5, and a metal film 8 is then formed on the film 5 formed with the groove 6. Then, after the film 8 is annealed by a laser light 9, the film 8 annealed with the laser light is patterned in electrode wirings 10. For example, a wedge-shaped groove 6 is formed on the film 5 by a photochemical process, and the angle formed between the groove 6 and the side face 7 is formed at an angle (54.7 deg.) formed between the face (111) of the face centered cubic lattice of aluminum and the face (-1-11).

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の金属電極配線及びその製造方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a metal electrode wiring of a semiconductor device and a method of manufacturing the same.

=べ従来の技術〕 半導体装置の電極配線材料としてA!とその合金が用い
られてて久しいが、これは以下のような理由に依る。A
!とその合金は、電子伝導率が高い上、P型n型Si双
方のコンタクトにおいて良好なオーミックコンタクトを
形成しやすいこと、写真製版技術により微細加工が容易
であり、表面上に安定な酸化展層を形成することが出来
るので、腐食式れにくいこと、そして安価で、高純度な
薄膜を容易に形成しうること、などがある。
= BACKGROUND TECHNOLOGY A! As an electrode wiring material for semiconductor devices! and its alloys have been used for a long time for the following reasons. A
! and its alloys have high electronic conductivity, are easy to form good ohmic contacts in both P-type and n-type Si contacts, are easy to microfabricate using photolithography, and have a stable oxide layer on the surface. It is possible to form a thin film with high purity, is less likely to corrode, and is inexpensive and can easily form a thin film with high purity.

従来、半導体装置の電極配線に用いられるAI薄iをS
1クエハ上に形成する場合、主にスパッタリング法が用
いられてきた。この方法で形5112されたAI薄膜の
模式断面図を第5図に示す。このようにして形成された
A/薄膜(1)は、単結晶体の集合体からなることはよ
く知られているが、通常用いられるAI′ys膜(1)
の膜厚は、0.5〜2.0.smと非常に薄いノT:、
AI(D結晶粒(2)ノ大きさと、AA!薄!! (1
)の膜厚がほぼ同程度となり、その微細構造は、第5図
に示すように結晶粒(2)がAI薄膜(1)を横断する
形状となっている。なお、結晶粒(2)間は結晶粒界(
8)によシ区別される。また、(4)はS1単結晶から
なる基板、(5)は基板(4)上に形成されたS1酸化
膜等からなる絶縁膜である。
Conventionally, AI thin i used for electrode wiring of semiconductor devices is
When forming on one wafer, sputtering method has mainly been used. A schematic cross-sectional view of an AI thin film shaped 5112 by this method is shown in FIG. It is well known that the A/thin film (1) thus formed is composed of an aggregate of single crystals;
The film thickness is 0.5 to 2.0. sm and very thin T:,
AI (D crystal grain (2) size and AA! Thin!! (1
) have almost the same thickness, and the microstructure has a shape in which crystal grains (2) cross the AI thin film (1), as shown in FIG. Note that there are grain boundaries (
8) It is distinguished by: Further, (4) is a substrate made of S1 single crystal, and (5) is an insulating film made of S1 oxide film or the like formed on substrate (4).

とこるん、近年の半導体装置の進歩はめざましく、高集
積化・微細化が急速に進んでいるが、これにともない電
極配線にも様々な障害が生じてきている。このような障
害の一つに、電流の高密度下で電極配線を使用すること
によるAI原子の移動(エレクトロマイグレーション)
による断線がある。エレクトロマイグレーションでは、
主にAI原子の移動が粒界で起こっていること、平均粒
径が小でいほど、粒界にあるAIの体積が増加し、AI
の移動量が大きくなること、が一般に知られている。
Semiconductor devices have made remarkable progress in recent years, with rapid progress toward higher integration and miniaturization, but this has also led to various problems with electrode wiring. One such obstacle is the movement of AI atoms (electromigration) due to the use of electrode wiring under high current densities.
There is a disconnection due to In electromigration,
The movement of AI atoms mainly occurs at the grain boundaries, and the smaller the average grain size, the more the volume of AI at the grain boundaries increases.
It is generally known that the amount of movement increases.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

前記従来の方法に依る半導体装置の金属電極配線におい
そは、多くの結晶粒界(8)が存在している。。
In the metal electrode wiring of a semiconductor device produced by the conventional method, many grain boundaries (8) are present. .

このため、配線を微細化し大電流密度下で使用する場合
、エレクトロマイグレーションによシ断線する可能性が
極めて高くなっていた。
For this reason, when wiring is miniaturized and used under high current density, the possibility of wire breakage due to electromigration is extremely high.

本発明は、以上のような従来の問題点に鑑みてなてれた
もので、粒界の極めて少ない、かつ配向のそろった金属
電極配線を有する半導体装置及び係る半導体装置の製造
方法を提供することを目的としている。
The present invention was developed in view of the conventional problems as described above, and provides a semiconductor device having extremely few grain boundaries and uniformly oriented metal electrode wiring, and a method for manufacturing such a semiconductor device. The purpose is to

〔課題を解決するための手段〕[Means to solve the problem]

本発明に係る半導体装置は、半導体基板と、前記半導体
基板の主面側に形成された絶縁膜と、前記絶縁膜上に形
成された溝と、前記溝上に形成てれた電極配線とを含ん
でいる。
A semiconductor device according to the present invention includes a semiconductor substrate, an insulating film formed on a main surface side of the semiconductor substrate, a groove formed on the insulating film, and an electrode wiring formed on the groove. I'm here.

本発明に係る半導体装置の製造方法は、半導体基板上の
主面上に絶縁膜を形成する第1工程と、前記絶縁膜上に
溝を形成する第2工程と、前記溝の形成された絶縁膜上
に金属膜を形成する第3工程と、前記金属!inレーザ
光によりアニールする第4工程と、前記レーザ光により
アニールされた前記金属膜を電極配線にパターニングす
る第5工程とを含んでいる。
A method for manufacturing a semiconductor device according to the present invention includes a first step of forming an insulating film on a main surface of a semiconductor substrate, a second step of forming a groove on the insulating film, and an insulating film in which the groove is formed. A third step of forming a metal film on the film, and the metal! The method includes a fourth step of annealing with in-laser light, and a fifth step of patterning the metal film annealed with the laser light into electrode wiring.

〔作用〕[Effect]

本発明によれば、電極配線下地に溝が形成され、前記下
地上に金属膜が形成され、前記金属膜にレーザ光線によ
るアニールがほどこされる。このため、前記レーザ光線
によってアニールをほどこされ念金属膜は、下地上に形
成された溝の影響を受け、配向がそろい、かつ結晶粒の
大きな膜が形成される・・ 〔実施例〕 本発明に係る半導体装置の金属電極配線を形成するため
の流れを、第1−に従い説明する9、第1図(Ajにお
いて、(4)はシリコン単結晶等からなる基板、(5)
は基板(4)上に形成された、例えばシリコン酸化膜か
らなる絶縁膜である。まず、前記絶縁膜(5)を、第1
図(Blに示すように、写真製版技術によりくさび型の
溝(6)を形成する。前記くさび型の溝(6)の側面(
ア)のなす角度は、例えば、アルミニウムの面心立方格
子の(111)面と、  (TT’l)面のなす角度(
54,7°)である。次に第1図(Cjlに示すように
p、l !I(8) k s例えばスパッタリング法に
より所望の膜厚まで形成する。この時、下地となる基板
(1)および絶縁膜(2)は、約300°Cまで加熱さ
れる。次に第1図(DIに示すように、高真空下(〜1
0 Torr以下)において、AI膜(8)にレーザ光
線(9)等を照射することによりアニールをほどこす。
According to the present invention, a groove is formed in an electrode wiring base, a metal film is formed on the base, and the metal film is annealed with a laser beam. For this reason, the metallurgical film annealed by the laser beam is influenced by the grooves formed on the base, and a film with uniform orientation and large crystal grains is formed... [Example] The present invention The flow for forming metal electrode wiring of a semiconductor device related to the semiconductor device will be explained according to No. 1-9.
is an insulating film formed on the substrate (4) and made of, for example, a silicon oxide film. First, the insulating film (5) is
As shown in Figure (Bl), a wedge-shaped groove (6) is formed by photolithography.The side surface of the wedge-shaped groove (6) (
For example, the angle formed by (a) is the angle (
54.7°). Next, as shown in FIG. , to approximately 300°C.Then, as shown in Figure 1 (DI), under high vacuum (~1
0 Torr or less), the AI film (8) is annealed by irradiating it with a laser beam (9) or the like.

前記レーザ光線(9)によるアニール工程をへることに
より、 AI膜(8)は、くでび型の溝(6)の側面(
7)に対して(111)面が平行になるように再配向す
る。次にwc1図(Elに示すように、再配向したAI
膜(8)は写真製版技術により、所望の配線にパターニ
ングされる。
By skipping the annealing process using the laser beam (9), the AI film (8) forms a side surface (
7), the (111) plane is reoriented so that it becomes parallel to it. Next, as shown in wc1 diagram (El), the reoriented AI
The film (8) is patterned into desired wiring by photolithography.

以上の方法により形成されたAI配配線値第2図及び第
3図(Al l (El)で示すように下地の溝(6)
の側面(γ)に(111)面をそろえて形成されるため
、配向のそろった電極配線となる上、従来の電極配線に
存在する粒界はほとんど存在しなくなる。
AI wiring lines formed by the above method (as shown in Figures 2 and 3 (Al), the underlying trench (6)
Since the (111) plane is aligned with the side surface (γ) of the electrode wiring, the electrode wiring is uniformly oriented, and there are almost no grain boundaries present in conventional electrode wiring.

なお、第4図に示すようにこの方法における、下地の絶
縁膜(6)に形成される溝(6)の断面形状は、くさび
型に限定されることはなく、また溝(6)の大きさや、
形成される密度は、その上に形成てれるAI配配線値依
り、変化させることも可能である。
Note that, as shown in FIG. 4, in this method, the cross-sectional shape of the groove (6) formed in the underlying insulating film (6) is not limited to a wedge shape, and the size of the groove (6) Saya,
The density formed can also be changed depending on the value of the AI wiring formed thereon.

さらに、利用される配線材料としては、Ajのみならず
、Ou 、 AjSi 、 A/5iOu 、 AjO
u等にも応用可能である。
Furthermore, the wiring materials used include not only Aj but also Ou, AjSi, A/5iOu, AjO
It is also applicable to u, etc.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、電極配線下地上に溝を形成し、その上
にAtWlを形成したので、レーザアニールすることに
より、結晶粒界の極めて少ない電極配線を形成すること
が可能となる。このため、エレクトロマイグレーション
耐性の非常にすぐれた電極配線を得ることができ、半導
体装置の高信頼度化をはかることができる。
According to the present invention, since a groove is formed on the electrode wiring base and AtWl is formed thereon, it is possible to form an electrode wiring with extremely few grain boundaries by laser annealing. Therefore, electrode wiring with extremely high electromigration resistance can be obtained, and the reliability of the semiconductor device can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係る半導体装置の製造方法の流れを示
した図である。第2図は本発明による一実施例を示した
半導体装置の電極配線の縦断面部分図である。第3図(
A+は第2図の■−■部における断面図である。第3図
5:3)は第3図tA+において6部分をさらに拡大し
た拡大図である。第4図は本発明の他の実施例を示した
斜視図である。第5図は従来の技術による半導体装置の
電極配線の縦断面部分図である。 図において、(4)は基板、(5)は絶縁膜、(6)は
溝、(7)は溝の側面、(8)はアルミ膜、(9)はレ
ーザー光線、叫は電極配線である。 なお、図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a diagram showing the flow of a method for manufacturing a semiconductor device according to the present invention. FIG. 2 is a partial vertical cross-sectional view of electrode wiring of a semiconductor device showing an embodiment of the present invention. Figure 3 (
A+ is a sectional view taken along the line ■-■ in FIG. 2. FIG. 3 5:3) is an enlarged view of the 6th part in FIG. 3 tA+. FIG. 4 is a perspective view showing another embodiment of the present invention. FIG. 5 is a partial vertical cross-sectional view of electrode wiring of a semiconductor device according to the prior art. In the figure, (4) is a substrate, (5) is an insulating film, (6) is a groove, (7) is a side surface of the groove, (8) is an aluminum film, (9) is a laser beam, and (9) is an electrode wiring. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板と、前記半導体基板の主面側に形成さ
れた絶縁膜と、前記絶縁膜上に形成された溝と、前記溝
上に形成された電極配線とを含む半導体装置。
(1) A semiconductor device including a semiconductor substrate, an insulating film formed on the main surface side of the semiconductor substrate, a groove formed on the insulating film, and an electrode wiring formed on the groove.
(2)半導体基板上の主面上に絶縁膜を形成する第1工
程と、前記絶縁膜上に溝を形成する第2工程と、前記溝
の形成された絶縁膜上に金属膜を形成する第3工程と、
前記金属膜をレーザ光によりアニールする第4工程と、
前記レーザ光によりアニールされた前記金属膜を電極配
線にパターニングする第5工程とを含む半導体装置の製
造方法。
(2) A first step of forming an insulating film on the main surface of the semiconductor substrate, a second step of forming a groove on the insulating film, and forming a metal film on the insulating film in which the groove is formed. The third step,
a fourth step of annealing the metal film with laser light;
a fifth step of patterning the metal film annealed by the laser beam into electrode wiring.
JP12933089A 1989-05-23 1989-05-23 Semiconductor device and manufacture thereof Pending JPH02307224A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12933089A JPH02307224A (en) 1989-05-23 1989-05-23 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12933089A JPH02307224A (en) 1989-05-23 1989-05-23 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH02307224A true JPH02307224A (en) 1990-12-20

Family

ID=15006934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12933089A Pending JPH02307224A (en) 1989-05-23 1989-05-23 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH02307224A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06216064A (en) * 1993-01-18 1994-08-05 Nec Corp Al contact structure and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06216064A (en) * 1993-01-18 1994-08-05 Nec Corp Al contact structure and manufacture thereof

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