JP2000353704A - Wiring, indicating device using the same, and manufacture thereof - Google Patents
Wiring, indicating device using the same, and manufacture thereofInfo
- Publication number
- JP2000353704A JP2000353704A JP11163651A JP16365199A JP2000353704A JP 2000353704 A JP2000353704 A JP 2000353704A JP 11163651 A JP11163651 A JP 11163651A JP 16365199 A JP16365199 A JP 16365199A JP 2000353704 A JP2000353704 A JP 2000353704A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- alloy thin
- wiring
- substrate
- substrate temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は配線及びそれを用
いた表示装置並びにそれらの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring, a display device using the same, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】例えば、アクティブマトリクス型の液晶
表示装置には、図７に示すように、走査ライン１及びデ
ータライン２等からなる配線を備えていると共に、走査
ライン１とデータライン２の各交点近傍に画素電極３及
びスイッチング素子としての薄膜トランジスタ４を備え
たものがある。この場合、薄膜トランジスタ４のゲート
電極Ｇは走査ライン１に接続され、ドレイン電極Ｄはデ
ータライン２に接続され、ソース電極Ｓは画素電極３に
接続されている。2. Description of the Related Art For example, as shown in FIG. 7, an active matrix type liquid crystal display device is provided with a wiring composed of a scanning line 1 and a data line 2 and the like. Some include a pixel electrode 3 and a thin film transistor 4 as a switching element near the intersection. In this case, the gate electrode G of the thin film transistor 4 is connected to the scanning line 1, the drain electrode D is connected to the data line 2, and the source electrode S is connected to the pixel electrode 3.
【０００３】次に、図８は図７の薄膜トランジスタ４の
部分の断面図を示したものである。ガラス基板１１の上
面の所定の箇所にはゲート電極Ｇを含む走査ライン１が
形成され、その表面には陽極酸化膜１２が形成され、そ
の上面全体にはゲート絶縁膜１３が形成されている。ゲ
ート絶縁膜１３の上面の所定の箇所でゲート電極Ｇに対
応する部分にはアモルファスシリコンからなる半導体薄
膜１４が形成されている。半導体薄膜１４の上面の中央
部にはブロッキング層１５が形成されている。半導体薄
膜１４及びブロッキング層１５の上面の両側にはｎ+シ
リコンからなるオーミックコンタクト層１６、１７が形
成されている。オーミックコンタクト層１６、１７の各
上面にはドレイン電極Ｄ及びソース電極Ｓが形成されて
いる。また、これら電極Ｄ、Ｓの形成と同時にデータラ
イン２が形成されている。ゲート絶縁膜１３の上面の所
定の箇所には画素電極３がソース電極Ｓに接続されて形
成されている。画素電極１１の所定の部分を除く上面全
体にはパッシベーション膜１８が形成されている。FIG. 8 is a sectional view of the thin film transistor 4 shown in FIG. The scanning line 1 including the gate electrode G is formed at a predetermined position on the upper surface of the glass substrate 11, the anodic oxide film 12 is formed on the surface thereof, and the gate insulating film 13 is formed on the entire upper surface. A semiconductor thin film 14 made of amorphous silicon is formed in a portion corresponding to the gate electrode G at a predetermined location on the upper surface of the gate insulating film 13. A blocking layer 15 is formed at the center of the upper surface of the semiconductor thin film 14. Ohmic contact layers 16 and 17 made of n + silicon are formed on both sides of the upper surfaces of the semiconductor thin film 14 and the blocking layer 15. A drain electrode D and a source electrode S are formed on the upper surfaces of the ohmic contact layers 16 and 17, respectively. The data line 2 is formed simultaneously with the formation of the electrodes D and S. The pixel electrode 3 is formed at a predetermined position on the upper surface of the gate insulating film 13 so as to be connected to the source electrode S. A passivation film 18 is formed on the entire upper surface of the pixel electrode 11 except for a predetermined portion.
【０００４】ところで、走査ライン１やデータライン２
等からなる配線の材料としては、配線の低抵抗化を図る
と共に、耐熱性の向上を図るために、ＮｄとＴｉとを含
有するＡｌ合金を用いることが知られている（特開平１
０−２８４４９３号公報参照）。この場合、Ｎｄ含有率
を０．７５ａｔ％とし、Ｔｉ含有率を０．５ａｔ％とす
ると、抵抗率が８μΩｃｍ程度の低抵抗値となり、また
耐熱性の向上を図ることができるが、Ｎｄ含有率とＴｉ
含有率の合計としては、３．５ａｔ％程度以下（ただ
し、Ｎｄ含有率及びＴｉ含有率は共に０．１ａｔ％以
上）が好ましく、１．５ａｔ％程度以下（ただし、Ｎｄ
含有率及びＴｉ含有率は共に０．１ａｔ％以上）がより
好ましい。By the way, scanning line 1 and data line 2
It is known that as a material of a wiring made of an aluminum alloy containing Nd and Ti, an Al alloy containing Nd and Ti is used in order to reduce the resistance of the wiring and to improve the heat resistance (Japanese Unexamined Patent Publication No.
0-284493). In this case, when the Nd content is 0.75 at% and the Ti content is 0.5 at%, the resistivity becomes a low resistance value of about 8 μΩcm and the heat resistance can be improved. And Ti
The total content is preferably about 3.5 at% or less (however, both the Nd content and the Ti content are 0.1 at% or more), and about 1.5 at% or less (however, Nd
Both the content and the Ti content are preferably 0.1 at% or more).
【０００５】[0005]
【発明が解決しようとする課題】ところで、アクティブ
マトリクス型の液晶表示装置の場合には、ゲート電極Ｇ
を含む走査ライン１上に形成されるゲート絶縁膜１３の
絶縁耐圧が低下しないようにする必要があるが、上記文
献（特開平１０−２８４４９３号公報）では、絶縁耐圧
については考慮されていなかった。この発明の課題は、
絶縁耐圧の向上も図ることができるようにすることであ
る。By the way, in the case of an active matrix type liquid crystal display device, the gate electrode G
It is necessary to prevent the withstand voltage of the gate insulating film 13 formed on the scanning line 1 including the above from lowering. However, the above-mentioned document (Japanese Patent Laid-Open No. 10-284493) does not consider the withstand voltage. . The object of the present invention is to
An object is to improve the withstand voltage.
【０００６】[0006]
【課題を解決するための手段】この発明は、少なくとも
希土類元素を含有するＡｌ合金薄膜を基板上にスパッタ
リング法により基板温度を５０〜１５０℃程度好ましく
は８０〜１３０℃程度として成膜し、この成膜したＡｌ
合金薄膜によって配線を形成するようにしたものであ
る。この発明によれば、少なくとも希土類元素を含有す
るＡｌ合金薄膜を基板上にスパッタリング法により成膜
するときの基板温度を５０〜１５０℃程度好ましくは８
０〜１３０℃程度とすると、絶縁耐圧の向上も図ること
ができる。According to the present invention, an Al alloy thin film containing at least a rare earth element is formed on a substrate by sputtering at a substrate temperature of about 50 to 150 ° C., preferably about 80 to 130 ° C. Al formed
The wiring is formed by an alloy thin film. According to the present invention, when forming an Al alloy thin film containing at least a rare earth element on a substrate by a sputtering method, the substrate temperature is set to about 50 to 150 ° C., preferably 8 to 150 ° C.
When the temperature is about 0 to 130 ° C., the withstand voltage can be improved.
【０００７】[0007]
【発明の実施の形態】本発明者は、まず、図１に示すこ
の発明の一実施形態のように、スパッタリング法によ
り、基板温度を変えて、ガラス基板（透明絶縁基板）２
１上にＡｌ合金薄膜２２を成膜した。この場合、Ａｌ合
金薄膜２２としては、Ａｌ−Ｎｄ−Ｔｉ合金薄膜及びＡ
ｌ−Ｎｄ合金薄膜を共に膜厚３００ｎｍ程度に成膜し
た。また、Ａｌ−Ｎｄ−Ｔｉ合金薄膜の場合には、Ｎｄ
含有率を０．９ａｔ％とし、Ｔｉ含有率を０．６ａｔ％
とした。Ａｌ−Ｎｄ合金薄膜の場合には、Ｎｄ含有率を
１．１ａｔ％とした。成膜条件は、ターゲットとガラス
基板２１との間の間隔を２〜２０ｃｍ程度とし、パワー
を１ｗ／ｃｍ2以上とし、Ａｒ圧力を１〜１０Ｔｏｒｒ
程度とした。BEST MODE FOR CARRYING OUT THE INVENTION First, the inventor of the present invention changed a glass substrate (transparent insulating substrate) 2 by changing a substrate temperature by a sputtering method as in one embodiment of the present invention shown in FIG.
An Al alloy thin film 22 was formed on 1. In this case, the Al alloy thin film 22 includes an Al—Nd—Ti alloy thin film and A
Both l-Nd alloy thin films were formed to a thickness of about 300 nm. In the case of an Al—Nd—Ti alloy thin film, Nd
The content is set to 0.9 at%, and the Ti content is set to 0.6 at%.
And In the case of an Al—Nd alloy thin film, the Nd content was set to 1.1 at%. The film forming conditions are as follows: the distance between the target and the glass substrate 21 is about 2 to 20 cm, the power is 1 w / cm 2 or more, and the Ar pressure is 1 to 10 Torr.
Degree.
【０００８】そして、まず、Ａｌ合金薄膜２２の抵抗率
の成膜時基板温度（スパッタリング法によりＡｌ合金薄
膜２２を成膜するときの基板温度）依存性について調べ
たところ、図２に示す結果が得られた。この図におい
て、四角印はＡｌ−Ｎｄ−Ｔｉ合金薄膜の場合であり、
三角印はＡｌ−Ｎｄ合金薄膜の場合である。いずれの場
合も、成膜時基板温度５０℃以下の特性が図示されてい
ないのは、この温度以下ではＡｌ合金薄膜２２のガラス
基板２１に対する密着性が低下するため、成膜時基板温
度は５０℃程度以上とする必要があることが確認された
ためである。この場合、Ａｌ合金薄膜２２のガラス基板
２１に対する密着性は、８０℃程度以上であるとより確
実であり、より好ましいことも確認されている。First, the dependence of the resistivity of the Al alloy thin film 22 on the substrate temperature at the time of film formation (substrate temperature when the Al alloy thin film 22 is formed by the sputtering method) was examined. The result shown in FIG. Obtained. In this figure, square marks indicate the case of an Al-Nd-Ti alloy thin film,
Triangle marks indicate the case of an Al—Nd alloy thin film. In any case, the characteristics at a substrate temperature of 50 ° C. or less during film formation are not shown because the adhesion of the Al alloy thin film 22 to the glass substrate 21 is reduced below this temperature. This is because it has been confirmed that the temperature needs to be higher than about ° C. In this case, it has been confirmed that the adhesion of the Al alloy thin film 22 to the glass substrate 21 is more preferably about 80 ° C. or more, and it is more preferable.
【０００９】また、図２から明らかなように、いずれの
場合も、成膜時基板温度が５０〜１３０℃程度である
と、抵抗率が１０μΩｃｍ以上で１０．４μΩｃｍ以下
であり、成膜時基板温度が１３０〜１５０℃程度である
と、抵抗率が少し低減し、成膜時基板温度が１５０℃程
度以上であると、抵抗率がさらに低減している。As is apparent from FIG. 2, when the substrate temperature at the time of film formation is about 50 to 130 ° C., the resistivity is 10 μΩcm or more and 10.4 μΩcm or less. When the temperature is about 130 to 150 ° C., the resistivity is slightly reduced, and when the substrate temperature during film formation is about 150 ° C. or more, the resistivity is further reduced.
【００１０】これを考察するに、成膜時基板温度が１３
０℃程度以上になると、Ａｌのマトリクス中にＮｄやＴ
ｉが入りにくくなり、この結果抵抗率が純Ａｌの抵抗率
に近づくものと思われる。ちなみに、５０万倍以上のＴ
ＥＭ（透過型電子顕微鏡）によると、ＮｄやＴｉを含む
小さな粒子の析出が観察された。なお、配線の低抵抗化
の点からすれば、成膜時基板温度は高い方が望ましい
が、後述する絶縁耐圧を考慮すると、成膜時基板温度は
あまり高いと好ましくない。Considering this, the substrate temperature during film formation is 13
At about 0 ° C. or higher, Nd or T
It is considered that i becomes difficult to enter, and as a result, the resistivity approaches the resistivity of pure Al. By the way, T of 500,000 times or more
According to EM (transmission electron microscope), precipitation of small particles containing Nd and Ti was observed. Note that from the viewpoint of reducing the resistance of the wiring, it is desirable that the substrate temperature during film formation be high. However, considering the dielectric strength described below, it is not preferable that the substrate temperature during film formation be too high.
【００１１】次に、示差走査熱量測定（ＤＳＣ）による
熱分析により、成膜時基板温度とＤＳＣピーク開始温度
との関係について調べたところ、図３に示す結果が得ら
れた。この図においても、四角印はＡｌ−Ｎｄ−Ｔｉ合
金薄膜の場合であり、三角印はＡｌ−Ｎｄ合金薄膜の場
合である。ＤＳＣピーク開始温度とは、発熱反応を開始
する温度で、所定温度上昇するのに供給する熱量が最も
大きくなる温度のことである。このＤＳＣピーク開始温
度は、Ａｌ−Ｎｄ−Ｔｉ合金薄膜の場合、ヒロックの発
生温度と一致し、Ａｌ−Ｎｄ合金薄膜の場合、Ａｌ4Ｎ
ｄの析出温度と一致する。Next, the relationship between the substrate temperature during film formation and the DSC peak start temperature was examined by thermal analysis by differential scanning calorimetry (DSC), and the results shown in FIG. 3 were obtained. Also in this figure, the square marks indicate the case of the Al-Nd-Ti alloy thin film, and the triangle marks indicate the case of the Al-Nd alloy thin film. The DSC peak start temperature is a temperature at which an exothermic reaction starts, and is a temperature at which the amount of heat supplied to increase by a predetermined temperature becomes the largest. The DSC peak onset temperature coincides with the hillock generation temperature in the case of the Al—Nd—Ti alloy thin film, and the Al 4 N in the case of the Al—Nd alloy thin film.
It matches the deposition temperature of d.
【００１２】そして、図３から明らかなように、いずれ
の場合も、成膜時基板温度が５０〜１３０℃程度である
と、ＤＳＣピーク開始温度がほぼ一定であり、成膜時基
板温度が１３０〜１５０℃程度であると、ＤＳＣピーク
開始温度がやや低下し、成膜時基板温度が１５０℃程度
以上であると、ＤＳＣピーク開始温度がさらに低下して
いる。したがって、成膜時基板温度が１３０〜１５０℃
程度であると、Ａｌ−Ｎｄ−Ｔｉ合金薄膜の場合、ヒロ
ックがやや発生し、Ａｌ−Ｎｄ合金薄膜の場合、Ａｌ4
Ｎｄがやや析出するが、いずれの場合も、耐熱性が問題
となるほど低下することはない。これに対して、成膜時
基板温度が１５０℃程度以上であると、Ａｌ−Ｎｄ−Ｔ
ｉ合金薄膜の場合、ヒロックがかなり発生し、Ａｌ−Ｎ
ｄ合金薄膜の場合、Ａｌ4Ｎｄがかなり析出することと
なり、いずれの場合も、耐熱性が低下することになる。
また、Ａｌのマトリクス中のＮｄやＴｉの実質的な量が
減少し、耐腐食性も低下することになる。As is apparent from FIG. 3, in any case, when the substrate temperature during film formation is about 50 to 130 ° C., the DSC peak start temperature is substantially constant, and the substrate temperature during film formation is 130 ° C. When the temperature is about 150 ° C., the DSC peak start temperature is slightly lowered, and when the film forming substrate temperature is about 150 ° C. or higher, the DSC peak start temperature is further lowered. Therefore, the substrate temperature during film formation is 130 to 150 ° C.
In the case of Al-Nd-Ti alloy thin film, hillocks are slightly generated, and in the case of Al-Nd alloy thin film, Al 4
Nd is slightly precipitated, but in any case, the heat resistance does not decrease so much as to be a problem. On the other hand, when the substrate temperature during film formation is about 150 ° C. or higher, the Al—Nd—T
In the case of the i-alloy thin film, hillocks are considerably generated and Al-N
In the case of a d-alloy thin film, Al 4 Nd is considerably precipitated, and in any case, the heat resistance is reduced.
Further, the substantial amounts of Nd and Ti in the Al matrix are reduced, and the corrosion resistance is also reduced.
【００１３】次に、成膜時基板温度と絶縁耐圧との関係
について説明する。まず、成膜時基板温度と中心線平均
粗さＲａ（粒径に相当）との関係について調べたとこ
ろ、図４に示す結果が得られた。この図においても、四
角印はＡｌ−Ｎｄ−Ｔｉ合金薄膜の場合であり、三角印
はＡｌ−Ｎｄ合金薄膜の場合である。図４から明らかな
ように、いずれの場合も、第１に、成膜時基板温度が５
０〜１３０℃程度であると、中心線平均粗さＲａが２．
５〜５ｎｍ程度であり、成膜時基板温度が１３０℃程度
以上になると、中心線平均粗さＲａがそれ以上に大きく
なることが分かる。第２に、成膜時基板温度が５０〜１
５０℃程度であると、中心線平均粗さＲａが２．５〜１
０ｎｍ程度であるが、成膜時基板温度が１５０℃程度以
上になると、中心線平均粗さＲａがそれ以上に大きくな
ることが分かる。Next, the relationship between the substrate temperature during film formation and the withstand voltage will be described. First, when the relationship between the substrate temperature during film formation and the center line average roughness Ra (corresponding to the particle size) was examined, the results shown in FIG. 4 were obtained. Also in this figure, the square marks indicate the case of the Al-Nd-Ti alloy thin film, and the triangle marks indicate the case of the Al-Nd alloy thin film. As is clear from FIG. 4, in each case, first, the substrate temperature during film formation was 5
When the temperature is about 0 to 130 ° C., the center line average roughness Ra is 2.
It is about 5 to 5 nm, and it is understood that when the substrate temperature at the time of film formation becomes about 130 ° C. or more, the center line average roughness Ra becomes larger. Second, the substrate temperature during film formation is 50 to 1
When the temperature is about 50 ° C., the center line average roughness Ra is 2.5 to 1
Although it is about 0 nm, it can be seen that when the substrate temperature during film formation is about 150 ° C. or more, the center line average roughness Ra is further increased.
【００１４】これを考察するに、成膜時基板温度が特に
１５０℃程度以上になると、Ａｌのマトリクス中にＮｄ
やＴｉが入りにくくなるだけでなく、ＮｄやＴｉを含む
粒が成長し、Ａｌ合金薄膜２２を構成する粒子の径が大
きくなり、ひいてはＡｌ合金薄膜２２の表面粗さが粗く
なり、次に述べるように、絶縁耐圧が低下するものと思
われる。Considering this fact, when the substrate temperature during film formation particularly becomes about 150 ° C. or more, Nd is contained in the Al matrix.
In addition to making it difficult for Ti and Ti to enter, grains containing Nd and Ti grow, the diameter of the particles constituting the Al alloy thin film 22 increases, and the surface roughness of the Al alloy thin film 22 becomes coarse. Thus, it is considered that the dielectric strength is reduced.
【００１５】次に、図５に示すように、ガラス基板２１
上に成膜した膜厚３００ｎｍ程度のＡｌ合金薄膜２２の
表面に膜厚１００ｎｍ程度の陽極酸化膜２３を形成し、
次いでプラズマＣＶＤ法により窒化シリコンからなる絶
縁膜２４を膜厚２００ｎｍ程度に成膜し、次いでその上
面に電極２５を形成し、そして電極２５とＡｌ合金薄膜
２２との間の絶縁耐圧を測定したところ、図６に示す結
果が得られた。この図においても、四角印はＡｌ−Ｎｄ
−Ｔｉ合金薄膜の場合であり、三角印はＡｌ−Ｎｄ合金
薄膜の場合である。ただし、この場合の絶縁耐圧は、１
０％以上が絶縁不良となる電圧とした。Next, as shown in FIG.
An anodic oxide film 23 having a thickness of about 100 nm is formed on the surface of the Al alloy thin film 22 having a thickness of about 300 nm formed thereon,
Next, an insulating film 24 made of silicon nitride was formed to a thickness of about 200 nm by a plasma CVD method, then an electrode 25 was formed on the upper surface thereof, and the withstand voltage between the electrode 25 and the Al alloy thin film 22 was measured. The result shown in FIG. 6 was obtained. Also in this figure, the square mark is Al-Nd
-It is the case of the Ti alloy thin film, and the triangle mark is the case of the Al-Nd alloy thin film. However, the dielectric strength in this case is 1
The voltage at which 0% or more causes insulation failure is set.
【００１６】図６から明らかなように、いずれの場合
も、成膜時基板温度が５０〜１３０℃程度であると、絶
縁耐圧が５０Ｖ以上であり、成膜時基板温度が１３０〜
１５０℃程度であると、絶縁耐圧が４０Ｖ以上である
が、成膜時基板温度が１５０℃以上になると、絶縁耐圧
が４０Ｖ以下に低下している。したがって、成膜時基板
温度は、絶縁耐圧を考慮すると、１５０℃程度以下が好
ましく、１３０℃程度以下がより好ましい。As is apparent from FIG. 6, in any case, when the substrate temperature during film formation is about 50 to 130 ° C., the withstand voltage is 50 V or more, and the substrate temperature during film formation is 130 to 130 ° C.
When the temperature is about 150 ° C., the withstand voltage is 40 V or more. However, when the substrate temperature during film formation is 150 ° C. or more, the withstand voltage is reduced to 40 V or less. Therefore, the substrate temperature during film formation is preferably about 150 ° C. or less, more preferably about 130 ° C. or less, in consideration of the dielectric strength.
【００１７】以上のことをまとめると、成膜時基板温度
は、Ａｌ合金薄膜２２のガラス基板２１に対する密着性
を考慮すると、５０℃程度以上が好ましく、８０℃程度
以上がより好ましい。また、絶縁耐圧を考慮すると、１
５０℃程度以下が好ましく、１３０℃程度以下がより好
ましい。したがって、成膜時基板温度は、５０〜１５０
℃程度が好ましく、５０〜１３０℃程度あるいは８０〜
１５０℃程度がより好ましく、８０〜１３０℃程度がさ
らに好ましい。ところで、成膜時基板温度を５０〜１５
０℃程度としても、図２に示すように、抵抗率が１０．
４μΩｃｍ以下となるので、配線の低抵抗化を図ること
ができる。To summarize the above, the substrate temperature during film formation is preferably about 50 ° C. or higher, more preferably about 80 ° C. or higher, in consideration of the adhesion of the Al alloy thin film 22 to the glass substrate 21. Considering the dielectric strength, 1
The temperature is preferably about 50 ° C. or less, more preferably about 130 ° C. or less. Therefore, the substrate temperature during film formation is 50 to 150
C. is preferable, and about 50-130 C. or 80-C.
About 150 ° C is more preferable, and about 80 to 130 ° C is more preferable. By the way, the substrate temperature during film formation is set to 50 to 15
Even at about 0 ° C., as shown in FIG.
Since the resistance is 4 μΩcm or less, the resistance of the wiring can be reduced.
【００１８】なお、上記説明では、ガラス基板上にＡｌ
合金薄膜からなる配線を形成する場合について説明した
が、ガラス基板上に酸化シリコンや窒化シリコン等から
なる絶縁膜を形成し、その上にＡｌ合金薄膜からなる配
線を形成するようにしてもよい。また、走査ラインに限
らず、データラインをＡｌ合金薄膜からなる配線によっ
て形成するようにしてもよい。また、ガラス基板に限ら
ず、例えば半導体基板上にＡｌ合金薄膜からなる配線を
形成するようにしてもよい。Note that, in the above description, Al is placed on the glass substrate.
Although the case of forming the wiring made of the alloy thin film has been described, an insulating film made of silicon oxide or silicon nitride may be formed on a glass substrate, and the wiring made of the Al alloy thin film may be formed thereon. Further, the data line is not limited to the scan line, and the data line may be formed by a wiring made of an Al alloy thin film. In addition, not limited to the glass substrate, for example, a wiring made of an Al alloy thin film may be formed on a semiconductor substrate.
【００１９】さらに、Ａｌ−Ｎｄ合金薄膜に限らず、希
土類元素のうちの１種または２種以上を含有するＡｌ合
金薄膜によって配線を形成するようにしてもよい。ま
た、Ａｌ−Ｎｄ−Ｔｉ合金薄膜に限らず、希土類元素の
うちの１種または２種以上とＴｉ、Ｔａ、Ｍｏ、Ｃｒ、
Ａｕ、Ａｇ、Ｃｕのうちの１種または２種以上とを含有
するＡｌ合金薄膜によって配線を形成するようにしても
よい。Further, the wiring may be formed not only by the Al-Nd alloy thin film but also by an Al alloy thin film containing one or more rare earth elements. Further, not limited to the Al-Nd-Ti alloy thin film, one or more of the rare earth elements may be combined with Ti, Ta, Mo, Cr,
The wiring may be formed by an Al alloy thin film containing one or more of Au, Ag, and Cu.
【００２０】[0020]
【発明の効果】以上説明したように、この発明によれ
ば、少なくとも希土類元素を含有するＡｌ合金薄膜を基
板上にスパッタリング法により成膜するときの基板温度
を５０〜１５０℃程度好ましくは８０〜１３０℃程度と
すると、絶縁耐圧の向上も図ることができる。As described above, according to the present invention, the substrate temperature when forming an Al alloy thin film containing at least a rare earth element on a substrate by sputtering is about 50 to 150 ° C., preferably 80 to 150 ° C. When the temperature is about 130 ° C., the withstand voltage can be improved.
【図１】この発明の一実施形態における配線の断面図。FIG. 1 is a sectional view of a wiring according to an embodiment of the present invention.
【図２】Ａｌ合金薄膜の抵抗率の成膜時基板温度依存性
を示す図。FIG. 2 is a graph showing the substrate temperature dependence of the resistivity of an Al alloy thin film during film formation.
【図３】成膜時基板温度とＤＳＣピーク開始温度との関
係を示す図。FIG. 3 is a diagram showing a relationship between a substrate temperature during film formation and a DSC peak start temperature.
【図４】成膜時基板温度と中心線平均粗さＲａとの関係
を示す図。FIG. 4 is a diagram showing a relationship between a substrate temperature during film formation and a center line average roughness Ra.
【図５】絶縁耐圧を測定するために用意した試料の断面
図。FIG. 5 is a sectional view of a sample prepared for measuring a dielectric strength.
【図６】成膜時基板温度と絶縁耐圧との関係を示す図。FIG. 6 is a diagram showing a relationship between a substrate temperature during film formation and a withstand voltage.
【図７】従来の液晶表示装置の一部の回路図。FIG. 7 is a circuit diagram of a part of a conventional liquid crystal display device.
【図８】図７の薄膜トランジスタの部分の断面図。FIG. 8 is a cross-sectional view of a portion of the thin film transistor of FIG. 7;
２１ ガラス基板 ２２ Ａｌ合金薄膜 21 Glass substrate 22 Al alloy thin film
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 2H092 GA26 HA06 MA05 NA11 4K029 AA09 BA23 BD00 CA05 5F033 GG04 HH09 LL09 PP15 RR03 RR06 SS15 SS26 TT02 VV06 VV15 WW03 XX08 XX13 XX16 5F110 AA03 AA12 BB01 CC07 DD02 DD13 DD14 EE06 EE44 FF01 FF03 FF09 FF24 FF30 GG02 GG15 HK09 HK21 NN01 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2H092 GA26 HA06 MA05 NA11 4K029 AA09 BA23 BD00 CA05 5F033 GG04 HH09 LL09 PP15 RR03 RR06 SS15 SS26 TT02 VV06 VV15 WW03 XX08 XX13 XX16 5F110 AA03 FF01 DD03 DD01 FF09 FF24 FF30 GG02 GG15 HK09 HK21 NN01
Claims (16)
平均粗さＲａが２．５〜１０ｎｍ程度であるＡｌ合金薄
膜からなることを特徴とする配線。1. A wiring comprising an Al alloy thin film containing at least a rare earth element and having a center line average roughness Ra of about 2.5 to 10 nm.
合金薄膜はＮｄを含有するものであることを特徴とする
配線。2. The method according to claim 1, wherein the Al
A wiring characterized in that the alloy thin film contains Nd.
合金薄膜はＮｄとＴｉとを含有するものであることを特
徴とする配線。3. The method according to claim 1, wherein the Al
A wiring characterized in that the alloy thin film contains Nd and Ti.
絶縁基板の少なくとも一方の内面側に形成された配線と
を有し、前記配線の少なくとも一部を、少なくとも希土
類元素を含有し、中心線平均粗さＲａが２．５〜１０ｎ
ｍ程度であるＡｌ合金薄膜によって形成したことを特徴
とする表示装置。4. A semiconductor device comprising: a pair of transparent insulating substrates; and a wiring formed on an inner surface of at least one of the pair of transparent insulating substrates, wherein at least a part of the wiring contains at least a rare earth element, and has a center. Line average roughness Ra is 2.5 to 10 n
A display device formed of an Al alloy thin film having a thickness of about m.
絶縁基板の内面側にスイッチング素子及び該スイッチン
グ素子に接続された画素電極がマトリクス状に形成さ
れ、前記配線は前記スイッチング素子を接続する走査ラ
インまたはデータラインであることを特徴とする表示装
置。5. The switching device according to claim 4, wherein switching elements and pixel electrodes connected to the switching elements are formed in a matrix on an inner surface side of the transparent insulating substrate, and the wiring is a scan for connecting the switching elements. A display device, which is a line or a data line.
前記Ａｌ合金薄膜はＮｄを含有するものであることを特
徴とする表示装置。6. The invention according to claim 4, wherein
The display device, wherein the Al alloy thin film contains Nd.
前記Ａｌ合金薄膜はＮｄとＴｉとを含有するものである
ことを特徴とする表示装置。7. The method according to claim 4, wherein
The display device, wherein the Al alloy thin film contains Nd and Ti.
金薄膜を基板上にスパッタリング法により基板温度を５
０〜１５０℃程度として成膜し、この成膜したＡｌ合金
薄膜によって配線を形成することを特徴とする配線の製
造方法。8. An Al alloy thin film containing at least a rare earth element is formed on a substrate by sputtering at a substrate temperature of 5 ° C.
A method for manufacturing a wiring, comprising forming a film at a temperature of about 0 to 150 ° C. and forming a wiring using the formed Al alloy thin film.
金薄膜を基板上にスパッタリング法により基板温度を８
０〜１３０℃程度として成膜し、この成膜したＡｌ合金
薄膜によって配線を形成することを特徴とする配線の製
造方法。9. An Al alloy thin film containing at least a rare earth element is formed on a substrate by sputtering at a substrate temperature of 8 ° C.
A method for manufacturing a wiring, comprising forming a film at about 0 to 130 [deg.] C. and forming a wiring by using the formed Al alloy thin film.
て、前記Ａｌ合金薄膜はＮｄを含有するものであること
を特徴とする配線の製造方法。10. The method according to claim 8, wherein the Al alloy thin film contains Nd.
て、前記Ａｌ合金薄膜はＮｄとＴｉとを含有するもので
あることを特徴とする配線の製造方法。11. The method according to claim 8, wherein the Al alloy thin film contains Nd and Ti.
明絶縁基板の少なくとも一方の内面側に形成された配線
とを有する表示装置の製造に際し、少なくとも希土類元
素を含有するＡｌ合金薄膜を前記一方の透明絶縁基板の
内面側にスパッタリング法により基板温度を５０〜１５
０℃程度として成膜し、この成膜したＡｌ合金薄膜によ
って前記配線の少なくとも一部を形成することを特徴と
する表示装置の製造方法。12. When manufacturing a display device having a pair of transparent insulating substrates and wiring formed on at least one inner surface side of the pair of transparent insulating substrates, an Al alloy thin film containing at least a rare earth element is formed on the one side. The substrate temperature was set to 50 to 15 on the inner surface side of the transparent insulating substrate by sputtering.
A method for manufacturing a display device, comprising: forming a film at about 0 ° C .; and forming at least a part of the wiring by using the formed Al alloy thin film.
明絶縁基板の少なくとも一方の内面側に形成された配線
とを有する表示装置の製造に際し、少なくとも希土類元
素を含有するＡｌ合金薄膜を前記一方の透明絶縁基板の
内面側にスパッタリング法により基板温度を８０〜１３
０℃程度として成膜し、この成膜したＡｌ合金薄膜によ
って前記配線の少なくとも一部を形成することを特徴と
する表示装置の製造方法。13. When manufacturing a display device having a pair of transparent insulating substrates and wiring formed on at least one inner surface of the pair of transparent insulating substrates, an Al alloy thin film containing at least a rare earth element is removed from the one of the transparent insulating substrates. The substrate temperature was set to 80 to 13 on the inner surface side of the transparent insulating substrate by sputtering.
A method for manufacturing a display device, comprising: forming a film at about 0 ° C .; and forming at least a part of the wiring by using the formed Al alloy thin film.
いて、前記透明絶縁基板の内面側にスイッチング素子及
び該スイッチング素子に接続された画素電極がマトリク
ス状に形成され、前記配線は前記スイッチング素子を接
続する走査ラインまたはデータラインであることを特徴
とする表示装置の製造方法。14. The switching element according to claim 12, wherein switching elements and pixel electrodes connected to the switching elements are formed in a matrix on an inner surface side of the transparent insulating substrate, and the wiring connects the switching elements. A method of manufacturing a display device, comprising: a scanning line or a data line.
発明において、前記Ａｌ合金薄膜はＮｄを含有するもの
であることを特徴とする表示装置の製造方法。15. The method according to claim 12, wherein the Al alloy thin film contains Nd.
発明において、前記Ａｌ合金薄膜はＮｄとＴｉとを含有
するものであることを特徴とする表示装置の製造方法。16. The method according to claim 12, wherein the Al alloy thin film contains Nd and Ti.
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|---|---|---|---|
| JP16365199A JP4674774B2 (en) | 1999-06-10 | 1999-06-10 | Wiring manufacturing method and display device manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16365199A JP4674774B2 (en) | 1999-06-10 | 1999-06-10 | Wiring manufacturing method and display device manufacturing method |
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| Publication Number | Publication Date |
|---|---|
| JP2000353704A true JP2000353704A (en) | 2000-12-19 |
| JP4674774B2 JP4674774B2 (en) | 2011-04-20 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7633580B2 (en) | 2001-03-29 | 2009-12-15 | Nec Lcd Technologies, Ltd. | Liquid crystal display panel having reflection electrodes improved in smooth surface morphology and process for fabrication thereof |
| KR101018757B1 (en) | 2003-09-18 | 2011-03-04 | 삼성전자주식회사 | Manufacturing method of thin film transistor array panel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10209160A (en) * | 1997-01-21 | 1998-08-07 | Casio Comput Co Ltd | Wiring and display using the same |
| JPH10284493A (en) * | 1997-04-04 | 1998-10-23 | Casio Comput Co Ltd | Interconnection and display apparatus using the same |
| JP2000314897A (en) * | 1999-05-06 | 2000-11-14 | Hitachi Ltd | Liquid crystal display device |
-
1999
- 1999-06-10 JP JP16365199A patent/JP4674774B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10209160A (en) * | 1997-01-21 | 1998-08-07 | Casio Comput Co Ltd | Wiring and display using the same |
| JPH10284493A (en) * | 1997-04-04 | 1998-10-23 | Casio Comput Co Ltd | Interconnection and display apparatus using the same |
| JP2000314897A (en) * | 1999-05-06 | 2000-11-14 | Hitachi Ltd | Liquid crystal display device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7633580B2 (en) | 2001-03-29 | 2009-12-15 | Nec Lcd Technologies, Ltd. | Liquid crystal display panel having reflection electrodes improved in smooth surface morphology and process for fabrication thereof |
| KR101018757B1 (en) | 2003-09-18 | 2011-03-04 | 삼성전자주식회사 | Manufacturing method of thin film transistor array panel |
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| Publication number | Publication date |
|---|---|
| JP4674774B2 (en) | 2011-04-20 |
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