JP2819821B2 - Method for manufacturing thin film semiconductor device - Google Patents

Description

The present invention relates to an active matrix display,
The present invention relates to a thin-film semiconductor device used for driving an image sensor, a print head, and the like, and more particularly, to a method for manufacturing a thin-film semiconductor device capable of increasing operating speed.

[Conventional technology]

As a thin film semiconductor device of this type, a MOS thin film transistor will be described as an example. As shown in FIGS. 9 to 10, a glass substrate (g) and a gate formed on the glass substrate (g) are formed. Electrode (gt) and this gate electrode (gt)
A gate insulating film (h), a semiconductor layer (j) of amorphous silicon laminated on the gate insulating film (h), and a protective film (k) provided on the semiconductor layer (j).
And a source electrode (st) and a drain electrode (dt) provided on both ends of the semiconductor layer (j) via an ohmic contact formation layer (m) of n ⁺ -amorphous silicon, to constitute a main part thereof. As shown in FIGS. 11 and 12, a glass substrate (g), an amorphous silicon semiconductor layer (j) provided on the glass substrate (g), and n ⁺ A source electrode (st) and a drain electrode (dt) provided at both ends of the semiconductor layer (j) via an ohmic contact formation layer (m) of amorphous silicon; and a source electrode (st) and a drain electrode thereof. (Dt), a signal wiring (n), a gate insulating film (h) covering the semiconductor layer (j), a gate electrode (gt) provided on the gate insulating film (h), and the like. It is called the “stagger type” that constitutes the main part Etc. have been known.

In these MOS type thin film transistors, a drain voltage (V _D ) is applied between the source electrode (st) and the drain electrode (dt), and a gate electrode (gt)
When a gate voltage (V _G ) is applied to the semiconductor layer (j), a channel is formed in the semiconductor layer (j), the transistor is turned on, and a drain current (I _D ) flows, while the gate voltage (V _G ) is reduced. Accordingly, a channel is not formed in the semiconductor layer (j), the transistor is turned off, and the drain current ( _ID ) does not flow, and is used for driving the above-described active matrix display, image sensor, and the like. It is.

By the way, when manufacturing this type of thin film semiconductor device, first wiring portions such as a gate electrode (gt), a source electrode (st) and a drain electrode (dt), and a signal wiring (n) which are formed first. Needs to be made of a conductive material having excellent heat-resistance, which is excellent in adhesion to an insulating substrate such as the glass substrate (g) and hardly deteriorates in a heat treatment in a subsequent step. Tantalum (T
a), molybdenum (Mo), titanium (Ti), and chromium (C
Metal materials having a high melting point such as r) are used, and in particular, tantalum which has excellent electric corrosion resistance and can improve the breakdown voltage with the formation of the anodic oxide film is widely used among these materials.

However, when a tantalum thin film is formed on an insulating substrate such as a glass substrate by a sputtering method, this tantalum thin film has a drawback that it becomes β-tantalum having a tetragonal structure and a high resistance value and has a drawback. The delay of the signal based on the resistance becomes remarkable, which has been a serious problem in increasing the operation speed of the semiconductor device.

On the other hand, Ta-, whose conductivity is better than β-tantalum,
Tantalum alloys such as W and Ta-Mo are also used in some cases, but when this tantalum alloy is applied to a gate electrode or the like, there is a drawback that even if an anodic oxide film is formed, it does not contribute to the improvement in withstand voltage. There was a disadvantage that the conductivity was inferior to that of α-tantalum.

Under such a technical background, the present inventor can increase the operation speed by making it possible to deposit α-tantalum, which has a lower resistance value than β-tantalum or a tantalum alloy, on the insulating substrate surface. Have already provided thin film semiconductor devices.

That is, as shown in FIG. 13, this technical means is to convert a first wiring portion such as a gate electrode (gt) into a conductive material having a body-centered cubic lattice structure and having the same or similar lattice constant as α-tantalum. A substrate-side wiring base (a) formed of a conductive material (for example, TaMo alloy or TaW alloy), and a tantalum laminated wiring portion (b) laminated on the substrate-side wiring base (a). Wherein the laminated wiring portion (b) laminated on the substrate-side wiring base (a) inherits the body-centered cubic lattice structure of the substrate-side wiring base (a) and grows to form β-tantalum. Since it is composed of α-tantalum having a body-centered cubic lattice structure without an insulator, an insulating substrate (g)
This is a means capable of providing a thin film semiconductor device in which the conductivity of a first wiring portion such as a gate electrode (gt) provided in surface contact with the surface is improved and the operation speed is increased.

By the way, when the first wiring portion such as the gate electrode is formed by applying this technical means, it is usually performed by the following sputtering method using a Ta target and a Mo or W target.

That is, as shown in FIG. 14 (A), a TaMo alloy (TaMo) having a body-centered cubic lattice structure and having a lattice constant similar to that of α-tantalum is deposited on a glass substrate (g) as shown in FIG. A film is formed to a predetermined thickness by a sputtering method according to a film speed condition.

Next, as shown in FIG. 15, after temporarily stopping the sputtering by setting the deposition rate of Ta and Mo to 0, sputtering was performed again with only the deposition rate of Ta increased as shown in FIG. As shown in FIG. 14 (B), a TaMo alloy (TaMo)
A film of tantalum (Ta) having a predetermined thickness is formed thereon. In this case, the tantalum (Ta) grows while inheriting the body-centered cubic lattice structure of the TaMo alloy (TaMo) and becomes α-tantalum.

Then, a laminated film of a TaMo alloy (TaMo) and tantalum (Ta) is patterned, and a substrate-side wiring base (a) of TaMo metal and a laminated wiring portion of α-tantalum (b) as shown in FIG. 14 (C). A first wiring portion (t) such as a gate electrode composed of
Was formed.

[Problems to be solved by the invention]

However, when the first wiring portion (t) is formed in accordance with the above-described "two-stage deposition method" of forming a TaMo alloy (TaMo), temporarily stopping sputtering, and then forming tantalum (Ta) again, At the interface between TaMo alloy (TaMo) and tantalum (Ta), the crystal structure is distorted due to the difference in lattice constant between the two, and the conductivity of the tantalum (Ta) distorted portion is reduced. was there.

The strain between the TaMo alloy (TaMo) and tantalum (Ta) is gradually reduced as the thickness of the tantalum (Ta) increases, and as shown in FIG. 16, the strain varies depending on the thickness of the tantalum (Ta). Since the resistance value is reduced, it is possible to prevent a decrease in conductivity by setting a large thickness of tantalum (Ta) laminated on a TaMo alloy (TaMo).

However, in order to obtain the desired conductivity, the thickness of tantalum (Ta) must be set to a large value, which is contrary to the demand for flattening in a thin film semiconductor device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object a thin film capable of obtaining a desired conductivity without setting a large thickness of tantalum (Ta) in a first wiring portion. An object of the present invention is to provide a method for manufacturing a semiconductor device.

[Means for solving the problem]

That is, the present invention provides an insulating substrate, a semiconductor layer provided on the insulating substrate, and a TaMo (tantalum molybdenum) alloy or TaW
The above-described TaMo alloy or TaW alloy is premised on a method of manufacturing a thin film semiconductor device comprising: a substrate-side wiring base of a (tantalum tungsten) alloy and a first wiring portion comprising a stacked wiring portion of Ta (tantalum) laminated thereon. A first film forming step of forming the substrate-side wiring base film by sputtering, and a method of continuously lowering the deposition rate of Mo (molybdenum) or W (tungsten) forming the substrate-side wiring base film. The TaMo alloy or TaW alloy intermediate film whose Mo or W content is continuously reduced in the film deposition direction by continuously increasing the Ta film deposition rate is used for the substrate side wiring base by sputtering. A second film forming step of continuously forming a film on the film, and a third film forming step of continuously forming a film for a laminated wiring portion of Ta on the intermediate film by a sputtering method. What is characteristic That.

In such technical means, glass, quartz, ceramics, and the like can be used as a material constituting the insulating substrate as in the past, and as a material constituting the semiconductor layer provided on the insulating substrate, Is polysilicon (po
For example, ly-Si) or amorphous silicon (a-Si: H) can be used.

In addition, in the first film forming step, as a sputtering method for forming a film for a substrate-side wiring base of a TaMo alloy or a TaW alloy, a Ta target and a Mo target or a Ta target and a W target are used, and the amount of power applied to each target is adjusted. And set it to a predetermined deposition rate,
In addition to the simultaneous sputtering for synthesizing the TaW alloy and forming a film at the same time, the sputtering can be performed using a single target corresponding to the target TaMo alloy or TaW alloy. In addition, the film for the substrate-side wiring base is constituted.
The mixing ratio of tantalum in the TaMo alloy or TaW alloy is set, for example, to about 60 to 85 at%.

Next, in the second film-forming step, while continuously decreasing the deposition rate of Mo or W constituting the substrate-side wiring base film, the deposition rate of Ta is continuously increased to contain the Mo or W. As a sputtering method for continuously forming an intermediate film of a TaMo alloy or a TaW alloy in which the amount is continuously decreased in the deposition direction, `` simultaneous sputtering '' is used for forming a film for a substrate-side wiring base. When applied, the amount of power applied to each target is adjusted to continuously reduce the deposition rate of Mo or W, while the deposition rate of Ta is continuously increased to form the intermediate coating. It is possible.

On the other hand, a TaMo alloy or Ta
When the sputtering method using a “single target” corresponding to W alloy is applied, a Ta target is placed at a certain distance from the “single target”, and a constant speed is applied. By transporting the insulating substrate by the above, the intermediate film can be formed when the substrate sequentially passes through the Ta target and the TaMo target.

Next, in the third film forming step, a film for a laminated wiring portion of Ta is continuously formed on the intermediate film by a sputtering method, and the film for the laminated wiring portion of Ta is formed of the film for the wiring base on the substrate side and the intermediate film. Body-centered cubic lattice structure (bcc… body-centered
It grows by inheriting cubic lattice) and becomes a film of α-tantalum having a body-centered cubic lattice structure and low resistance.

By the way, "Handb" issued by McGRAW-HILL BOOK COMPANY
Looking at the specific resistance (μΩcm) of β-tantalum having a square lattice structure and α-tantalum having a body-centered cubic lattice structure (bcc) from “ook of Thin Film Technology”, β-tantalum is 180 Α-tantalum is 25 to 50 μΩ · cm, whereas α-tantalum is as low as bulk (13 μΩ · cm).

Here, the intermediate film is made of a TaMo alloy or a TaW alloy in which the content of Mo or W is continuously reduced in the deposition direction, and is made of this intermediate film and a TaMo alloy or a TaW alloy. Since the composition between the substrate-side wiring base film is approximated and the difference between the lattice constants is small, distortion of the crystal structure at the interface between the intermediate film and the substrate-side wiring base film is reduced. Since the composition of the film for the laminated wiring portion is also approximated and the difference between the lattice constants is small, the distortion of the crystal structure at the interface between the intermediate film and the film for the laminated wiring portion is reduced.

Therefore, as the crystal structure distortion in the film for the laminated wiring portion of Ta decreases, it is possible to minimize the decrease in the conductivity of the film for the laminated wiring portion at the interface with the intermediate film, This has the advantage that the desired conductivity can be obtained without setting the Ta film thickness large.

In addition, even if the first wiring portion is formed by the “two-stage film forming method” in which the TaMo alloy is formed and the sputtering is temporarily stopped, and then the tantalum is formed again, the TaMo alloy substrate-side wiring base film is not used. A small amount of Mo diffuses into the film for the laminated wiring part, and a thin film corresponding to the intermediate film of the present invention (that is, a thin film of a TaMo alloy having a continuously reduced Mo content) is slightly formed at these interfaces. However, it has been confirmed that such a thin film cannot sufficiently reduce the distortion.

Next, in this technical means, the first wiring portion means a wiring portion formed first during the manufacturing process of the thin film semiconductor device and at least a part thereof is provided in surface contact with the insulating substrate, for example, This corresponds to the gate electrode of an "inverted staggered" transistor, the source electrode / drain electrode of a "staggered" transistor, signal wiring, and the like, and the wiring portion formed first in a bipolar thin film transistor. I do.

[Action]

According to the technical means as described above, a first film forming step of forming a film for a substrate-side wiring base of a TaMo alloy or a TaW alloy by a sputtering method, and Mo or W constituting the film for a substrate-side wiring base. Of TaMo alloy or TaW alloy in which the deposition rate of Ta is continuously increased while the content of Mo or W is continuously decreased in the deposition direction while the deposition rate of Ta is continuously decreased. A second film forming step of continuously forming a film on the substrate side wiring base film by a sputtering method, and a third film forming of a Ta laminated wiring portion film by a sputtering method on the intermediate film. A film forming step, wherein the intermediate film formed in the second film forming step is Mo or W
Whose content is continuously reduced in the deposition direction
The composition between this intermediate film and the substrate-side wiring base film composed of TaMo alloy or TaW alloy is similar and the difference in each lattice constant is small, so the intermediate film and the substrate-side wiring While the crystal structure distortion at the interface of the base film is reduced, the composition between the above-mentioned intermediate film and the film for the laminated wiring portion of Ta is also approximated and the difference in each lattice constant is small. The distortion of the crystal structure at the interface of the coating is also reduced.

〔Example〕

Hereinafter, an embodiment in which the present invention is applied to an “inverted staggered” thin film transistor will be described in detail with reference to the drawings.

That is, the thin film transistor according to this embodiment is the first thin film transistor.
As shown in FIGS. 2 and 3, a glass substrate (1), a gate electrode (20) and a first wiring (30) provided in surface contact on the glass substrate (1), and the gate electrode (20). )
A Si _x N _y made of the gate insulating film covering the (4), the gate insulating film (4) formed on the intrinsic amorphous silicon: and (ia-Si H) made of a semiconductor layer (5), this the semiconductor layer (5) Si _x n _y made of top insulating film provided on portions corresponding to the gate electrode (20) on (6), provided on both ends of the semiconductor layer (5) n ⁺ An amorphous silicon ohmic contact formation layer (70) and a barrier metal layer (8) provided on the ohmic contact formation layer (70) and formed of Cr, Mo, Ti, Ta, W, or a silicide thereof;
0) Source electrode (7) and drain electrode (8)
And an interlayer insulating film (90) made of polyimide, which is formed while exposing a part of the barrier metal layer (80), and the barrier metal layer (90) through an exposed portion of the interlayer insulating film (90). the second wiring 80) to be connected with aluminum provided with (91), a main part out with SiO _x steel passivation film (92) is configured to cover the entire this like, and the gate electrode ( 20) and the first wiring (30) are 250mm thick with TaMo
Board side wiring base (21) made of alloy (Mo content 35at%)
And a thickness of 500 provided on the board-side wiring base (21).
The intermediate film (22) made of TaMo alloy in which the content of Mo is continuously reduced in the deposition direction at Å, and the thickness of 2250 mm provided on this intermediate film (22) is made of Ta. It is composed of a laminated wiring portion (23) and a TaO _x anodic oxide film (24) formed on the surface thereof.

The thin film transistor is manufactured according to the following steps.

That is, by using a Ta target and a Mo target and appropriately adjusting the amount of electric power applied to each target, the “simultaneous sputtering” set at the deposition rate shown in FIG. As shown in FIG. 4, a substrate side wiring base film (25) made of an alloy (Mo compounding ratio 35 at%) was formed (see FIG. 3A), and the amount of power applied to each target was adjusted. The film deposition rate of Mo is continuously reduced while the deposition rate of Ta is
After the TaMo alloy intermediate film (22), in which the content of Mo is continuously reduced in the deposition direction, is continuously formed on the substrate-side wiring base film (25) ( According to the deposition rate shown in FIG. 4 and FIG.
2) A film (26) for a laminated wiring portion made of Ta is formed on the upper surface to a thickness of 2250 mm (see FIG. 3C).

In this case, the film (26) for the laminated wiring portion of Ta is grown by inheriting the body-centered cubic lattice (bcc ... body-centered cubic lattice) of the film (25) for the wiring base on the substrate side and the intermediate film (22). The substrate-side wiring base film (25), the intermediate film (22), and the laminated wiring portion film (2
6) In the composition ratio (that is, Ta and Mo in the depth direction of each film)
For example, RBS
(Rutherford back scattering) method was as shown in the graph of FIG.

Next, these substrate side wiring base film (25), intermediate film (22), and laminated wiring portion film (26) are subjected to a photolithography step and an etching step using a CF ₄ -based etching agent as shown in FIG. Patterning is performed as shown in (D), and the surface of these films is anodized to form an anodic oxide film (24) of TaO _x as shown in FIG. 3 (E). One wiring is provided.

The components other than the gate electrode and the first wiring are formed by the same method as in the related art.

That is, as shown in FIG. 6 (A), after forming the gate electrode and the first signal wiring, the thickness is 3000 mm and the Si _x N
_y film for gate insulating film (4 '), 500 mm thick intrinsic amorphous silicon (ia-Si: H) semiconductor layer film (5'), and 1500 mm thick Si _x N _y top insulation The film for film (6 ') is successively deposited by the PCVD method sequentially (see FIG. 6B), and the film for top insulation (6') is wet-etched as shown in FIG. 6 (C). The top insulating film (6) is formed by patterning by a method.

Then, on this surface, an ohmic contact formation layer film (71) of n ⁺ -amorphous silicon with a thickness of 1000 mm for forming source and drain electrodes and a thickness of 1500 mm with Cr, Mo, Ti, T
a, W or a barrier metal layer film (81) formed of such silicide is sequentially deposited by PCVD method and sputtering method (see FIG. 6D), and these are subjected to photolithography and wet processing. After patterning by an etching method (see FIGS. 6E to 6G), an interlayer insulating film (90) of polyimide resin is deposited as shown in FIG. 6 (H).

Further, as shown in FIG. 6 (I), a part thereof is removed by etching to form a via hole (93), and aluminum for forming a second wiring is deposited on this surface by sputtering. After the second wiring (91) is formed by patterning by wet etching, a SiO _x passivation film (92) is deposited on the entire surface of the second wiring (91) to manufacture the thin film transistor.

The thin film transistor according to the embodiment thus configured has a source electrode (7) and a thin film transistor similar to a conventional transistor.
Apply a drain voltage (V _D ) between the drain electrodes (8),
When a gate voltage (V _G ) is applied to the gate electrode (20), a channel is formed in the semiconductor layer (5) to act as an ON state. On the other hand, as the gate voltage (V _G ) is lowered, the channel becomes It is no longer formed and acts as an OFF state.

In the thin film transistor according to this embodiment, the gate electrode (20) and the first wiring (30) are
The substrate-side wiring base (21) made of TaMo alloy at 250 mm and the Mo content provided on the substrate-side wiring base (21) and having a thickness of 500 mm have a continuous decrease in the Mo content in the film deposition direction. An intermediate film (22) made of TaMo alloy, a laminated wiring portion (23) made of Ta having a thickness of 2250 mm provided on this intermediate film (22), and an anodic oxide film of TaO _x ( 24), the laminated wiring portion (23) grows while inheriting the body-centered cubic lattice structure of the TaMo alloy as the substrate-side wiring base (21) and the intermediate film (22), and has a resistance value of Since it is composed of low α-tantalum, the gate electrode (20) and the first wiring (3
The conductivity of 0) is significantly higher than in the past.

Therefore, the thin film transistor according to this embodiment has an advantage that the operation speed can be drastically increased.

Moreover, the intermediate film (22) is made of a TaMo alloy in which the content of Mo is continuously reduced in the deposition direction,
Since the composition between this intermediate film (22) and the substrate-side wiring base (21) made of TaMo alloy is similar and the difference in each lattice constant is small, the intermediate film (22) and the substrate-side wiring base (21)
While the distortion of the crystal structure at the interface between them is reduced, the composition between the above-mentioned intermediate film (22) and the laminated wiring portion (23) of Ta is also approximated, and the difference in each lattice constant is small.
The distortion of the crystal structure at the interface between 2) and the laminated wiring portion (23) is also reduced.

Accordingly, it is possible to minimize the decrease in the conductivity of the laminated wiring portion (23) at the interface with the intermediate film (22) due to the reduction in the distortion of the crystal structure in the laminated wiring portion (23). Since the desired conductivity can be obtained even if the thickness of Ta is not set large, the step between the portion where the wiring portion is formed and the portion where the wiring portion is not formed becomes small, contributing to the demand for flattening of the thin film semiconductor device. It has the advantages that it can.

In this example, the intermediate film (2) was formed by “simultaneous sputtering” using a Ta target and a Mo target.
2) etc. are formed, but the T shown in FIGS.
It is also possible to form the above intermediate film (22) or the like by an "in-line apparatus" using an aMo target and a Ta target.

That is, the TaMo target (11) and the Ta target (12) are juxtaposed in the sputtering chamber (10) at an appropriate distance. By arranging in this way, as shown in FIG.
A region filled with a TaMo mixed gas in which the Mo concentration decreases as the Ta target (12) is approached and the Ta concentration increases becomes closer to the Mo target (11) and the Ta target (12).

Accordingly, the glass substrate (1) is carried into the sputtering chamber (10), and is passed through the above-mentioned region, so that the substrate-side wiring base film, the intermediate film, and the laminated wiring are formed on the glass substrate (1). Part coatings can be sequentially and continuously formed.

〔The invention's effect〕

According to the present invention, the intermediate film formed in the second film forming step is Mo or W
Whose content is continuously reduced in the deposition direction
The composition between this intermediate film and the substrate-side wiring base film composed of TaMo alloy or TaW alloy is similar and the difference in each lattice constant is small, so the intermediate film and the substrate-side wiring While the strain at the interface of the base film is reduced, the composition between the above-mentioned intermediate film and the film for the laminated wiring portion of Ta is also approximated and the difference in each lattice constant is small, so the interface between the intermediate film and the film for the laminated wiring portion is small. Is also reduced.

Accordingly, as the crystal structure distortion in the film for the laminated wiring portion of Ta decreases, it is possible to minimize the decrease in the conductivity of the film for the laminated wiring portion at the interface with the intermediate film, and to reduce the Ta content. The desired conductivity can be obtained without setting the film thickness large, so that the step between the portion where the wiring portion is formed and the portion where the wiring portion is not formed becomes small, which contributes to the demand for flattening the thin film semiconductor device. have.

[Brief description of the drawings]

1 to 8 show an embodiment of the present invention. FIG. 1 is a schematic perspective view of a thin film transistor according to the embodiment, FIG. 2 is a sectional view taken along the line II-II of FIG. 1, and FIG. (A) to (E) are process explanatory views showing a process of forming a gate electrode and a first wiring of the thin film transistor. FIG. 4 is a view showing Ta and Mo when the gate electrode and the first wiring are formed by “simultaneous sputtering”. FIG. 5 is a graph showing the relationship between the deposition time and the deposition rate of FIG. 5, and FIG. 5 shows the composition ratio of Ta and Mo (the content of Ta and Mo in the depth direction) in the film forming the gate electrode and the first wiring. 6 (A) to 6 (J) are process explanatory diagrams showing a manufacturing process of a thin film transistor after forming a gate electrode and a first wiring, and FIG. 7 is applied to another embodiment. FIG. 8 is a plan view of the “in-line device”, and FIG.
FIGS. 9 to 13 show sectional views taken along the plane VIII. FIGS. 9 to 13 show a conventional thin film semiconductor device.
FIG. 10 is a schematic perspective view of a MOS thin film transistor, FIG. 10 is a sectional view taken along the line XX of FIG. 9, FIG. 12 is a sectional view taken along the line XII-XII of FIG. 11, and FIG. FIG. 14 is a sectional view of an improved MOS thin film transistor, and FIGS.
(C) is a step explanatory view showing a step of forming the first wiring portion,
FIG. 15 is a graph showing the relationship between the deposition time and deposition rate of Ta and Mo in this formation step, and FIG. 16 is a graph showing the relationship between the thickness of Ta and the resistance value of the formed first wiring portion. It is a graph which shows a relationship. [Explanation of Symbols] (1) Glass substrate (5) Semiconductor layer (20) Gate electrode (21) Substrate wiring base (22) Intermediate coating (23) Multilayer wiring section ( 25)… Coating for substrate base side wiring (26)… Coating for laminated wiring part (30)… First wiring

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 29/786 H01L 21/336 H01L 21/3205 H01L 29/40 H01L 21/208 301

Claims (1)

(57) [Claims] An insulating substrate, a semiconductor layer provided on the insulating substrate, and a TaMo (tantalum molybdenum) alloy or a TaW (tantalum tungsten) provided at least partially in surface contact with the insulating substrate. A) a first wiring portion comprising an alloy substrate-side wiring base and a laminated wiring portion of Ta (tantalum) laminated thereon; and a substrate-side wiring base of the TaMo alloy or TaW alloy. Film forming process for forming a film for sputtering by sputtering method, and Mo (molybdenum) constituting the film for the substrate side wiring base
Or a TaMo alloy in which the deposition rate of W (tungsten) is continuously reduced, while the deposition rate of Ta is continuously increased, and the content of Mo or W is continuously reduced in the deposition direction. Alternatively, a second film forming step in which an intermediate film of a TaW alloy is continuously formed on the substrate side wiring base film by a sputtering method, and a Ta laminated wiring film is continuously formed on the intermediate film by a sputtering method. And a third film forming step of forming a film.