JPH02306696A - Multilayer interconnection substrate - Google Patents
Multilayer interconnection substrateInfo
- Publication number
- JPH02306696A JPH02306696A JP12833689A JP12833689A JPH02306696A JP H02306696 A JPH02306696 A JP H02306696A JP 12833689 A JP12833689 A JP 12833689A JP 12833689 A JP12833689 A JP 12833689A JP H02306696 A JPH02306696 A JP H02306696A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- copper
- layer
- wiring board
- reducing flame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title 1
- 239000000463 material Substances 0.000 claims abstract description 26
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 17
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000010949 copper Substances 0.000 claims abstract description 13
- 229910052802 copper Inorganic materials 0.000 claims abstract description 12
- 239000005751 Copper oxide Substances 0.000 claims abstract description 11
- 229910000431 copper oxide Inorganic materials 0.000 claims abstract description 11
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 239000010410 layer Substances 0.000 abstract description 50
- 125000001475 halogen functional group Chemical group 0.000 abstract description 14
- 239000011229 interlayer Substances 0.000 abstract description 10
- BERDEBHAJNAUOM-UHFFFAOYSA-N copper(I) oxide Inorganic materials [Cu]O[Cu] BERDEBHAJNAUOM-UHFFFAOYSA-N 0.000 abstract description 5
- KRFJLUBVMFXRPN-UHFFFAOYSA-N cuprous oxide Chemical compound [O-2].[Cu+].[Cu+] KRFJLUBVMFXRPN-UHFFFAOYSA-N 0.000 abstract description 4
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 239000004744 fabric Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- -1 aminoborane compound Chemical class 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910002090 carbon oxide Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000002485 combustion reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 239000003721 gunpowder Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- UKLNMMHNWFDKNT-UHFFFAOYSA-M sodium chlorite Chemical compound [Na+].[O-]Cl=O UKLNMMHNWFDKNT-UHFFFAOYSA-M 0.000 description 1
- 229960002218 sodium chlorite Drugs 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 229920006305 unsaturated polyester Polymers 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） この発明は、多層配線基板に関するものである。[Detailed description of the invention] (Industrial application field) The present invention relates to a multilayer wiring board.
さらに詳しくは、この発明は、内層材とプリプレグ層と
の接着力を向上させ、ファイン回路を有する配線板の信
頼性を向上させた新しい多層配線基板に関するものであ
る。More specifically, the present invention relates to a new multilayer wiring board in which the adhesive strength between an inner layer material and a prepreg layer is improved, and the reliability of a wiring board having fine circuits is improved.
（従来の技術）
電気・電子機器、電子計算機、通信機器等に用いられて
いるプリント配線板については、近年の高密度実装の要
請の高まりとともに多層配線板への需要が増大し、これ
にともなって多層配線板の信頼性向上のための種々の工
夫がなされてきてい木。(Prior art) With regard to printed wiring boards used in electrical and electronic equipment, electronic computers, communication equipment, etc., demand for multilayer wiring boards has increased with the increasing demand for high-density packaging in recent years. Various efforts have been made to improve the reliability of multilayer wiring boards.
従来、このような多層構造を有するプリント配線板につ
ｉｌては、たとえば第２図に示したように、片面または
両面銅張積層板の銅箔面に回路（ア）を形成したものを
内層材（イ）とし、この内層材（イ）の表面をサンダー
、ベルトサンダー等によって物理的に粗化し、あるいは
この粗化後にアルカリ性亜塩素酸ナトリウム水溶液等で
処理して銅箔回路（ア）の表面に黒色酸化銅皮膜を形成
する黒化処理してから、プリプレグ層（つ）を介して片
面鋼張積層板や銅油（１）を外層材として配設して一体
化成形することにより製造してきている。Conventionally, for printed wiring boards having such a multilayer structure, for example, as shown in FIG. The surface of the inner layer material (A) is physically roughened using a sander, belt sander, etc., or after roughening, it is treated with an alkaline sodium chlorite aqueous solution to form a copper foil circuit (A). Manufactured by blackening treatment to form a black copper oxide film on the surface, and then integrally forming a single-sided steel clad laminate and copper oil (1) as the outer layer material through prepreg layers. I've been doing it.
（発明が解決しようとする課り
、 このような従来の製造法は、これまでのパターン密
度の回路においては信頼性を一応は確保できるものの、
近年の回路密度が著しく増大したファインパターン回路
においては、内層材（イ）とプリプレグ層（つ）との間
の層間接着力を確保することが難しくなってきている。(Issues that the invention aims to solve) Although such conventional manufacturing methods can secure reliability in circuits with conventional pattern densities,
In recent years, in fine pattern circuits where the circuit density has significantly increased, it has become difficult to ensure interlayer adhesion between the inner layer material (a) and the prepreg layer (t).
これは、プリント配線板における内層材（イ）表面の従
来の回路面積に比べて、ファインパターン回路の場合に
はその回路（ア）の占める面積が著しく大きくなるため
、内層材（イ）の樹脂層とプリプレグ層（つ）との接触
面積が減少し、たとえ銅箔回路（ア）を従来の方法で表
面処理したとしても、この接触面での層間接着性の低下
が避けられないことによる。This is because the area occupied by the circuit (A) in a fine pattern circuit is significantly larger than the conventional circuit area on the surface of the inner layer material (A) in a printed wiring board. This is because the contact area between the layer and the prepreg layer (2) is reduced, and even if the copper foil circuit (A) is surface-treated by a conventional method, the interlayer adhesion at this contact surface will inevitably deteriorate.
このため、従来の製造方法によっては層間接着力が低下
し、ハローの発生と配線板の信頼性の低下が避けられな
かった。For this reason, depending on the conventional manufacturing method, the interlayer adhesion strength is reduced, and the occurrence of halos and a decrease in the reliability of the wiring board are unavoidable.
このような課題を解決するものとして、内層材（イ）の
表面を黒化処理した後に還元する方法が提案されている
が、この方法は、特殊なアミノボラン化合物を使用する
ことが必要であり、その効果も必ずしも満足できるもの
ではなかった。As a solution to this problem, a method has been proposed in which the surface of the inner layer material (a) is blackened and then reduced, but this method requires the use of a special aminoborane compound. The effects were not necessarily satisfactory.
この発明は、以上の通りの事情に鑑みてなされたもので
あり、従来の多層配線板の製造方法の欠点を改善し、フ
ァインパターン回路、すなわち内層材表面の回路面積が
大きくなっても層間接着性が良好であって、耐ハロー性
に優れ、信頼性を向上させることのできる新しい多層配
線基板を提供することを目的としている。This invention was made in view of the above-mentioned circumstances, and it improves the shortcomings of the conventional multilayer wiring board manufacturing method, and improves interlayer adhesion even when the circuit area of the surface of the inner layer material becomes fine pattern circuit. The present invention aims to provide a new multilayer wiring board that has good properties, excellent halo resistance, and can improve reliability.
（課題を解決するための手段） この発明は、上記の課題を解決するものとして。(Means for solving problems) This invention is intended to solve the above problems.
内層回路板の銅回路を酸化処理して形成した銅酸化物層
を、還元炎と接触させて低酸化状態とし、次いでプリプ
レグを介して外層材を配設した積層体を一体成形してな
ることを特徴とする多層配線基板を提供する。A copper oxide layer formed by oxidizing the copper circuit of the inner layer circuit board is brought into contact with a reducing flame to bring it into a low oxidation state, and then a laminate is integrally formed with outer layer material arranged via prepreg. A multilayer wiring board is provided.
Ｃｕ Ｏ、Ｃｕ ２０の銅酸化物層と接触させる還元炎
は、燃料となるガスのバーナー等による燃焼により生じ
るものであり、空気が送気されずに、水素、−酸化炭素
などを含む還元性の炎である。The reducing flame that is brought into contact with the copper oxide layer of CuO and Cu20 is generated by the combustion of gas as a fuel using a burner, etc., and the reducing flame containing hydrogen, carbon oxide, etc. is generated without air being supplied. It is the flame of
この発明では、たとえば、このような還元炎中に銅酸化
物層を有する内装回路板を通過させることにより、還元
炎と酸化物層とを接触させる。In this invention, for example, the reducing flame and the oxide layer are brought into contact by passing an internal circuit board having a copper oxide layer through such a reducing flame.
この接触は瞬時に行うのが好ましい、好適には、３秒以
内程度の還元炎中の通過によって、銅酸化物層の低レベ
ル酸化状態への還元を行う。Preferably, this contact is instantaneous, preferably by passage through the reducing flame for no more than 3 seconds to reduce the copper oxide layer to a low oxidation state.
この処理により、銅回路唇面は粗面化し、１リプレグと
の接着力は一段と向上する。This treatment roughens the lip surface of the copper circuit and further improves the adhesive strength with 1 Repreg.
また、還元炎との接触は、回路板表面での溶剤燃焼によ
って行うこともできる。Contact with the reducing flame can also be achieved by burning a solvent on the circuit board surface.
添付した図面に沿ってこの発明の多層配線基板について
説明する。The multilayer wiring board of the present invention will be explained along with the attached drawings.
（ａ） プリプレグおよび銅箔等から成形した片また
は両面に銅回路（１）を有する内層材（２）の銅回路（
１）表面を酸化処理し、ＣｕＯ１Ｃｕ２０の銅酸化物層
（３）を形成する。(a) Copper circuit (
1) Oxidize the surface to form a copper oxide layer (3) of CuO1Cu20.
この時の内層材（２）を形成するプリプレグには特にそ
の種類に限定はなく、ガラスクロス、紙等の基材にフェ
ノール、エボキン、ポリイミド、不飽和ポリエステル等
の樹脂を含浸させたものを適宜使用することができる。The prepreg forming the inner layer material (2) at this time is not particularly limited in its type, and may be a base material such as glass cloth or paper impregnated with a resin such as phenol, Evoquin, polyimide, or unsaturated polyester. can be used.
これらのプリプレグは、たとえば１〜３枚の適宜な枚数
用いることができる。An appropriate number of these prepregs, for example 1 to 3, can be used.
銅回路（１）の酸化は、これまでに知られている黒化処
理等の方法によって、あるいは気相での酸素酸化等によ
って行うことができる。この時の処理に応じて、ＣｕＯ
１またはＣｕ２Ｏ、もしくはその共存の状態の銅酸化物
層（３）が形成される。The copper circuit (1) can be oxidized by a known method such as blackening treatment, or by oxygen oxidation in a gas phase. Depending on the treatment at this time, CuO
A copper oxide layer (3) of Cu2O, Cu2O, or their coexistence is formed.
“次いで、この銅酸化物層（３）の酸化レベルを還元炎
との接触によって、より低い状態とする。“This copper oxide layer (3) is then brought to a lower oxidation level by contact with a reducing flame.
（ｂ） 次いで、得られた表面に、所要枚数の１リプ
レグ（４）と外層材（５）とを配設して積層一体化する
。(b) Next, the required number of 1-repreg (4) and outer layer material (5) are arranged on the obtained surface and laminated and integrated.
プリプレグ（４）は、たとえば１〜３枚程度配設するの
が好ましいが、特にこれに限定されることはない、プリ
プレグ（４）としては１．内層材（２）の場合と同様に
ガラスクロス、アラミドクロス、ポリエスチルクロスな
どのクロスやマット状物、あるいは不織布や紙などの基
材にエポキシ樹脂、フェノール樹脂、ポリイミド樹脂な
どの樹脂を含浸させたものを用いることができる。なか
でもガラスクロスエポキシ樹脂プリプレグが好適なもの
として例示される。It is preferable to arrange, for example, about 1 to 3 prepregs (4), but the prepregs (4) are not particularly limited to this. As with the inner layer material (2), a cloth or mat-like material such as glass cloth, aramid cloth, or polyester cloth, or a base material such as nonwoven fabric or paper is impregnated with resin such as epoxy resin, phenol resin, or polyimide resin. can be used. Among these, glass cloth epoxy resin prepreg is exemplified as a suitable one.
また、外層材（５）としては、銅箔や、あるいはプリプ
レグと銅箔とから片面銅張積層体としたものを用いるこ
とができる。Further, as the outer layer material (5), a single-sided copper-clad laminate made of copper foil or prepreg and copper foil can be used.
積層一体化成形は、多段プレス、スチロール、ダブルベ
ルト、無圧連続加熱等の従来公知の方法や条件に沿って
適宜に実施することができる。この成形によって一体化
した積層板の最外層ＩＦｌ箔に回路形成することにより
多層回路板が製造される。The lamination and integral molding can be appropriately carried out according to conventionally known methods and conditions such as multistage press, styrene, double belt, pressureless continuous heating, and the like. A multilayer circuit board is manufactured by forming a circuit on the outermost layer of IFl foil of the laminate integrated by this molding.
もちろん、以上の製造上の条件等の細部については、公
知のものを含めて様々な態様が可能であることはいうま
でもない。Of course, it goes without saying that the details of the above manufacturing conditions and the like can be modified in various ways, including known ones.
（作 用）
この発明においては、内層材の銅回路表面の酸化処理と
、還元炎との接触による酸化レベルの低次化処理で、内
層材とプリプレグ層との層間接着力を大きく向上させ、
優れた耐ハロー性を実現する。(Function) In this invention, the interlayer adhesion between the inner layer material and the prepreg layer is greatly improved by oxidizing the copper circuit surface of the inner layer material and lowering the oxidation level by contacting with a reducing flame.
Achieves excellent halo resistance.
以下、実施例を示してさらに詳しくこの発明の多層配線
基板について説明する。Hereinafter, the multilayer wiring board of the present invention will be described in more detail with reference to Examples.
〈実施例）
実施例１
厚さＩＩＩＩ＋の両面銅張ガラスエポキシ樹脂′Ｈｉ層
板の両面に回路形成し、これを内層材としな。<Examples> Example 1 A circuit was formed on both sides of a double-sided copper-clad glass epoxy resin 'Hi layer plate having a thickness of III+, and this was used as an inner layer material.
水洗後に、ＮａＣＪ ０４ 、ＮａＯＨおよびＮ２ＰＯ
４・２Ｈ２０の水溶液で処理して、回路表面にＣｕＯ層
を形成した。After washing with water, NaCJ 04 , NaOH and N2PO
A CuO layer was formed on the circuit surface by treatment with an aqueous solution of 4.2H20.
その後、ガスの還元炎中に瞬時的に通過させてＣｕｒｌ
を還元した０次いで、水洗した後に乾燥した。Then, it is passed momentarily through a gas reducing flame to curl
0 was then washed with water and dried.
厚さ０．１ｆｉのガラスクロスエポキシ樹脂プリプレグ
を各々２枚づつ内層材の上下両面に配設し、さらに最外
層として厚さ０．０３５ ｍの銅箔を配設した。Two glass cloth epoxy resin prepregs each having a thickness of 0.1 fi were disposed on the upper and lower surfaces of the inner layer material, and a copper foil having a thickness of 0.035 m was further disposed as the outermost layer.
この積層体を４０ｋｇ／−の圧力、１６５℃の温度で６
０分間積層成形し、４層回路プリント配線基板を得た。This laminate was heated at a pressure of 40 kg/- and a temperature of 165°C.
Lamination molding was carried out for 0 minutes to obtain a four-layer circuit printed wiring board.
この配線板について層間接着性と耐ハロー性を評価しな
ところ、表１に示した結果を得な、後述の比較例の対比
から、層間接着力は大きく向上し、耐ハロー性は若しく
改善されていることが確認された。When we evaluated the interlayer adhesion and halo resistance of this wiring board, we obtained the results shown in Table 1. From the comparison with the comparative examples described later, we found that the interlayer adhesion was greatly improved and the halo resistance was slightly improved. It was confirmed that
なお、耐ハロー性については、１ ： ＩＨＣｊ溶液の
３０分間浸漬として評価しな。Note that the halo resistance was evaluated as 1: immersion in IHCj solution for 30 minutes.
実施例２
回路表面にＣｕ２Ｏ層を形成した他は実施例１と同様に
して多層配線基板を製造し、耐ハロー性を評価した。そ
の結果を表１に示した。Example 2 A multilayer wiring board was manufactured in the same manner as in Example 1 except that a Cu2O layer was formed on the circuit surface, and the halo resistance was evaluated. The results are shown in Table 1.
ずぐれた耐ハロー性が得られた。Excellent halo resistance was obtained.
実施例３
実施例１のＣｕＯ層を有する回路板にメタノールをわず
かに塗布し、その後点火して３秒後に水中に投入して消
火した。Example 3 The circuit board having the CuO layer of Example 1 was lightly coated with methanol, then ignited, and 3 seconds later it was put into water to extinguish it.
これを同様にして多層板とし、耐ハロー特性について評
価した。This was similarly made into a multilayer board, and the halo resistance properties were evaluated.
比較例１
銅回路表面の酸化および還元炎処理を行わずに多層配線
基板を製造した０、耐ハロー性を評価したところ、実施
例に比べてはるかに劣っていた。Comparative Example 1 A multilayer wiring board was manufactured without performing oxidation and reduction flame treatment on the surface of the copper circuit. When the halo resistance was evaluated, it was far inferior to the examples.
比較例２
黒化処理によりＣｕ、Ｑ層を形成し、そのままの状態で
多層板を製造した。耐ハロー性は劣っていた。Comparative Example 2 Cu and Q layers were formed by blackening treatment, and a multilayer board was manufactured in that state. Halo resistance was poor.
表 １
（発明の効果）
この発明の多層配線基板により、以上詳しく説明した通
り、層間接着性および耐ハロー性を大きく向上させた多
層配線基板が実現される。Table 1 (Effects of the Invention) As explained in detail above, the multilayer wiring board of the present invention realizes a multilayer wiring board with greatly improved interlayer adhesion and halo resistance.
ファインパターン回路を有する多層配線基板の信頼性を
向上させることができる。The reliability of a multilayer wiring board having a fine pattern circuit can be improved.
第１図はこの発明の多層配線基板の製造工程を例示した
断面図である。第２図は、従来の製造工程を示した断面
図である。
１・・・銅 回 路
２・・・内 層 材
３・・・銅酸化物層
４・・・プリプレグ
５・・・外層材
代理人 弁理士 西 澤 利 火薬 １
図
第 ２ 図
アFIG. 1 is a cross-sectional view illustrating the manufacturing process of a multilayer wiring board according to the present invention. FIG. 2 is a sectional view showing a conventional manufacturing process. 1... Copper circuit 2... Inner layer material 3... Copper oxide layer 4... Prepreg 5... Outer layer material agent Patent attorney Toshi Nishizawa Gunpowder 1
Figure 2 Figure A
Claims (2)
酸化物層を、還元炎と接触させて低酸化状態とし、次い
でプリプレグを介して外層材を配設した積層体を一体成
形してなることを特徴とする多層配線基板。(1) The copper oxide layer formed by oxidizing the copper circuit of the inner layer circuit board is brought into a low oxidation state by contacting it with a reducing flame, and then a laminate with the outer layer material arranged through the prepreg is integrally formed. A multilayer wiring board characterized by:
１）記載の多層配線基板。(2) A claim in which the contact with the reducing flame is within 3 seconds (
1) Multilayer wiring board as described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1128336A JPH0644676B2 (en) | 1989-05-22 | 1989-05-22 | Method for manufacturing multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1128336A JPH0644676B2 (en) | 1989-05-22 | 1989-05-22 | Method for manufacturing multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02306696A true JPH02306696A (en) | 1990-12-20 |
| JPH0644676B2 JPH0644676B2 (en) | 1994-06-08 |
Family
ID=14982275
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1128336A Expired - Lifetime JPH0644676B2 (en) | 1989-05-22 | 1989-05-22 | Method for manufacturing multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0644676B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022009114A (en) * | 2019-02-26 | 2022-01-14 | ベジ 佐々木 | Substrate, electronic component, and mounting device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5635497A (en) * | 1979-08-30 | 1981-04-08 | Murata Manufacturing Co | Method of improving adherence of copper film |
| JPS57177593A (en) * | 1981-04-24 | 1982-11-01 | Hitachi Cable | Method of producing copper-coated laminated board |
-
1989
- 1989-05-22 JP JP1128336A patent/JPH0644676B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5635497A (en) * | 1979-08-30 | 1981-04-08 | Murata Manufacturing Co | Method of improving adherence of copper film |
| JPS57177593A (en) * | 1981-04-24 | 1982-11-01 | Hitachi Cable | Method of producing copper-coated laminated board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022009114A (en) * | 2019-02-26 | 2022-01-14 | ベジ 佐々木 | Substrate, electronic component, and mounting device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0644676B2 (en) | 1994-06-08 |
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