JPH02303191A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPH02303191A
JPH02303191A JP12521089A JP12521089A JPH02303191A JP H02303191 A JPH02303191 A JP H02303191A JP 12521089 A JP12521089 A JP 12521089A JP 12521089 A JP12521089 A JP 12521089A JP H02303191 A JPH02303191 A JP H02303191A
Authority
JP
Japan
Prior art keywords
tin
copper
layer material
circuit
laminated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12521089A
Other languages
Japanese (ja)
Inventor
Kunihiro Tsurumaru
鶴丸 邦浩
Sunao Ikoma
生駒 直
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP12521089A priority Critical patent/JPH02303191A/en
Publication of JPH02303191A publication Critical patent/JPH02303191A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To obtain a printed-wiring board whose interlayer bonding property is excellent and whose halo-resistant property is good by a method wherein laminated bodies where a circuit-copper surface of an inner-layer material is plated with copper containing tin, a eutectoid of tin and copper is precipitated and an outer-layer material is arranged, via a prepreg layer on the surface of the inner-layer material, at an outermost layer are laminated, molded and united. CONSTITUTION:Laminated bodies where a circuit-copper surface is plated with copper containing tin, a eutectoid of fine uneven tin and copper is precipitated on the circuit-copper surface and an outer-layer material composed of a one- sided metal-clad laminated sheet or a metal foil is arranged at an outermost layer via the required number of prepregs composed of a resin and a base material on the surface of an inner-layer material are laminated, molded and united by using a multistage press method, a multiroll method, a double-belt method, a drum method, a nonpressure continuous heating method or the like. For plating with copper containing tin, the copper containing a tin compound such as tin tartrate, potassium hydrogenstannate or the like is plated. It is preferable to contain 0.0001 to 0.01mol/l of tin ions.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電子機器、電気機器、コンピューター、通信機
器等に用すられるプリント配線板の製造方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing printed wiring boards used in electronic equipment, electrical equipment, computers, communication equipment, etc.

〔従来の技術〕[Conventional technology]

従来、プリント配線板は片面又は両面銅張積層板の銅箔
面に回路形成したものを内層材とし、内層材表面を粗化
、或は黒化処理等をおこなってからプリプレグ層を介し
、最外層に片面鋼張積層板や銅箔を外層材として配設し
た積層体を積層成形し一体化して得られるが、従来のパ
ターン回路間隔では上記方法でよいが、パターン回路間
隔が狭くなるファインパターンでは回路面積が増加し内
層材とプリプレグとの接着性が低下し、ドリル加工等の
穴あけ時の衝撃で開穴部周辺が層間剥離し、耐ハロー性
が低下する問題があった。
Conventionally, printed wiring boards are made by forming a circuit on the copper foil surface of a single-sided or double-sided copper-clad laminate as an inner layer material, and after roughening or blackening the surface of the inner layer material, the final layer is bonded via a prepreg layer. It is obtained by laminating and integrally molding a laminate in which a single-sided steel-clad laminate or copper foil is arranged as an outer layer material.The above method is sufficient for conventional pattern circuit spacing, but fine patterns with narrow pattern circuit spacing However, there was a problem in that the circuit area increased, the adhesiveness between the inner layer material and the prepreg decreased, and the impact during drilling etc. caused delamination of the layers around the hole, resulting in a decrease in halo resistance.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

。 従来の技術で述べたように、内層材表面をサンドペ
ーパー、サンドブラスト等で粗化する方法は均一な粗化
ができず回路を傷つける欠点があり、黒化処理では粗面
表面の黒色酸化銅被膜のため、耐ハロー性が低下する欠
点がある。本発明は従来の技術における上述の問題点に
鑑みてなされたもので、その目的とするところは層間接
置性に優れ、且つ耐ハロー性のよりプリント配線板の製
造方法を提供することにある。
. As mentioned in the conventional technology, the method of roughening the inner layer material surface using sandpaper, sandblasting, etc. has the disadvantage that it cannot achieve uniform roughening and damages the circuit. Therefore, there is a drawback that halo resistance decreases. The present invention has been made in view of the above-mentioned problems in the conventional technology, and its purpose is to provide a method for manufacturing a printed wiring board that has excellent interlayer bonding properties and is more resistant to halo. .

〔問題点を解決するための手段〕[Means for solving problems]

本発明は内層材の回路鋼表面に錫含有銅鍍金を施し、錫
と銅との共折物を析出させた後、該内層材表面にプリプ
レグNを介し最外層に外層材を配設した積層体を積層成
形し一体化5することを特徴とするプリント配線板の製
造方法のため、内層材の回路表面の接着性を向上させる
ことができ、且つ表面に黒色酸化銅皮膜がないので耐ノ
飄ロー性を向上させることができたもので、以下本発明
の詳細な説明する。
The present invention is a laminated structure in which tin-containing copper plating is applied to the circuit steel surface of the inner layer material to precipitate a symbiotic substance of tin and copper, and then the outer layer material is disposed on the surface of the inner layer material through prepreg N. Since the printed wiring board manufacturing method is characterized by laminated and integrated 5 parts, it is possible to improve the adhesion of the circuit surface of the inner layer material, and since there is no black copper oxide film on the surface, it is resistant to corrosion. The present invention will be described in detail below as it has been able to improve the rolling properties.

本発明に周込る内層材としてはフェノール樹脂、クレゾ
ール樹脂、エポキシ樹脂、不飽和ポリエステル樹脂、ポ
リイミド樹脂、ポリブタジェン樹脂、ポリフェニレンサ
ルファイド樹脂、ポリブチレンテレフタレートm脂、ポ
リエチレンテレフタレート樹脂、弗化樹脂等の樹脂と、
ガラス、アスベスト等の無機繊維やポリエステル、ポリ
アクリル、ポリアミド、ポリビニルアルコール等の有機
合成繊維や木綿等の天然繊維からなる織布、不織布、マ
、ソト或は紙又はこれらの組合せ基材とからなる片面又
は両面鋼張積層板に電気回路を形成したもので、回路銅
表面に錫含有銅鍍金を施し、回路銅表面に微細凹凸状の
錫と銅との共折物を・析出させてから、該内層材表面に
前記樹脂と基材とからなるプリプレグを所要枚数介し最
外層に片面金属張積層板や金属箔からなる外層材を配設
した積層体を多段プレス法、マルチロール法、ダブルベ
ルト法、ドラム法、無圧連続加熱法等で積層成形し一体
化するものである。錫含有銅鍍金としては酒石酸錫、錫
酸水素カリウム等のような錫化合物を含む銅鍍金を施す
もので錫イオンを0.0001〜0.Ofモル/l  
含有することが好ましい。
Inner layer materials included in the present invention include resins such as phenol resin, cresol resin, epoxy resin, unsaturated polyester resin, polyimide resin, polybutadiene resin, polyphenylene sulfide resin, polybutylene terephthalate resin, polyethylene terephthalate resin, and fluorinated resin. and,
Made of woven fabric, non-woven fabric, magenta, sotho, paper, or a combination of these materials made of inorganic fibers such as glass and asbestos, organic synthetic fibers such as polyester, polyacrylic, polyamide, and polyvinyl alcohol, and natural fibers such as cotton. An electric circuit is formed on a single-sided or double-sided steel-clad laminate, and the circuit copper surface is plated with tin-containing copper, and a finely uneven co-reciprocal compound of tin and copper is precipitated on the circuit copper surface. A laminate in which a required number of prepregs made of the above-mentioned resin and base material are interposed on the surface of the inner layer material and an outer layer material made of a single-sided metal-clad laminate or metal foil is placed on the outermost layer is prepared using a multi-stage press method, a multi-roll method, or a double belt method. They are laminated and integrated using methods such as the drum method, pressureless continuous heating method, etc. The tin-containing copper plating is a copper plating containing a tin compound such as tin tartrate, potassium hydrogen stannate, etc., and the tin ion is 0.0001 to 0. Ofmol/l
It is preferable to contain.

以下本発明を実施例にもとづいて説明する。The present invention will be explained below based on examples.

実施例 厚み1顛の両面銅張ガラス布エポキシ樹脂積層板の両面
に回路形成した内層材をプラーJシング、脱脂してから
陰極とじ錫酸水素カリウムを錫イオンでQ、001モル
/l 含有する銅鍍金液で鍍金処理し回路@表面に微細
凹凸状の錫と銅との共折物全析出させた後、該内層材の
上下面に厚さQ、 1 ffのガラス布エポキシ樹脂プ
リプレグを夫々2枚づつ介し最外層に厚さ35ミクロン
の銅箔を配設した積層体を40Kq/d 、  165
℃で60分間積層成形して4開回路プリント配線板を得
た。
Example: An inner layer material with circuits formed on both sides of a 1-thick double-sided copper-clad glass cloth epoxy resin laminate was put on a puller J-sing, degreased, and then used as a cathode. Potassium hydrogen stannate was added as a tin ion at a concentration of Q, 001 mol/l. After plating with a copper plating solution to fully precipitate a co-rectate of tin and copper in the form of fine irregularities on the surface of the circuit, a glass cloth epoxy resin prepreg with a thickness of Q and 1 ff was applied to the upper and lower surfaces of the inner layer material, respectively. A laminate with 35 micron thick copper foil placed on the outermost layer between two sheets at 40Kq/d, 165
Lamination molding was performed at ℃ for 60 minutes to obtain a 4-open circuit printed wiring board.

比較例 実施例と同じ回路形成した内層材をブラーJ、7ングし
てから90℃に加熱したアルカリ性亜塩素酸ナトリウム
水溶液に10分間浸漬して回路銅に酸化第2銅皮膜を形
成後、その上下面に厚さ0、IHのガラス布エポキシ樹
脂プリプレグを夫々2枚づつ介した以外は実施例と同様
に処理して4開回路プリント配線板を得た。
Comparative Example The inner layer material with the same circuit formed as in the Example was subjected to Blur J 7 immersion, and then immersed in an alkaline sodium chlorite aqueous solution heated to 90°C for 10 minutes to form a cupric oxide film on the circuit copper. A 4-open circuit printed wiring board was obtained in the same manner as in the example except that two glass cloth epoxy resin prepregs of 0 thickness and IH were interposed on the upper and lower surfaces.

実施例及び比較例のプリント配線板の性能は第1表のよ
うである。
The performances of the printed wiring boards of Examples and Comparative Examples are shown in Table 1.

注 ※ 穴あけ後、鍍金液処理後の水溶液のしみこみ。note *Aqueous solution seeps in after drilling and plating solution treatment.

〔発明の効果〕〔Effect of the invention〕

本発明は上述した如く構成されている。特許請求の範囲
@1項に記載したプリント配線板の創造方法によって得
られるプリント配線板は層間接着性及び耐ハロー性が向
上する効果がある。
The present invention is constructed as described above. The printed wiring board obtained by the method for creating a printed wiring board described in claim 1 has the effect of improving interlayer adhesion and halo resistance.

Claims (1)

【特許請求の範囲】[Claims] (1)内層材の回路銅表面に錫含有銅鍍金を施し、錫と
銅との共折物を析出させた後、該内層材表面にプリプレ
グ層を介し最外層に外層材を配設した積層体を積層成形
し一体化することを特徴とするプリント配線板の製造方
法。
(1) Laminate in which tin-containing copper plating is applied to the circuit copper surface of the inner layer material to precipitate a symbiotic substance of tin and copper, and then the outer layer material is placed on the surface of the inner layer material via a prepreg layer and the outermost layer. A method for manufacturing a printed wiring board, characterized by laminating and integrating the body.
JP12521089A 1989-05-18 1989-05-18 Manufacture of printed wiring board Pending JPH02303191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12521089A JPH02303191A (en) 1989-05-18 1989-05-18 Manufacture of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12521089A JPH02303191A (en) 1989-05-18 1989-05-18 Manufacture of printed wiring board

Publications (1)

Publication Number Publication Date
JPH02303191A true JPH02303191A (en) 1990-12-17

Family

ID=14904608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12521089A Pending JPH02303191A (en) 1989-05-18 1989-05-18 Manufacture of printed wiring board

Country Status (1)

Country Link
JP (1) JPH02303191A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100495184B1 (en) * 2002-12-02 2005-06-14 엘지마이크론 주식회사 A tape substrate and tin plating method of the tape substrate
KR100511965B1 (en) * 2002-12-13 2005-09-02 엘지전자 주식회사 A tin plating method of the tape substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100495184B1 (en) * 2002-12-02 2005-06-14 엘지마이크론 주식회사 A tape substrate and tin plating method of the tape substrate
KR100511965B1 (en) * 2002-12-13 2005-09-02 엘지전자 주식회사 A tin plating method of the tape substrate

Similar Documents

Publication Publication Date Title
JPH02303191A (en) Manufacture of printed wiring board
JPH02303187A (en) Manufacture of printed wiring board
JPH02303190A (en) Manufacture of printed wiring board
JPH02303188A (en) Manufacture of printed wiring board
JPH02277294A (en) Manufacture of printed wiring board
JPH02277289A (en) Manufacture of printed wiring board
JPH02277292A (en) Manufacture of printed circuit board
JPH02303189A (en) Manufacture of printed wiring board
JPH02277287A (en) Manufacture of printed wiring board
JPH02277290A (en) Manufacture of printed wiring board
JPH02277296A (en) Manufacture of printed wiring board
JPH02277297A (en) Manufacture of printed wiring board
JP3874076B2 (en) A method for producing a printed wiring board having an extra fine wire pattern.
JPH02277288A (en) Manufacture of printed wiring board
JPH08148836A (en) Multilayered flexrigid wiring board
JPH02277291A (en) Manufacture of printed wiring board
JPH02277293A (en) Manufacture of printed wiring board
WO2019098043A1 (en) Method for producing laminate with patterned metal foil, and laminate with patterned metal foil
JPH02277295A (en) Manufacture of printed wiring board
JPH02281690A (en) Manufacture of printed wiring board
JPH11238965A (en) Manufacture of multilayered printed wiring board
JPH02277298A (en) Manufacture of printed wiring board
JPH02250393A (en) Manufacture of printed board
JPH02306695A (en) Multilayer interconnection substrate
JPH05152740A (en) Manufacture of multilayered printed wiring board