JPH11238965A - Manufacture of multilayered printed wiring board - Google Patents
Manufacture of multilayered printed wiring boardInfo
- Publication number
- JPH11238965A JPH11238965A JP3862798A JP3862798A JPH11238965A JP H11238965 A JPH11238965 A JP H11238965A JP 3862798 A JP3862798 A JP 3862798A JP 3862798 A JP3862798 A JP 3862798A JP H11238965 A JPH11238965 A JP H11238965A
- Authority
- JP
- Japan
- Prior art keywords
- prepreg
- circuit board
- layer circuit
- resin
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、電子機器等に使用
される多層プリント配線板の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board used for electronic equipment and the like.
【0002】[0002]
【従来の技術】近年の電子機器の小型化に伴い、それに
使用されるプリント配線板も高集積化が要求され、また
多層化が進んでいる。多層プリント配線板は、それぞれ
複数の内層回路板、プリプレグ及び外層銅箔とを積層一
体に成形して製造されている。2. Description of the Related Art Along with the recent miniaturization of electronic devices, printed wiring boards used therein are required to be highly integrated and multilayered. The multilayer printed wiring board is manufactured by integrally molding a plurality of inner circuit boards, a prepreg, and an outer copper foil.
【0003】[0003]
【発明が解決しようとする課題】このような多層プリン
ト配線板において、プリプレグと内層回路板の接着性が
問題となっている。内層回路板は、両面金属張積層板を
エッチングにより回路加工して形成されるが、エッチン
グされた金属箔は、その表面が粗化形状を有しており内
層回路板の表面にその粗化形状が転写される。プリプレ
グと内層回路板の接着性は、内層回路板に使用された金
属箔の凹凸形状が基板表面に転写し、その凹凸がアンカ
ーの役割をはたすことにより達せられている。また、プ
リプレグと金属箔からなる回路パターンは回路パターン
表面を公知の酸化処理や酸化還元処理することにより、
接着性を高めることが行われている。ここで高密度化の
要求から内層回路板に使用する金属箔の厚さが薄くな
り、それに伴い金属箔の凹凸の小さいものを使用する傾
向にあり、基板に転写する凹凸も小さくなり、プリプレ
グと内層回路板の接着性が低下している。本発明はプリ
プレグと内層基板の接着性を、低コストで高生産性で向
上させることを課題とした。In such a multilayer printed wiring board, the adhesion between the prepreg and the inner circuit board has become a problem. The inner layer circuit board is formed by etching a double-sided metal-clad laminate, and the etched metal foil has a roughened surface. Is transferred. The adhesiveness between the prepreg and the inner layer circuit board is achieved by transferring the uneven shape of the metal foil used for the inner layer circuit board to the substrate surface, and the unevenness serves as an anchor. Also, the circuit pattern composed of prepreg and metal foil is obtained by subjecting the surface of the circuit pattern to a known oxidation treatment or oxidation-reduction treatment.
Enhancement of adhesion has been performed. Here, due to the demand for higher density, the thickness of the metal foil used for the inner layer circuit board has become thinner, and accordingly, there has been a tendency to use a metal foil with a smaller unevenness, and the unevenness transferred to the substrate has also become smaller. The adhesiveness of the inner circuit board is reduced. An object of the present invention is to improve the adhesiveness between a prepreg and an inner layer substrate at low cost and with high productivity.
【0004】[0004]
【課題を解決するための手段】本発明は、回路パターン
形成した内層回路板をプリプレグを介して積層接着する
多層プリント配線板の製造方法において、プリプレグと
接する内層回路板表面を薬品により粗化処理することを
特徴とする多層プリント配線板の製造方法である。ま
た、本発明は、内層回路板表面の十点平均粗さ(Rz)
が5μm以上であると好ましい多層プリント配線板の製
造方法である。SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a multilayer printed wiring board in which an inner circuit board on which a circuit pattern is formed is laminated and bonded via a prepreg. A method for manufacturing a multilayer printed wiring board. Further, the present invention provides a ten-point average roughness (Rz) of the inner circuit board surface.
Is preferably not less than 5 μm.
【0005】[0005]
【発明の実施の形態】内層回路板を薬品処理により粗化
処理する薬品としては、過マンガン酸カリ、濃硫酸又は
クロム酸等が挙げられ、バフ研磨やその他の研磨剤によ
る機械的粗化を併用しても良い。DESCRIPTION OF THE PREFERRED EMBODIMENTS Chemicals for roughening an inner circuit board by chemical treatment include potassium permanganate, concentrated sulfuric acid, chromic acid, and the like, and include buffing and mechanical roughening with other abrasives. You may use together.
【0006】本発明では、内層回路板表面の十点平均粗
さ(Rz)が5μm以上であることが好ましく、更に1
0μm以上であることが好ましい。表面粗さは、JIS
B601により規定されており、十点平均粗さ(R
z)はそれによる。本発明に使用される内層回路板やプ
リプレグに使用される樹脂として、フェノール樹脂、エ
ポキシ樹脂、不飽和ポリエステル樹脂、ポリイミド樹
脂、ポリブタジエン樹脂、ポリアミド樹脂、ポリスルホ
ン樹脂、ポリフェニレンサルファイド樹脂、ポリフェニ
レンエーテル樹脂、ポリブチレンテレフタレート樹脂、
フッソ樹脂等の単独、変性物、混合物等が挙げられる。In the present invention, the ten-point average roughness (Rz) of the inner layer circuit board surface is preferably 5 μm or more, and more preferably 1 μm or more.
It is preferably at least 0 μm. Surface roughness is JIS
B601, the ten-point average roughness (R
z) is based on it. As the resin used for the inner layer circuit board or prepreg used in the present invention, phenol resin, epoxy resin, unsaturated polyester resin, polyimide resin, polybutadiene resin, polyamide resin, polysulfone resin, polyphenylene sulfide resin, polyphenylene ether resin, poly Butylene terephthalate resin,
A single, modified, or a mixture of a fluorine resin and the like can be given.
【0007】内層回路板は前記樹脂のワニスを繊維基材
に含浸乾燥してプリプレグとし、このプリプレグを所定
枚数重ね、金属箔例えば銅箔を重ねて加熱加圧して金属
箔張積層板を製造し、これを回路加工することによって
得られる。一般に銅箔は光沢面と粗化面からなってお
り、粗化面の表面粗さは銅箔厚み及び用途によって異な
るが一般的に十点平均粗さ(Rz)2〜15μmのもの
が使用される。The inner-layer circuit board is prepared by impregnating the resin varnish into a fiber base material and drying to form a prepreg, stacking a predetermined number of the prepregs, stacking a metal foil, for example, a copper foil, and applying heat and pressure to produce a metal foil-clad laminate. , Obtained by circuit processing. Generally, a copper foil is composed of a glossy surface and a roughened surface, and the surface roughness of the roughened surface varies depending on the copper foil thickness and application, but generally a ten-point average roughness (Rz) of 2 to 15 μm is used. You.
【0008】繊維基材としてはガラス繊維の織布、不織
布、マット、芳香族ポリアミド繊維の織布、不織布、マ
ットなどが使用される。上記金属箔張積層板に回路加工
を施し、その後基板表面を粗化処理する。粗化処理とし
ては、バフ又はその他の研磨剤により機械的に表面を粗
化した後に薬品で処理しても良く、直接薬品により粗化
処理しても良い。薬品としては前述の過マンガン酸カ
リ、濃硫酸又はクロム酸等を用いて化学的に粗化する。
プリプレグに接する金属箔からなる回路パターン表面
は、公知の酸化処理や酸化還元処理する。接着用のプリ
プレグとしては、前記内層回路板の製造に用いたプリプ
レグと同じものを用いるのが望ましい。多層プリント配
線板としたときの全体の材質が同じとなるので熱膨張収
縮などの特性が均一化でき、また製造上からも多種類の
材質を用いることによるコストアップを無くすことがで
きるためである。As the fiber base material, woven fabric, nonwoven fabric, mat of glass fiber, woven fabric, nonwoven fabric, mat of aromatic polyamide fiber and the like are used. The metal foil-clad laminate is subjected to circuit processing, and then the surface of the substrate is roughened. As the roughening treatment, the surface may be mechanically roughened with a buff or another abrasive and then treated with a chemical, or may be directly roughened with a chemical. As the chemical, the above-mentioned potassium permanganate, concentrated sulfuric acid, chromic acid, or the like is used to chemically roughen.
The surface of the circuit pattern made of metal foil in contact with the prepreg is subjected to a known oxidation treatment or oxidation-reduction treatment. As the prepreg for bonding, it is preferable to use the same prepreg used for manufacturing the inner layer circuit board. This is because the same material is used as the whole material when a multilayer printed wiring board is used, so that properties such as thermal expansion and contraction can be made uniform, and cost increases due to the use of various types of materials can be eliminated from the manufacturing perspective. .
【0009】積層成形については、通常の多層板の積層
成形と同様に、従来から採用されている条件で行うこと
ができる、この条件は、おおむね、温度100〜200
℃、圧力0.5〜20MPa、加熱時間10〜120分
間とされるが、接着用プリプレグの樹脂組成によって適
宣の条件が選定される。[0009] The lamination molding can be carried out under conventionally employed conditions, similarly to the ordinary lamination molding of a multilayer board.
C., pressure 0.5 to 20 MPa, and heating time 10 to 120 minutes. Appropriate conditions are selected according to the resin composition of the adhesive prepreg.
【0010】[0010]
【実施例】(実施例1)ビスフェノールAノボラック型
エポキシ樹脂(大日本インキ化学工業株式会社製、エピ
クロンN−868(商品名)を使用した)50重量部、
ビスフェノールAノボラック樹脂(油化シェルエポキシ
株式会社製、YLH−129(商品名)を使用した)4
0重量部、ブロム化ビスフェノールA型エポキシ樹脂
(住友化学工業株式会社製、ESB−400(商品名)
を使用した)50重量部及び1−シアノエチル−2−フ
ェニルイミダゾール1重量部をメチルエチルケトン90
重量部に溶解してワニスとした。このワニスを100μ
mのガラス織布(MIL品番2116タイプ)に含浸
し、150℃の乾燥器中で4分間乾燥し、B−ステージ
状態のプリプレグを得た。得られたプリプレグ4枚を重
ねて、その両側に厚み35μm(粗化面表面粗さRz=
9.4μm)の銅箔を配し、圧力2MPa、温度170
℃で100分間加熱加圧して両面銅張積層板を得た。こ
の両面銅張積層板を所定のパターンエッチングを施し内
層回路板を得た。この内層回路板表面の凹凸はRz=
9.4μmであった。なお銅箔粗化面及び内層回路板表
面の凹凸は株式会社東京精密製商品名、サーフコム(Su
rfcom)で測定した。次にこのパターンエッチングされ
た内層回路板表面を過マンガン酸カリ(シップレイ(Sh
iply)社、CIRCUPOSIT ROMOTER3308)を用いて8
5℃5分間処理を行った。この内層回路板表面粗さはR
z=10.9μmであり、その後、導体である銅箔パタ
ーンに所定の酸化還元処理を行った。このようにして得
られた内層回路板の上下にそれぞれ前記のプリプレグを
1枚、更に18μm銅箔を置き、温度175℃で90分
加熱加圧し多層板Aを得た。(Example 1) 50 parts by weight of bisphenol A novolak type epoxy resin (using Epicron N-868 (trade name) manufactured by Dainippon Ink and Chemicals, Inc.)
Bisphenol A novolak resin (using YLH-129 (trade name) manufactured by Yuka Shell Epoxy Co., Ltd.) 4
0 parts by weight, brominated bisphenol A type epoxy resin (ESB-400 (trade name) manufactured by Sumitomo Chemical Co., Ltd.)
50 parts by weight and 1 part by weight of 1-cyanoethyl-2-phenylimidazole were added to 90 parts of methyl ethyl ketone.
The varnish was dissolved in parts by weight. 100μ of this varnish
m woven glass fabric (MIL part number 2116 type) and dried in a dryer at 150 ° C. for 4 minutes to obtain a B-stage prepreg. The obtained four prepregs are stacked, and a thickness of 35 μm (roughened surface roughness Rz =
9.4 μm) copper foil, pressure 2 MPa, temperature 170
The mixture was heated and pressed at 100 ° C. for 100 minutes to obtain a double-sided copper-clad laminate. This double-sided copper-clad laminate was subjected to a predetermined pattern etching to obtain an inner layer circuit board. The irregularities on the surface of the inner circuit board are represented by Rz =
It was 9.4 μm. The roughened surface of the copper foil and the surface of the inner layer circuit board are manufactured by Tokyo Seimitsu Co., Ltd.
rfcom). Next, the surface of the inner layer circuit board subjected to the pattern etching is coated with potassium permanganate (Shipley (Sh
iply) using CIRCUPOSIT ROMOTER 3308)
The treatment was performed at 5 ° C. for 5 minutes. The surface roughness of the inner circuit board is R
z = 10.9 μm. Thereafter, a predetermined oxidation-reduction treatment was performed on the copper foil pattern as a conductor. One prepreg and 18 μm copper foil were placed on the upper and lower sides of the inner circuit board thus obtained, respectively, and heated and pressed at a temperature of 175 ° C. for 90 minutes to obtain a multilayer board A.
【0011】(実施例2)実施例1と同様にして、厚み
35μmで粗化面の表面粗さがRz=3.9μmの銅箔
を用いた両面銅張積層板を作製し、この両面銅張積層板
を所定のパターンエッチングを施し内層回路板を得た。
この内層回路板の表面粗さは、Rz=3.9μmであ
り、粗化処理後の内層回路板表面粗さは、Rz=6.2
μmであった。そしてこの内層回路板を用いて実施例1
と同様にして多層板Bを得た。Example 2 In the same manner as in Example 1, a double-sided copper-clad laminate using a copper foil having a thickness of 35 μm and a roughened surface having a surface roughness of Rz = 3.9 μm was prepared. The laminated laminate was subjected to a predetermined pattern etching to obtain an inner circuit board.
The surface roughness of the inner circuit board is Rz = 3.9 μm, and the surface roughness of the inner circuit board after the roughening treatment is Rz = 6.2.
μm. Example 1 using this inner layer circuit board
In the same manner as in the above, a multilayer board B was obtained.
【0012】(比較例1)実施例1における粗化処理を
行わなかった他は実施例1同様にして多層板Cを得た。Comparative Example 1 A multilayer board C was obtained in the same manner as in Example 1 except that the roughening treatment was not performed.
【0013】(比較例2)実施例2における粗化処理を
行わなかった他は実施例2と同様にして多層板Dを得
た。Comparative Example 2 A multilayer board D was obtained in the same manner as in Example 2 except that the roughening treatment was not performed.
【0014】実施例1,2及び比較例1,2で得られた
多層板を用いて吸湿半田耐熱性、プリプレグと基板間の
引き剥がし強さの評価を行い、その結果を表1に示し
た。The multilayer boards obtained in Examples 1 and 2 and Comparative Examples 1 and 2 were evaluated for moisture absorption solder heat resistance and peel strength between a prepreg and a substrate. The results are shown in Table 1. .
【0015】吸湿半田耐熱性は121℃、2atmのプ
レッシャークッカー試験機で所定時間吸湿させた後、2
60℃の半田に20秒浸漬させ、外観を目視により評価
し、ふくれの無いものをOK、ふくれのあるものをNG
とした。プリプレグと内層回路基板間の接着性は、多層
板から100×25mmの試験片を切り出し、片側の最
外層の銅箔とプリプレグ1枚からなる絶縁層を10mm
幅の帯状部を残して引き剥がし、帯状部の端を引き剥が
し、その先端を試験機のつかみ具でつかみ、試験片面と
垂直方向に50mm/分で引張り速度で引き剥がした
時、引き剥がすために必要な荷重を測定して引き剥がし
強さとした。The heat resistance of the solder after absorption is 121 ° C. and 2 atm.
Immerse in solder at 60 ° C for 20 seconds, and evaluate the appearance by visual inspection. Those without blisters are OK, those with blisters are NG.
And The adhesion between the prepreg and the inner layer circuit board was determined by cutting out a 100 × 25 mm test piece from the multilayer board and forming an outermost layer of copper foil on one side and an insulating layer made of one prepreg into a 10 mm piece.
Peeling off the strip with the width of the strip remaining, peeling off the end of the strip, grasping the tip with the gripper of the testing machine, and peeling off at the pulling speed of 50 mm / min in the direction perpendicular to the surface of the test piece. The required load was measured to determine the peel strength.
【0016】[0016]
【表1】 項目 実施例1 実施例2 比較例1 比較例2 多層板A 多層板B 多層板C 多層板D 基板表面粗さ(Rz、μm) 9.4 3.9 9.4 3.9 (粗化処理前) 基板表面粗さ(Rz、μm) 10.9 6.2 − − (粗化処理後) 引き剥がし強さ(KN/m) 0.81 0.63 0.73 0.49 耐熱性 状態 OK OK OK OK PCT-2h OK OK OK NG PCT-3h OK NG OK NG PCT-4h OK NG NG NG [Table 1] Item Example 1 Example 2 Comparative example 1 Comparative example 2 Multilayer board A Multilayer board B Multilayer board C Multilayer board D Substrate surface roughness (Rz, μm) 9.4 3.9 9.4 3.9 (Roughening treatment Before) Substrate surface roughness (Rz, μm) 10.9 6.2-- (After roughening treatment) Peel strength (KN / m) 0.81 0.63 0.73 0.49 Heat resistance State OK OK OK OK PCT-2h OK OK OK NG PCT-3h OK NG OK NG PCT-4h OK NG NG NG
【0017】表1より、本発明の基板表面を薬品処理し
た実施例1、2は、それに対応する薬品処理しない比較
例1、2に比べ、引き剥がし強さが高く、これにより吸
湿半田耐熱性が著しく向上する。本発明は、特に銅箔の
粗化面の表面粗さが小さい薄い銅箔を用いた場合にプリ
プレグと内層回路基板表面との接着性が高くなる。From Table 1, it can be seen that Examples 1 and 2 in which the substrate surface of the present invention was treated with chemicals had higher peeling strengths than Comparative Examples 1 and 2 in which the chemical treatment was not performed, and therefore, the heat resistance of the moisture absorption solder. Is significantly improved. According to the present invention, the adhesiveness between the prepreg and the surface of the inner layer circuit board is increased particularly when a thin copper foil having a small surface roughness on the roughened surface of the copper foil is used.
【0018】[0018]
【発明の効果】本発明の多層プリント配線板の製造方法
によれば、基板表面を粗化処理することによりプリプレ
グと基板表面の接着性を、従来設備で且つ安価に向上さ
せることができる。According to the method of manufacturing a multilayer printed wiring board of the present invention, the adhesion between the prepreg and the substrate surface can be improved by using conventional equipment and at low cost by roughening the substrate surface.
Claims (2)
プレグを介して積層接着する多層プリント配線板の製造
方法において、プリプレグと接する内層回路板表面を薬
品により粗化処理することを特徴とする多層プリント配
線板の製造方法。1. A method for manufacturing a multilayer printed wiring board in which an inner circuit board on which a circuit pattern is formed is laminated and bonded via a prepreg, wherein the surface of the inner circuit board in contact with the prepreg is roughened by a chemical. Manufacturing method of wiring board.
が5μm以上である請求項1に記載の多層プリント配線
板の製造方法。2. Ten-point average roughness (Rz) of the surface of the inner circuit board
2. The method for producing a multilayer printed wiring board according to claim 1, wherein the thickness is 5 μm or more.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3862798A JP4099681B2 (en) | 1998-02-20 | 1998-02-20 | Manufacturing method of multilayer printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3862798A JP4099681B2 (en) | 1998-02-20 | 1998-02-20 | Manufacturing method of multilayer printed wiring board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH11238965A true JPH11238965A (en) | 1999-08-31 |
JP4099681B2 JP4099681B2 (en) | 2008-06-11 |
Family
ID=12530487
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3862798A Expired - Fee Related JP4099681B2 (en) | 1998-02-20 | 1998-02-20 | Manufacturing method of multilayer printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4099681B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002217544A (en) * | 2001-01-18 | 2002-08-02 | Ngk Spark Plug Co Ltd | Wiring board |
WO2011061969A1 (en) * | 2009-11-18 | 2011-05-26 | 株式会社フジクラ | Partially multilayer wiring board and method for producing same |
-
1998
- 1998-02-20 JP JP3862798A patent/JP4099681B2/en not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002217544A (en) * | 2001-01-18 | 2002-08-02 | Ngk Spark Plug Co Ltd | Wiring board |
JP4685978B2 (en) * | 2001-01-18 | 2011-05-18 | 日本特殊陶業株式会社 | Wiring board |
WO2011061969A1 (en) * | 2009-11-18 | 2011-05-26 | 株式会社フジクラ | Partially multilayer wiring board and method for producing same |
CN102484952A (en) * | 2009-11-18 | 2012-05-30 | 株式会社藤仓 | Partially multilayer wiring board and method for producing same |
JPWO2011061969A1 (en) * | 2009-11-18 | 2013-04-04 | 株式会社フジクラ | Partial multilayer wiring board and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
JP4099681B2 (en) | 2008-06-11 |
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