JPH02277294A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPH02277294A
JPH02277294A JP9834989A JP9834989A JPH02277294A JP H02277294 A JPH02277294 A JP H02277294A JP 9834989 A JP9834989 A JP 9834989A JP 9834989 A JP9834989 A JP 9834989A JP H02277294 A JPH02277294 A JP H02277294A
Authority
JP
Japan
Prior art keywords
layer material
inner layer
circuit
printed wiring
laminate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9834989A
Other languages
Japanese (ja)
Inventor
Kunihiro Tsurumaru
鶴丸 邦浩
Sunao Ikoma
生駒 直
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP9834989A priority Critical patent/JPH02277294A/en
Publication of JPH02277294A publication Critical patent/JPH02277294A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To improve interlayer adhesion and halo resistance by forming a laminate in which outer layer material is arranged at the outermost layer through a prepreg layer at the surface after treating the surface of circuit copper with silane coupling agent. CONSTITUTION:A laminate is formed in which outer layer material is arranged at the outermost layer through a prepreg layer at the surface of inner layer material after treating the surface of circuit copper of inner layer material, where electric circuits are formed at a single-sided or double-sided copper-clad laminate, by spray, etc., using solution wherein silane coupling agent is dissolved or dispersed in solvent such as water, etc. Hereby, the adhesion at the circuit surface of the inner layer material can be improved, and since there is no black copper oxide film at the surface, the halo resistance can be improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電子機器、電気機器、コンピューター、通信機
器等に用すられるプリント配線板の製造方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing printed wiring boards used in electronic equipment, electrical equipment, computers, communication equipment, etc.

〔従来の技術〕[Conventional technology]

従来、プリント配線板は片面又は両面銅張積層板の銅箔
面に回路形成したものを内層材とし、内層材表面を粗化
、或は黒化処理等をおこなってからプリプレグ層を介し
、最外層に片面鋼張積層板や銅箔を外層材として配設し
た積層体を積層成形し一体化して得られるが、従来のパ
ターン回路間隔では上記方法でよいが、パターン回路間
隔が狭くなるファインパターンでは回路面積が増加し内
層材とプリプレグとの接着性が低下し、ドリル加工等の
穴あけ時の衝撃で開穴部周辺が層間剥離し耐ハロー性が
低下する問題があった。
Conventionally, printed wiring boards are made by forming a circuit on the copper foil surface of a single-sided or double-sided copper-clad laminate as an inner layer material, and after roughening or blackening the surface of the inner layer material, the final layer is bonded via a prepreg layer. It is obtained by laminating and integrally molding a laminate in which a single-sided steel-clad laminate or copper foil is arranged as an outer layer material.The above method is sufficient for conventional pattern circuit spacing, but fine patterns with narrow pattern circuit spacing However, there was a problem in that the circuit area increased, the adhesiveness between the inner layer material and the prepreg decreased, and the impact during drilling etc. caused delamination in the vicinity of the hole, resulting in a decrease in halo resistance.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の技術で述べたように、内層材表面をサンドベーパ
ー サンドブラスト等で粗化する方法は均一な粗化がで
きず回路を傷つける欠点があり、黒化処理では粗面表面
の黒色酸化鋼級膜のため、耐ハロー性が低下する欠点が
ある。本発明は従来の技術における上述の問題点に鑑み
てなされたもので、その目的とするところは層間接着性
に優れ、且つ耐ハロー性のよいプリント配線板の製造方
法を提供することにある。
As described in the conventional technology, the method of roughening the inner layer material surface using sand vapor, sandblasting, etc. has the drawback that it cannot achieve uniform roughening and damages the circuit. Therefore, there is a drawback that halo resistance decreases. The present invention has been made in view of the above-mentioned problems in the prior art, and its purpose is to provide a method for manufacturing a printed wiring board that has excellent interlayer adhesion and good halo resistance.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は内層材の回路鋼表面をシランカーlプリング剤
で処理してから、内層材表面にプリプレグ層を介し最外
層に外層材を配設した積層体を積層成形し一体化するこ
とを特徴とするプリント配線板の製造方法のため、内層
材の回路表面の接着性を向上させることができ、且つ表
面に黒色酸化銅皮膜がないので耐ハロー性を向上させる
ことができたもので、以下本発明の詳細な説明する。
The present invention is characterized in that the circuit steel surface of the inner layer material is treated with a silancar l pulling agent, and then a laminate in which the outer layer material is disposed on the outermost layer with a prepreg layer interposed on the surface of the inner layer material is laminated and integrated. This method of manufacturing printed wiring boards improves the adhesion of the circuit surface of the inner layer material, and since there is no black copper oxide film on the surface, it improves halo resistance. Detailed description of the invention.

本発明に用いる内層材としてはフェノール樹脂クレゾー
ル樹脂、エポキシ樹脂、不飽和ポリエステル樹脂、ポリ
イミド樹脂、ポリブタジェン樹脂、ポリフェニレンサル
ファイド樹脂、ポリエチレンテレフタレート樹脂、ポリ
エチレンテレフタレート樹脂、弗化樹脂等の樹脂と、ガ
ラス、アスベスト等の無機繊維やポリエステル、ポリア
クリル、ポリアミド、ポリビニルアルコール等の有機合
成繊維や木綿等の天然繊維からなる織布、不織布、マッ
ト或は紙又はこれらの胡合せ基材とからなる片面又は両
面銅張積層板に電気回路を形成したもので、回路鋼表面
にビニルトリクロロシランビニルトリスベータメトキシ
エトキシシラン等のシランカーフプリング剤を水或はア
ルコール、ケトン類の溶媒に溶解或は分散した溶液をス
プレー噴霧、塗布、浸漬、流延等で処理してから、該内
層材表面に前記樹脂と基材とからなるプリプレグを所要
枚数介し、最外層に片面金属張積層板や金属箔からなる
外層材を配設した積層体を多段プレス法、マルチロール
法、タプルベルト法、ドラム法、無圧連続加熱法等で積
層成形し一体化するものである。
Inner layer materials used in the present invention include resins such as phenolic resin cresol resin, epoxy resin, unsaturated polyester resin, polyimide resin, polybutadiene resin, polyphenylene sulfide resin, polyethylene terephthalate resin, polyethylene terephthalate resin, and fluorinated resin, glass, and asbestos. Woven fabrics, non-woven fabrics, mats or paper made of inorganic fibers such as polyester, polyacrylic, polyamide, polyvinyl alcohol, etc., organic synthetic fibers such as cotton, natural fibers such as cotton, or single-sided or double-sided copper fabrics made of these mating base materials. An electric circuit is formed on a stretched laminate, and a solution of a silane kerf pulling agent such as vinyltrichlorosilane vinyltrisbetamethoxyethoxysilane dissolved or dispersed in water, alcohol, or ketone solvent is sprayed onto the surface of the circuit steel. After processing by spraying, coating, dipping, casting, etc., a required number of prepregs made of the resin and base material are interposed on the surface of the inner layer material, and an outer layer material made of a single-sided metal-clad laminate or metal foil is applied as the outermost layer. The arranged laminates are laminated and integrated by a multi-stage press method, a multi-roll method, a tuple belt method, a drum method, a pressureless continuous heating method, etc.

以下本発明を実施例にもとづいて説明する。The present invention will be explained below based on examples.

実施例 厚み1flの両面銅張ガラス布エポキシ樹脂積層板の両
面に回路形成した内層材をブラッシングしてからビニル
トリクロロシランの0.1重it係エチルアルコール溶
液でスプレー噴霧処理後、該内層材の上下面に厚さ0.
1ffのガラス布エポキシ樹脂プリプレグを夫々2枚づ
つ介し最外層に厚さ35ミクロンの銅箔を配設した積層
体を40 Kq/d 、  165℃で60分間積層底
形して4層回路プリント配線板を得た。
Example After brushing the inner layer material with circuits formed on both sides of a 1 fl thick double-sided copper-clad glass cloth epoxy resin laminate, the inner layer material was sprayed with a 0.1 weight ethyl alcohol solution of vinyltrichlorosilane. Thickness 0 on the top and bottom surfaces.
A laminate consisting of two 1ff glass cloth epoxy resin prepregs each with a 35 micron thick copper foil on the outermost layer was laminated at 40 Kq/d at 165°C for 60 minutes to form a 4-layer circuit printed wiring. Got the board.

比較例 実施例と同じ回路形成した内層材をブラッシングしてか
ら90℃に加熱したアルカリ性亜塩素酸ナトリウム水溶
液に10分間浸漬して回路銅に醸化第2銅皮膜を形成後
、その上下面に厚さ0.1龍のガラス布エポキシ樹脂プ
リプレグを夫々2枚づつ介した以外は実施例と同様に処
理して4層面路プリント配線板を得た。
Comparative Example The same circuit-formed inner layer material as in the example was brushed and immersed in an alkaline sodium chlorite aqueous solution heated to 90°C for 10 minutes to form a cupric film on the circuit copper. A four-layer printed wiring board was obtained in the same manner as in the example except that two sheets of glass cloth epoxy resin prepreg each having a thickness of 0.1 mm were interposed.

実施例及び比較例のプリント配線板の性能は第1表のよ
うである。
The performances of the printed wiring boards of Examples and Comparative Examples are shown in Table 1.

注 棗 穴あけ後、鍍金液処理後の水溶液のしみこみ。note Natsumi: Aqueous solution seeps in after drilling and plating solution treatment.

〔発明の効果〕〔Effect of the invention〕

本発明は上述した如く構成されている。特許請求の範囲
第1項に記載したプリント配線板の製造方法によって得
られるプリント配線板は層間接着性及び耐ハロー性が向
上する効果がある。
The present invention is constructed as described above. The printed wiring board obtained by the printed wiring board manufacturing method described in claim 1 has the effect of improving interlayer adhesion and halo resistance.

Claims (1)

【特許請求の範囲】[Claims] (1)内層材の回路銅表面をシランカップリング剤で処
理してから、内層材表面にプリプレグ層を介し最外層に
外層材を配設した積層体を積層成形し一体化することを
特徴とするプリント配線板の製造方法。
(1) The circuit copper surface of the inner layer material is treated with a silane coupling agent, and then a laminate in which the outer layer material is disposed on the outermost layer with a prepreg layer interposed on the surface of the inner layer material is laminated and integrated. A method for manufacturing a printed wiring board.
JP9834989A 1989-04-18 1989-04-18 Manufacture of printed wiring board Pending JPH02277294A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9834989A JPH02277294A (en) 1989-04-18 1989-04-18 Manufacture of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9834989A JPH02277294A (en) 1989-04-18 1989-04-18 Manufacture of printed wiring board

Publications (1)

Publication Number Publication Date
JPH02277294A true JPH02277294A (en) 1990-11-13

Family

ID=14217424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9834989A Pending JPH02277294A (en) 1989-04-18 1989-04-18 Manufacture of printed wiring board

Country Status (1)

Country Link
JP (1) JPH02277294A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07147482A (en) * 1993-11-24 1995-06-06 Matsushita Electric Works Ltd Manufacture of multilayer printed wiring board
JPH07161867A (en) * 1993-12-10 1995-06-23 Nec Corp Semiconductor package
JPH1035164A (en) * 1996-04-25 1998-02-10 Samsung Aerospace Ind Ltd Ic card and manufacture thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07147482A (en) * 1993-11-24 1995-06-06 Matsushita Electric Works Ltd Manufacture of multilayer printed wiring board
JPH07161867A (en) * 1993-12-10 1995-06-23 Nec Corp Semiconductor package
JPH1035164A (en) * 1996-04-25 1998-02-10 Samsung Aerospace Ind Ltd Ic card and manufacture thereof

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