JPH03155189A - Manufacture of multilayer interconnection board - Google Patents
Manufacture of multilayer interconnection boardInfo
- Publication number
- JPH03155189A JPH03155189A JP29540289A JP29540289A JPH03155189A JP H03155189 A JPH03155189 A JP H03155189A JP 29540289 A JP29540289 A JP 29540289A JP 29540289 A JP29540289 A JP 29540289A JP H03155189 A JPH03155189 A JP H03155189A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- layer
- circuit
- resin layer
- layer material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229920005989 resin Polymers 0.000 claims abstract description 44
- 239000011347 resin Substances 0.000 claims abstract description 44
- 239000000463 material Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 5
- 239000011521 glass Substances 0.000 abstract description 5
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 abstract description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 4
- 239000003822 epoxy resin Substances 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000002184 metal Substances 0.000 abstract description 4
- 229920000647 polyepoxide Polymers 0.000 abstract description 4
- 239000011888 foil Substances 0.000 abstract description 3
- QTWJRLJHJPIABL-UHFFFAOYSA-N 2-methylphenol;3-methylphenol;4-methylphenol Chemical compound CC1=CC=C(O)C=C1.CC1=CC=CC(O)=C1.CC1=CC=CC=C1O QTWJRLJHJPIABL-UHFFFAOYSA-N 0.000 abstract description 2
- 229920000742 Cotton Polymers 0.000 abstract description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract description 2
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 239000010425 asbestos Substances 0.000 abstract description 2
- 239000010949 copper Substances 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 abstract description 2
- 229930003836 cresol Natural products 0.000 abstract description 2
- 239000000835 fiber Substances 0.000 abstract description 2
- 239000012784 inorganic fiber Substances 0.000 abstract description 2
- 229910052742 iron Inorganic materials 0.000 abstract description 2
- 229910052759 nickel Inorganic materials 0.000 abstract description 2
- 239000005011 phenolic resin Substances 0.000 abstract description 2
- 229920000728 polyester Polymers 0.000 abstract description 2
- 229910052895 riebeckite Inorganic materials 0.000 abstract description 2
- 239000012209 synthetic fiber Substances 0.000 abstract description 2
- 229920002994 synthetic fiber Polymers 0.000 abstract description 2
- 239000002966 varnish Substances 0.000 abstract description 2
- 229910052725 zinc Inorganic materials 0.000 abstract description 2
- 239000011701 zinc Substances 0.000 abstract description 2
- 238000003848 UV Light-Curing Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 41
- 239000011889 copper foil Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- -1 polybutylene terephthalate Polymers 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000005062 Polybutadiene Substances 0.000 description 1
- 239000004734 Polyphenylene sulfide Substances 0.000 description 1
- 239000004372 Polyvinyl alcohol Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920002857 polybutadiene Polymers 0.000 description 1
- 229920001707 polybutylene terephthalate Polymers 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920000069 polyphenylene sulfide Polymers 0.000 description 1
- 229920002451 polyvinyl alcohol Polymers 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920006337 unsaturated polyester resin Polymers 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電子機器、電気機器、コンピューター、通信機
器等に用いられる多層配線基板の製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a multilayer wiring board used in electronic equipment, electrical equipment, computers, communication equipment, etc.
従来の多層配線基板は内層材表面が回路形成されたまま
のため、内層材と内層材或は内層材と外層材との間に介
在する樹脂層のかなりの量が回路部に起因する凹凸の凹
部を充填するために消費され、眉間樹脂量不足により耐
熱性が低下してbた。In conventional multilayer wiring boards, circuits are still formed on the surface of the inner layer material, so a considerable amount of the resin layer interposed between the inner layer materials or between the inner layer materials and the outer layer materials is free from unevenness caused by the circuit parts. It was consumed to fill the recesses, and the heat resistance decreased due to insufficient amount of resin between the eyebrows.
この対策として層間に介在させる樹脂層の樹脂量全増量
すると積層成形時にスリッピングを発生する問題があっ
た。As a countermeasure to this problem, if the total amount of resin in the resin layer interposed between the layers is increased, there is a problem in that slipping occurs during lamination molding.
従来の技術で述べたように多層配線基板は層間樹脂量不
足により耐熱性が低下しやすく、層間に介在する樹脂層
の樹脂量を増量するとスリリビングの問題がある0本発
明は従来の技術におをする上述の問題点に鑑みてなされ
たもので、その目的きするところはスリッピングを発生
させず、耐熱性のより多層配線基板の製造方法を提供す
ることにある。As described in the conventional technology, heat resistance of multilayer wiring boards tends to decrease due to insufficient amount of interlayer resin, and when the amount of resin in the resin layer interposed between layers is increased, there is a problem of sliving. This method was developed in view of the above-mentioned problems, and its purpose is to provide a method for manufacturing a multilayer wiring board that does not cause slipping and is more heat resistant.
本発明は所要枚数の内層材の各回路形成面に感光性樹脂
層を配設し、回路部以外の樹脂層は硬化残留させると共
に、回路上の樹脂層は除去しその上面及び又は下面に樹
脂層を介して外層材を配設一体化することを特徴とする
多層配線基板の製造方法のため、内層材表面が回路形成
してあ−でも平滑面なため、層間に介在させる樹脂量を
無駄にすることがなくなり上記目的を達成することがで
きたもので、以下本発明の詳細な説明する。In the present invention, a photosensitive resin layer is provided on each circuit forming surface of a required number of inner layer materials, and the resin layer other than the circuit portion is left cured, and the resin layer on the circuit is removed and the upper and/or lower surface is covered with resin. Since the manufacturing method for multilayer wiring boards is characterized by integrating the outer layer material through layers, the surface of the inner layer material is smooth even after circuit formation, so the amount of resin interposed between the layers is wasted. The present invention will now be described in detail.
本発明に用層る内層材としてはフェノール樹脂クレゾー
ル樹脂、エポキシ樹脂、不飽和ポリエステル樹脂、ポリ
イミド樹脂、ポリブタジェン樹脂、ポリフェニレンサル
ファイド樹脂、ポリブチレンテレフタレート樹脂、ポリ
エチレンテレフタレート樹脂、弗化樹脂等の樹脂と、ガ
ラス、アスベスト等の無機繊維やポリエステル、ポリア
クリル、ポリアミド、ポリビニルアルコール等の有機合
成繊維や木綿等の天然Mi維、紙、基材とから、なる片
面又は両面金属張積層板に電気回路を形成したものであ
る。感光性樹脂層としては感光性ドライフィルム、Uv
硬化型ワニスの単独、併用であり、特に限定するもので
はなり0内層材の回路形成面に配設された感光性樹脂層
は回路部以外の樹脂層は硬化残留させると共に回路上の
樹脂層は未硬化状で除去することによって表面平滑な内
層材が得られるものである。内層材間又は内層材と外層
材間に介在させる樹脂層としては内層材に用すたような
樹脂の塗布層、樹脂シート層或は樹脂と基材とからなる
樹脂含浸基材層であり単独或は併用して用層ることがで
きるが、好ましくは厚み均一性を確保するため樹脂含浸
基材を所要枚数用いることが望ましb0外層材としては
銅、アルミニウム、鉄、ニッケル、亜鉛等の単独、合金
、複合からなる金属箔や片面金属張積層板を用いること
ができる。一体化手段としては多段プレス法、真空多段
フレス法、マルチロール法、タプルベルト法ドラム法、
無圧連続加熱法等で積層−本化するものである。Inner layer materials used in the present invention include resins such as phenolic resin cresol resin, epoxy resin, unsaturated polyester resin, polyimide resin, polybutadiene resin, polyphenylene sulfide resin, polybutylene terephthalate resin, polyethylene terephthalate resin, and fluorinated resin, Electric circuits are formed on single-sided or double-sided metal-clad laminates made of inorganic fibers such as glass and asbestos, organic synthetic fibers such as polyester, polyacrylic, polyamide, and polyvinyl alcohol, natural Mi fibers such as cotton, paper, and base materials. This is what I did. As the photosensitive resin layer, photosensitive dry film, Uv
The curable varnish can be used alone or in combination, and there are no particular limitations.The photosensitive resin layer disposed on the circuit forming surface of the inner layer material leaves the resin layer other than the circuit portion cured, and the resin layer on the circuit is left cured. By removing it in an uncured state, an inner layer material with a smooth surface can be obtained. The resin layer interposed between the inner layer materials or between the inner layer material and the outer layer material may be a resin coating layer such as that used for the inner layer material, a resin sheet layer, or a resin-impregnated base material layer consisting of a resin and a base material, and may be used alone. Alternatively, it can be used in combination as a layer, but it is preferable to use the required number of resin-impregnated base materials to ensure thickness uniformity.As the b0 outer layer material, copper, aluminum, iron, nickel, zinc, etc. A single metal foil, an alloy, or a composite metal foil or a single-sided metal-clad laminate can be used. Integration methods include multi-stage press method, vacuum multi-stage Fres method, multi-roll method, tuple belt method, drum method,
Lamination is carried out using a pressureless continuous heating method or the like.
以下本発明を実施例にもとづいて説明する。The present invention will be explained below based on examples.
実施例
厚みQ、45 m+11の両面銅張ガラス基材エポキシ
樹脂積層板(銅箔厚み夫々0.03510g )の両面
に電気回路を形成後、回路形成面にUV硬化樹脂フェス
(松下電工株式会社製、品番バナシーラーCV 700
0 )をスクリーン印刷後、パターンを用いて回路部以
外の樹脂層を硬化残留させると共に、回路上の樹脂層は
未硬化状のまま除去して表面平滑な内層材を得、次に該
内層材の上下蘭に厚みQ、l Mlllのエポキシ樹脂
含浸ガラス布基材を夫々2枚づつ介して外層材として厚
みQ、035fl+の銅箔を配設した積層体を成形圧力
30Kg/、−j 、 tss℃で120分間積層成
形して4層回路配線基板を得た。Example After forming electric circuits on both sides of a double-sided copper-clad glass base epoxy resin laminate (copper foil thickness: 0.03510 g each) with thickness Q of 45 m+11, a UV-cured resin face (manufactured by Matsushita Electric Works Co., Ltd.) was applied to the circuit-forming surface. , Product number Banasealer CV 700
After screen printing 0), the resin layer other than the circuit part is left cured using a pattern, and the resin layer on the circuit is removed in an uncured state to obtain an inner layer material with a smooth surface. A laminate with two epoxy resin-impregnated glass cloth substrates each having a thickness of Q and l Mlll placed on the upper and lower sides and a copper foil having a thickness of Q and 035 fl+ as an outer layer material was formed at a pressure of 30 kg/, -j, tss. Lamination molding was performed at ℃ for 120 minutes to obtain a four-layer circuit wiring board.
比較例
厚み0.6關の両面鋼張ガラス基材エポキシ樹脂積層板
(銅箔厚み夫々0.035 mm )の両面に電気回路
を形成したものをそのまま内層材として用層た以外は実
施例と同様に処理して4層回路配線基板を得た。Comparative Example Same as the example except that a 0.6-thick double-sided steel-clad glass base epoxy resin laminate (copper foil thickness 0.035 mm each) with electric circuits formed on both sides was used as the inner layer material. A four-layer circuit wiring board was obtained by processing in the same manner.
実施例及び比較例の4層回路配線基板の性能は第1表の
ようである。Table 1 shows the performance of the four-layer circuit wiring boards of Examples and Comparative Examples.
注
※ 2 気圧、133℃のプレッシャー、クラカー試験
を40分、60分、90分実施し、後260℃の溶融ハ
ンダに30秒間浸漬しふくれのないものを合格、ふくれ
発生を不合格とした。Note ※ 2 The cracker test was conducted at atmospheric pressure and 133°C for 40, 60, and 90 minutes, and then immersed in molten solder at 260°C for 30 seconds. Those with no blistering were considered to pass, and those with blistering were considered to be failed.
本発明は上述した如く構成されている。特許請求の範囲
に記載した多層配線基板の製造方法で得られた多層配線
基板は耐熱性が向上する効果がある。The present invention is constructed as described above. The multilayer wiring board obtained by the method for manufacturing a multilayer wiring board described in the claims has the effect of improving heat resistance.
Claims (1)
を配設し、回路部以外の樹脂層は硬化残留させると共に
、回路上の樹脂層は除去しその上面及び又は下面に樹脂
層を介して外層材を配設一体化することを特徴とする多
層配線基板の製造方法。(1) A photosensitive resin layer is provided on each circuit forming surface of the required number of inner layer materials, and the resin layer other than the circuit part is left cured, and the resin layer on the circuit is removed and the upper and/or lower surface is covered with resin. A method for manufacturing a multilayer wiring board, characterized in that outer layer materials are arranged and integrated through layers.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29540289A JPH03155189A (en) | 1989-11-14 | 1989-11-14 | Manufacture of multilayer interconnection board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29540289A JPH03155189A (en) | 1989-11-14 | 1989-11-14 | Manufacture of multilayer interconnection board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03155189A true JPH03155189A (en) | 1991-07-03 |
Family
ID=17820148
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29540289A Pending JPH03155189A (en) | 1989-11-14 | 1989-11-14 | Manufacture of multilayer interconnection board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03155189A (en) |
-
1989
- 1989-11-14 JP JP29540289A patent/JPH03155189A/en active Pending
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