JPH02281690A - Manufacture of printed wiring board - Google Patents
Manufacture of printed wiring boardInfo
- Publication number
- JPH02281690A JPH02281690A JP10252189A JP10252189A JPH02281690A JP H02281690 A JPH02281690 A JP H02281690A JP 10252189 A JP10252189 A JP 10252189A JP 10252189 A JP10252189 A JP 10252189A JP H02281690 A JPH02281690 A JP H02281690A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- wiring board
- printed wiring
- roughened
- prepreg
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000463 material Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 10
- 238000000465 moulding Methods 0.000 claims abstract description 6
- 238000007788 roughening Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 13
- 125000001475 halogen functional group Chemical group 0.000 abstract description 10
- 229910052802 copper Inorganic materials 0.000 abstract description 8
- 239000010949 copper Substances 0.000 abstract description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 7
- 239000002184 metal Substances 0.000 abstract description 7
- 239000011888 foil Substances 0.000 abstract description 6
- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 238000003475 lamination Methods 0.000 abstract description 2
- 238000010030 laminating Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 30
- 239000011229 interlayer Substances 0.000 description 9
- 239000004744 fabric Substances 0.000 description 7
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 239000007864 aqueous solution Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- UKLNMMHNWFDKNT-UHFFFAOYSA-M sodium chlorite Chemical compound [Na+].[O-]Cl=O UKLNMMHNWFDKNT-UHFFFAOYSA-M 0.000 description 2
- 229960002218 sodium chlorite Drugs 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004760 aramid Substances 0.000 description 1
- 229920003235 aromatic polyamide Polymers 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910001431 copper ion Inorganic materials 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- ZQLBQWDYEGOYSW-UHFFFAOYSA-L copper;disulfamate Chemical compound [Cu+2].NS([O-])(=O)=O.NS([O-])(=O)=O ZQLBQWDYEGOYSW-UHFFFAOYSA-L 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 229920006305 unsaturated polyester Polymers 0.000 description 1
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
この発明はプリント配線板の製造方法に関するものであ
る。さらに詳しくは、この発明は、内層材とプリプレグ
層との接着性を向上させ、ファインパターン回路を有す
る多層配線板の信頼性を向上させることのできるプリン
ト配線板の新しい製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a printed wiring board. More specifically, the present invention relates to a new method for manufacturing a printed wiring board that can improve the adhesiveness between an inner layer material and a prepreg layer and improve the reliability of a multilayer wiring board having a fine pattern circuit.
(従来の技術)
電気・電子機器、電子計算機、通信機器等に用いられて
いるプリント配線板については、近年の高密度実装の要
請の高まりとともに多層プリント配線板への需要が増大
し、これにともなって多層プリント配線板の信頼性向上
のために種々の工夫がなされてきている。(Prior art) With regard to printed wiring boards used in electrical and electronic equipment, electronic computers, communication equipment, etc., the demand for multilayer printed wiring boards has increased with the increasing demand for high-density packaging in recent years. Accordingly, various efforts have been made to improve the reliability of multilayer printed wiring boards.
従来、このような多層構造を有するプリント配線板につ
いては、たとえば第2図に示したように、片面または両
面銅張積層板の銅箔面に回路(ア)を形成したものを内
層材(イ)とし、この内層材(イ)の表面をサンダー、
ベルトサンダー等によって物理的に粗化し、あるいはこ
の粗化後にアルカリ性亜塩素酸ナトリウム水溶液等で処
理して銅箔回路(ア)の表面に黒色酸化銅皮膜を形成す
る黒化処理してから、プリプレグ層(つ)を介して片面
銅張積層板や銀箔(1)を外層材として配設して一体化
成形することにより製造してきている。Conventionally, for printed wiring boards having such a multilayer structure, as shown in FIG. ), and sand the surface of this inner layer material (a).
The prepreg is then physically roughened using a belt sander, or after this roughening is treated with an alkaline sodium chlorite aqueous solution to form a black copper oxide film on the surface of the copper foil circuit (A). It has been manufactured by disposing a single-sided copper-clad laminate or silver foil (1) as an outer layer material via layers and integrally molding it.
(発明が解決しようとする課題)
上記のような従来の製造法は、これまでのパターン密度
の回路においては信頼性を一応は確保できるものの、近
年の回路密度が著しく増大したファインパターン回路に
おいては、内層材(イ)とプリプレグ層(つ)との間の
層間接着性を確保することが難しくなってきている。こ
れは、プリント配線板における内層材(イ)表面の従来
の回路面積に比べて、ファインパターン回路の場合には
、その回路(ア)の占める面積が著しく大きくなるため
、内層材(イ)の樹脂層とプリプレグ層(つ)との接触
面積が減少し、たとえ銅箔回路(ア)を従来の方法で表
面処理したとしても、この接触面での層間接着性の低下
が避けられないことによる。(Problems to be Solved by the Invention) Although the conventional manufacturing method described above can secure reliability for circuits with conventional pattern densities, it is difficult to achieve reliability in fine pattern circuits where circuit densities have increased significantly in recent years. It has become difficult to ensure interlayer adhesion between the inner layer material (a) and the prepreg layer (t). This is because in the case of a fine pattern circuit, the area occupied by the circuit (A) is significantly larger than the conventional circuit area on the surface of the inner layer material (A) in a printed wiring board. This is because the contact area between the resin layer and the prepreg layer (2) decreases, and even if the copper foil circuit (A) is surface-treated using the conventional method, a decrease in interlayer adhesion at this contact surface is unavoidable. .
このため、従来の製造方法によっては層間接着性が低下
し、ハローの発生と配線板の信頼性の低下が避けられな
かった。For this reason, depending on the conventional manufacturing method, interlayer adhesion deteriorates, and the occurrence of halos and a decrease in reliability of the wiring board are unavoidable.
この発明は、以上の通りの事情に鑑みてなされたもので
あり、従来の多層プリント配線板の製造方法の欠点を改
善し、ファインパターン回路、すなわち内層材表面の回
路面積が大きくなっても層間接着性が良好であって、耐
ハロー性に優れ、多層配線板の信頼性を向上させること
のできる新しい製造方法を提供することを目的としてい
る。This invention was made in view of the above circumstances, and it improves the shortcomings of the conventional multilayer printed wiring board manufacturing method. The object of the present invention is to provide a new manufacturing method that has good adhesiveness, excellent halo resistance, and can improve the reliability of multilayer wiring boards.
(課題を解決するための手段)
この発明は、上記の課題を解決するものとして、内層材
の回路を陰極処理して粗面化し、次いでプリプレグを介
して外層材を配設しな′lII層体を一体化成形するこ
とを特徴とするプリント配線板の製造方法を提供する。(Means for Solving the Problem) The present invention solves the above problems by roughening the circuit of the inner layer material by cathodic treatment, and then disposing the outer layer material through the prepreg. Provided is a method for manufacturing a printed wiring board characterized by integrally molding the body.
添付した図面の第1図に沿ってこの発明の製造方法につ
いて次に詳しく説明する。The manufacturing method of the present invention will now be described in detail with reference to FIG. 1 of the attached drawings.
(a) プリプレグおよび銅箔等の金属箔から成形し
た片面または両面に回路(1)を有する内層材(2)の
回路(1)表面を陰極処理によって粗面化する。(a) The surface of the circuit (1) of the inner layer material (2) having the circuit (1) on one or both sides formed from prepreg and metal foil such as copper foil is roughened by cathodic treatment.
この時の内層材(2)を形成するプリプレグには特にそ
の種類に限定はなく、ガラスクロス、紙等の基材にフェ
ノール、エポキシ、ポリイミド、不飽和ポリエステル等
の樹脂を含浸させたものを適宜使用することができ、ま
た、回路(1)についても、銅をはじめとする金属、合
金が使用できる。The prepreg forming the inner layer material (2) at this time is not particularly limited in its type, and may be a base material such as glass cloth or paper impregnated with a resin such as phenol, epoxy, polyimide, or unsaturated polyester. Also, for the circuit (1), metals and alloys including copper can be used.
これらの1リプレグは、たとえば−殻内には1〜3枚程
度使用することができる。For example, about 1 to 3 of these repregs can be used in the shell.
陰極処理は、たとえば銅を対象とする場合には、銅5〜
60g/jおよび硫酸10〜200t/Jの硫酸・硫酸
銅水溶液で10〜50℃の温度において、内層材(2)
の回N(1)(パターンはずべて導通させである)を陰
極として処理し、回路(1)に微細凹凸粗面を形成する
。なお、回路(1)に独立パターンがある場合には、導
電ペースト等によって仮配線して連結しておく。For example, when copper is the target, cathode treatment is performed using copper 5 to
Inner layer material (2) at a temperature of 10 to 50°C with a sulfuric acid/copper sulfate aqueous solution of 60 g/J and 10 to 200 t/J of sulfuric acid.
The circuit (1) is treated as a cathode (all the patterns are conductive) to form a finely uneven rough surface in the circuit (1). Note that if the circuit (1) has independent patterns, they are connected by temporary wiring using conductive paste or the like.
この場合も、硫酸銅に限定されることなく、硼弗化銅、
スルファミン酸銅等の銅イオン含有の電解メツキ液の適
宜なものを用いることができる。処理時間は通常1〜1
0分間程度とすることができる。In this case as well, copper borofluoride, copper borofluoride,
An appropriate electrolytic plating solution containing copper ions such as copper sulfamate can be used. Processing time is usually 1-1
The time can be approximately 0 minutes.
(b) 次いで、得られた表面に、所要枚数のプリプ
レグ(3)と外層材(4)とを配設して積層一体止する
。(b) Next, the required number of prepregs (3) and outer layer material (4) are placed on the obtained surface and laminated together.
プリプレグ(3)は、たとえば1〜3枚穆度配設するの
が好ましいが、特にこれに限定されることはない、プリ
プレグ(4〉としては、内層材(2)の場合と同様にガ
ラスクロス、アラミドクロス、ポリエステルクロスなど
のクロスやマット状物、あるいは不織布や紙などの基材
にエポキシ樹脂、フェノール樹脂、ポリイミド樹脂など
の樹脂を含浸させたものを用いることができる。The prepreg (3) is preferably arranged in a thickness of 1 to 3 sheets, for example, but is not particularly limited to this.As the prepreg (4), glass cloth can be used as in the case of the inner layer material (2). A cloth or mat-like material such as , aramid cloth, or polyester cloth, or a base material such as nonwoven fabric or paper impregnated with a resin such as epoxy resin, phenol resin, or polyimide resin can be used.
なかでもガラスクロスエポキシ樹脂プリプレグが好適な
ものとして例示される。また、外層材(4)としては、
銅、アルミニウム、ステンレス等の金属箔や、あるいは
プリプレグとこれらの金属箔とから片面金属張積層体と
したものを用いることができる。このうち、外層材(4
)として銅箔を用いたものが好適なものの一つとして例
示される。Among these, glass cloth epoxy resin prepreg is exemplified as a suitable one. In addition, as the outer layer material (4),
Metal foils such as copper, aluminum, and stainless steel, or single-sided metal-clad laminates made of prepreg and these metal foils can be used. Of these, the outer layer material (4
) is exemplified as one of the preferred ones using copper foil.
積層一体止成形は、多段プレス、スチロール、ダブルベ
ルト、無圧連続加熱等の従来公知の方法や条件に沿って
適宜に実施することができる。この成形によって一体化
しな積層板の最外層金属箔に回路形成することにより多
層回路板が製造される。The lamination and integral molding can be carried out as appropriate using conventionally known methods and conditions such as multistage press, styrene, double belt, pressureless continuous heating, and the like. A multilayer circuit board is manufactured by forming a circuit on the outermost metal foil layer of the laminated board which is not integrated by this molding.
もちろん、以上の製造上の条件等の細部については、公
知のものを含めて様々な態様が可能であることはいうま
でもない。Of course, it goes without saying that the details of the above manufacturing conditions and the like can be modified in various ways, including known ones.
(作 用)
この発明の製造方法においては、内層材の回路表面を陰
極処理によって粗化することにより、内層材とプリプレ
グ層との層間接着力を大きく向上させ、優れた耐ハロー
性を実現する。(Function) In the manufacturing method of the present invention, by roughening the circuit surface of the inner layer material by cathodic treatment, the interlayer adhesion between the inner layer material and the prepreg layer is greatly improved, and excellent halo resistance is achieved. .
以下、実施例を示してさらに詳しくこの発明の方法につ
いて説明する。Hereinafter, the method of the present invention will be explained in more detail with reference to Examples.
(実施例)
実施例1
厚さ1ff111の両面銅張ガラスエポキシ樹脂積層板
の両面に回路形成し、これを内層材とした。(Example) Example 1 A circuit was formed on both sides of a double-sided copper-clad glass epoxy resin laminate having a thickness of 1FF111, and this was used as an inner layer material.
この内層材の回路を陰極とし、@ 50 g / Jl
、硫酸100f/、11の@電解メツキ液を用い、35
℃の温度において5分間処理し、表面に凹凸粗面を形成
した0次いで厚さ0.1市のガラスクロスエポキシ樹脂
プリプレグを各々2枚づつ内層材の上下両面に配設し、
さらに最外層に厚さ0.035++w+の銅箔を配設し
た。The circuit of this inner layer material is used as a cathode, @ 50 g / Jl
, using sulfuric acid 100f/, 11@electrolytic plating solution, 35
Two glass cloth epoxy resin prepregs each having a thickness of 0.0 and 0.1 mm were treated at a temperature of
Further, a copper foil having a thickness of 0.035++w+ was provided as the outermost layer.
この積層体を401qr/ cllの圧力、165℃の
温度で60分間積層成形し、4層回路プリント配線板を
得た。This laminate was laminated and molded at a pressure of 401 qr/cll and a temperature of 165° C. for 60 minutes to obtain a four-layer circuit printed wiring board.
この配線板について層間接着性と耐ハロー性を評価した
ところ、表1に示した結果を得た。後述の比較例との対
比からも明らかなように、層間接着性は向上し、耐ハロ
ー性は著しく改善されている。When this wiring board was evaluated for interlayer adhesion and halo resistance, the results shown in Table 1 were obtained. As is clear from the comparison with the comparative example described below, the interlayer adhesion was improved and the halo resistance was significantly improved.
なお、耐ハロー性については、スルホール孔あけ後の銅
メツキ液処理にともなう液体浸透性として評価した。Note that halo resistance was evaluated as liquid permeability associated with copper plating liquid treatment after through-hole drilling.
実施例2〜3
陰極処理時間を1分間および8分間として実施例1と同
様に配線板を製造し、層間接着性および耐ハロー性につ
いて評価した。その結果を表1に示したが、いずれも優
れた特性を有していた。Examples 2 to 3 Wiring boards were manufactured in the same manner as in Example 1, with cathode treatment times of 1 minute and 8 minutes, and interlayer adhesion and halo resistance were evaluated. The results are shown in Table 1, and all had excellent properties.
比軸例
実施例1に示した陰極処理を行わずに、NaCl0t
40t/、11 、NaOH15g/Jl 、N
a s P O47t / JおよびNai COs
’zr/1のアルカリ性亜塩素酸ナトリウム水溶液に
90℃で7分間浸漬して黒化処理し、次いで実施例1と
同様にプリプレグを配設して4層プリント配線板を製造
しな。Ratio example Without cathodic treatment shown in Example 1, NaCl0t
40t/, 11, NaOH15g/Jl, N
a s P O47t/J and Nai COs
It was immersed in an alkaline sodium chlorite aqueous solution of 'zr/1 at 90° C. for 7 minutes to perform a blackening treatment, and then a prepreg was provided in the same manner as in Example 1 to produce a 4-layer printed wiring board.
表1に示したように、層間接着性、耐ハロー性は実施例
1〜3に比べてはるかに劣っていた。As shown in Table 1, interlayer adhesion and halo resistance were far inferior to Examples 1 to 3.
表 1
(発明の効果)
この発明の製造方法により、以上詳しく説明した通り、
層間接着性および耐ハロー性を大きく向上させた多層プ
リント配線板が実現される。Table 1 (Effects of the invention) As explained in detail above, the production method of this invention
A multilayer printed wiring board with significantly improved interlayer adhesion and halo resistance is realized.
ファインパターン回路を有する多層プリント配線板の信
頼性を向上させることができる。The reliability of a multilayer printed wiring board having a fine pattern circuit can be improved.
第1図はこの発明の製造方法を例示した工程断面図であ
る。第2図は、従来の方法を示した工程断面図である。
工・・・回 路
2・・・内層材
3・・・プリプレグ
4・・・外 層 材FIG. 1 is a process sectional view illustrating the manufacturing method of the present invention. FIG. 2 is a process sectional view showing a conventional method. Engineering...Circuit 2...Inner layer material 3...Prepreg 4...Outer layer material
Claims (1)
リプレグを介して外層材を配設した積層体を一体化成形
することを特徴とするプリント配線板の製造方法。(1) A method for manufacturing a printed wiring board, which comprises roughening the circuits of the inner layer material by cathodic treatment, and then integrally molding a laminate in which the outer layer material is provided via a prepreg.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10252189A JPH02281690A (en) | 1989-04-21 | 1989-04-21 | Manufacture of printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10252189A JPH02281690A (en) | 1989-04-21 | 1989-04-21 | Manufacture of printed wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02281690A true JPH02281690A (en) | 1990-11-19 |
Family
ID=14329646
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10252189A Pending JPH02281690A (en) | 1989-04-21 | 1989-04-21 | Manufacture of printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02281690A (en) |
-
1989
- 1989-04-21 JP JP10252189A patent/JPH02281690A/en active Pending
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