JPH02305240A - Frame synchronization pick-up device - Google Patents

Abstract

PURPOSE:To acquire frame synchronization in a short time even when lots of bit number of the synchronization bit pattern are used by matching the synchronization bit pattern in a comparatively short pattern length during synchronization pick-up and matching the synchronization bit pattern in a comparatively long pattern length after the synchronization pick-up. CONSTITUTION:When a frame synchronization pick-up signal outputted from a frame correlation section 14 is at a low level, a synchronization bit pattern length switching circuit 18 decreased the pattern length of a bit pattern matching section 13 and the bit pattern matching section 13 outputs a pulse with a higher frequency comparing it with a long pattern length to acquire the frame synchronization in a short time. When the frame synchronization acquiring signal outputted from the frame correlation section 14 is at a high level, the synchronization bit pattern length switching circuit 18 increases the pattern length of the bit pattern matching section 13.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a frame synchronization acquisition device used for frame transmission of digital data.

BACKGROUND OF THE INVENTION FIG. 2 shows a signal format of a frame synchronization system.

As shown in Figures 2(a) and (b), one frame consists of an m-bit synchronization bit pattern and (n-m) bits of data (0<m<n). Therefore, the synchronization bit pattern is inserted in each frame. Based on the synchronization bit pattern, the frame synchronization acquisition device outputs a frame 1 synchronization signal at the first bit of the next data as shown in FIG. 2(C), and continues from this frame synchronization signal to a high level. A frame synchronization acquisition signal is output.

FIG. 3 shows the configuration of a conventional frame synchronization acquisition device.

In FIG. 3, 1 is a data input terminal, 2 is a clock input terminal, data is input in synchronization with the clock, and the clock is supplied to each circuit.

Reference numeral 3 denotes a bit pattern matching unit that takes in data in synchronization with a clock, performs matching of synchronous bit patterns before and after each frame, and outputs a pulse when all bits match. is composed of an n-bit shift register.

Reference numeral 4 denotes a frame correlation unit that removes pseudo synchronization bit patterns that cannot be removed sufficiently by the bit pattern matching unit 3 alone due to frame correlation.The frame correlation unit 4 includes an n-bit shift register and one frame It consists of a counter that counts the number of bits n using a clock, and after synchronization is acquired, it always outputs a frame synchronization signal of only one pulse per frame via terminal 6, and also outputs a frame synchronization signal of only one pulse per frame. If present, a frame synchronization acquisition signal is output via terminal 7.

Note that this frame synchronization acquisition signal becomes low level when even one bit of a focus error occurs in the synchronization bit pattern and this erroneous state continues for a predetermined number of frames or more.

5) The output pulse deviation of the bit pattern matching unit 3 and the position of the frame synchronization signal from the frame correlation unit 4 are constantly monitored, and if the synchronization focus pattern disappears due to a focus error due to a line error, etc., or the position of the synchronization bit pattern is detected. This is a frame synchronization holding section for changing the frame synchronization acquisition signal output from the frame correlating section 4 from high level to low level and restarting the frame synchronization signal acquisition operation when the frame synchronization signal is shifted on the transmitting side.

In this case, the frame correlation unit 4 outputs the frame synchronization signal before restarting the acquisition operation as the free-running timing,
Therefore, the frame synchronization signal is not lost even during the frame synchronization signal reacquisition operation.

Problems to be Solved by the Invention However, in the above-mentioned conventional frame synchronization acquisition device,
If even one bit of the output pulse of the bit pattern matching section 3 is lost due to a line focus error, there is a problem that the synchronization acquisition time becomes long when the number of bits m of the synchronization bit pattern is large.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a frame synchronization acquisition device that can acquire frame synchronization in a short time even when the number of bits in a synchronization bit pattern is large.

Means for Solving the Problems In order to achieve the above object, the present invention matches synchronization bit patterns with a relatively short pattern length during synchronization acquisition, and matches synchronization bit patterns with a relatively long pattern length after synchronization acquisition. It is designed to match.

Effect: With the above configuration, the present invention matches synchronization bit patterns with a relatively short pattern length during synchronization acquisition.
Frame synchronization can be achieved in a short time even when the number of bits in the synchronization bit pattern is large.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a frame synchronization acquisition device according to the present invention.

In FIG. 1, 11 is a data input terminal as shown in FIG. 2(a), 12 is a clock input terminal,
Data is input in synchronization with a clock, and the clock is supplied to each circuit.

The input data from the input terminal 11 is as shown in Fig. 2(a)(b).
), each frame is composed of an m-bit synchronous focus pattern and (n-m) bits of data (0<m<n).

13 captures data in synchronization with the clock, performs matching of the synchronous bit pattern of the pattern length set by the synchronous bit pattern length switching circuit 18 before and after each frame as described later, and when all bits match, The bit pattern matching section 13 is a bit pattern matching section that outputs pulses, and the bit pattern matching section 13 is constituted by an n-bit shift register or the like.

Reference numeral 14 denotes a frame correlation unit that removes pseudo-synchronous bit patterns that cannot be removed sufficiently by the bit pattern matching unit 13 alone due to frame correlation.The frame correlation unit 14 includes an n-bit shift register and a one-frame focus It consists of a counter that counts the number n using a clock.

The frame correlation unit 14 always outputs a frame synchronization signal of only one pulse per frame through the terminal 16 after acquiring synchronization, and also performs frame synchronization when there is a frame synchronization signal of only one pulse per frame. Acquire signal to terminal 1
7, and this frame synchronization acquisition signal becomes low level if even one bit error occurs in the synchronization bit pattern and this error state continues for a predetermined number of frames or more.

15 constantly monitors the position of the frame synchronization signal from the frame correlation section 14 using the output pulse of the bit pattern matching section 13, and detects when the synchronization bit pattern disappears due to a bit error due to a line error, or when a synchronization via pattern is detected. When the position of frame correlator 1 shifts on the transmitting side,
4 is a frame synchronization holding unit for changing the frame synchronization acquisition signal outputted from high level to low level and restarting the frame synchronization signal acquisition operation, and the synchronization focus pattern length switching circuit 18 is a frame synchronization holding unit for changing the frame synchronization acquisition signal output from the frame correlation unit 14 from high level to low level and restarting the frame synchronization signal acquisition operation. The pattern length of the bit pattern matching section 13 is switched according to the acquired signal.

Next, the operation of the above embodiment will be explained.

In FIG. 1, when synchronization is being acquired, that is, when the frame synchronization acquisition signal output from the frame correlation section 14 is at a low level, the synchronization bit pattern length switching circuit 18 shortens the pattern length of the bit pattern matching section 13. , Therefore, the bit pattern matching section 13 is
Pulses are output more frequently than when the pattern length is long, and frame synchronization can be achieved in a short time.

In this case, there is a possibility that the bit pattern matching unit 13 outputs a pulse based on the pseudo synchronization pattern, but this pulse is removed by the frame correlation unit 14, and even if frame synchronization is acquired using the pseudo synchronization pattern, Frame synchronization can be obtained again in a short time, so this is not a problem.

On the other hand, after synchronization is acquired, that is, when the frame synchronization acquisition signal outputted by the frame correlation section 14 is at a low level, the synchronization bit pattern length switching circuit 18 increases the pattern length of the bit pattern matching section 13.

In the above embodiment, the synchronization bit pattern length switching circuit 18 switches the pattern length of the bit pattern matching section 13 in accordance with the frame synchronization acquisition signal from the frame correlating section 14. The length may be changed.

As described in detail, the present invention matches synchronization bit patterns with a relatively short pattern length during synchronization acquisition, and matches the synchronization bit patterns with a relatively long pattern length after synchronization acquisition. Therefore, frame synchronization can be achieved in a short time even when the number of bits in the synchronization bit pattern is large.

[Brief explanation of drawings]

FIG. 2 is a block diagram showing a frame synchronization acquisition device. 13...Video pattern matching section, 14.
. . . Frame correlation section, 15 . . . Frame synchronization holding section, 18 . . . Synchronization bit pattern length switching circuit. Figure 1

Claims (1)

[Claims] Means for matching a synchronization bit pattern composed of a plurality of bits with a variable length, and controlling the matching means to match the synchronization bit pattern with a relatively short pattern length during synchronization acquisition. and means for controlling the matching means to match synchronization bit patterns with a relatively long pattern length after synchronization is acquired.