JP2002271433A - Digital wireless synchronization demodulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale of a shift register, etc., in reproducing a symbol clock for digital wireless synchronization demodulation to control the timing of a reproducing clock by detecting the difference from baseband input phase information which is input delay detected by using a synchronization word pattern. SOLUTION: The shift operation timing of a shift register 120 which accumulates the difference 105 between an input base band signal 101 and a signal delayed from the signal 101 by 1 symbol and which outputs data in a symbol unit is controlled by a register shift timing control section 160. The difference between the synchronization word differential pattern information from a synchronization word differential pattern memory 128 for storing the differential information of symbol data of a prescribed synchronization word pattern and the output from the shift register 120 is calculated, and the differential calculation result is accumulated for each shift clock to store it in a cumulative value memory 140. The shift timing where the differential cumulative value is minimized is detected in a timing calculation circuit 150, and the phase of a reproduced symbol clock is corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator for a digital radio apparatus, and more particularly to a demodulation clock reproducing circuit in which a signal pattern of a frame synchronization signal unique to a system is known in advance.

[0002]

2. Description of the Related Art Generally, in a demodulation circuit for digital radio,
In order to obtain a demodulation reference signal, a clock component on the transmission side is extracted from the received random signal. In order to extract an accurate clock component in a very short time, the transmitting side sends a regularly repeated continuous signal called a so-called preamble pattern, and the receiving side demodulation circuit regularly converts the preamble pattern into a reference phase from the preamble pattern. The baseband displacement.

[0003] With this method, the clock component can be efficiently extracted by the preamble pattern. On the other hand, in order to reliably extract the accurate clock synchronization component, the phase difference of the received signal is required. Depending on the size, a preamble of a sufficient length of several tens of bits is required. However, since the data of the information content to be transmitted is not included in the preamble pattern, the number of data bits is reduced by the number of inserted bits of the preamble, and as a result, transmission efficiency is reduced. For this reason, in many cases, it is usually inserted only at the beginning of communication that requires rapid clock synchronization in a short time.

After the clock synchronization component is extracted, clock synchronization can be stably maintained. However, if the received electric field is weak and the noise component cannot be ignored, or if the received radio wave is interrupted during communication for some reason, clock synchronization becomes unstable due to the noise component, resulting in deterioration of the transmission error rate. In addition, in order to extract a clock synchronization component from random signal components, when a preamble pattern is inserted only at the beginning of communication,
The time until the synchronization becomes longer, and the receiving operation of the signal data becomes unstable.

In order to solve this problem, there has been proposed a method of extracting an accurate clock component using a synchronization word signal when a pattern of a frame synchronization word unique to a system is known in advance. In this method, a circuit for determining the reception timing of a synchronization word is added after a general differential detection and demodulation circuit. More specifically,
Having the baseband information equivalent to the synchronization word in advance,
The correlation with the one-symbol difference pattern is calculated. Since the correlation has a peak in the synchronized state, the position where the correlation has a peak is detected, the phase of the input baseband signal is corrected based on the position information, and then demodulated in the phase determination circuit.

[0006]

When a frame synchronization word pattern signal is used, in order to extract accurate clock synchronization, when the number of registers in the register is N, the number of register stages = (N -2) × Sampling rate + 1 requires a very large number of shift register stages.

The present invention solves the above-mentioned drawbacks of the prior art, and detects a synchronization timing of an input signal using a frame synchronization word pattern stored in a demodulation circuit in advance. It is intended to provide a circuit.

[0008]

According to the present invention, there is provided:
A shift register for storing a difference signal between an input baseband signal and a signal obtained by delaying the input baseband signal by one symbol is used. The output of the shift register in units of symbol intervals and the difference information of each symbol data of a synchronous word pattern stored in advance are used. , The output timing (shift clock timing) of the shift register at which the value obtained by accumulating the phase difference for each shift clock becomes the minimum value is detected, and the phase of the reproduced symbol clock is determined according to the detected timing. In the clock recovery circuit that corrects, the timing of the shift clock of the shift register that accumulates and transfers the input baseband difference signal is varied according to the phase difference between the clock recovery output and the input baseband difference signal.
The required number of shift register stages can be reduced to a certain number or less.

According to the present invention, a digital wireless synchronization demodulation circuit for performing clock synchronization using an incoming synchronization word pattern provides a difference between an input baseband signal and a signal obtained by delaying the baseband signal by one symbol. Means,
Shift register means of a predetermined number of stages for accumulating the difference, register shift timing control means for generating a shift clock for the shift register means, first storage means for storing a one-symbol delay difference of a synchronous word pattern;
The difference between the input baseband difference signal read from the shift register means in symbol interval units and the synchronization word one-symbol delay difference signal read from the first storage means in response to the reproduction clock is calculated for each shift timing. Calculating means for calculating the sum of the differences calculated by the difference calculating means over the synchronous word section, second storing means for storing the sum, and shift timing stored in the second storing means. Timing detection means for detecting the minimum shift timing among the accumulated difference values of the respective synchronization word periods; and timing correction means for correcting the timing of the reproduced symbol clock according to the detected shift timing. Accordingly, the register shift timing control means makes the shift time interval of the shift clock variable.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a digital radio synchronous demodulation circuit according to the present invention. FIG. 1 is a block diagram showing a configuration of an embodiment of a digital wireless synchronous demodulation circuit according to the present invention. FIG. 2 shows a detailed configuration example of the synchronous word phase difference detection circuit in the embodiment, and FIG. 3 is a time chart for explaining the operation.

In FIG. 1, a baseband input phase signal is input to an input 101 of a digital radio synchronous demodulation circuit.
This is the phase information of the reception delay detection signal. The baseband input phase signal 101 is supplied to a one-symbol delay circuit 102 and a difference circuit 103. The difference circuit 103 calculates a difference between the baseband input phase signal 101 and the output signal 104 of the one-symbol delay circuit 102, outputs a difference signal 105 indicating the difference, and outputs an automatic phase control circuit (AFC) 106 described later. And a difference calculation circuit to be supplied to the clock recovery circuit 107. The automatic phase control circuit 106 receives a baseband phase correction signal 1
The absolute phase of the difference signal 105 is adjusted based on
Is supplied to the determination circuit 108. The difference signal 105 is also supplied to a clock recovery circuit 107, which recovers a synchronous demodulation clock. The clock recovery circuit 107 receives a symbol clock synchronization correction signal 1
In response to 51, the timing of the data punching clock recovery in the determination circuit described later is corrected. Its output clock
111 is supplied to the determination circuit 108 and becomes a reference clock for data determination. The determination circuit 108 outputs reproduced data 109 as a result of the determination based on the inputs 111 and 112. In the following description, a signal is designated by a reference number of a signal line in which the signal appears.

The difference output 105 from the difference circuit 103 is also supplied to a symbol shift register 120. The symbol shift register 120 includes a plurality of (N-1) symbols described later with reference to FIG.
It is composed of xm-stage shift registers 120-1 to 120-m (N-1) (m and N are natural numbers), and sequentially shifts the input difference signal 105 by the shift clock 161 from the register shift timing control unit 160. , Shift data in symbol interval units 12
Outputs 1. The shift data 121 is supplied to a phase correction circuit 124, where the absolute phase is corrected. The phase correction circuit 124 includes a phase signal 12 of a system-specific synchronization word pattern described later.
This circuit corrects the absolute phase of the symbol shift register output 121 with reference to 7. The phase correction circuit 124 supplies the shift data 125 whose absolute phase has been corrected to the subtraction circuit 130, outputs a corrected phase signal 126, and supplies the latter to the timing calculation unit 150. The timing calculation unit 150 corrects the baseband phase correction signal 152 by this.

The present apparatus has a synchronization word difference information memory 128, which is a storage device for storing 1-symbol delay difference information relating to a synchronization word unique to the system. This one-symbol delay difference information is supplied to a clock recovery circuit.
In response to the timing signal 110 based on 107 clocks, the difference signal 1
It is supplied to the difference circuit 130 as 29. The difference circuit 130 calculates the difference between the above-described phase correction circuit output 125 and the synchronization word difference signal 129 on a symbol-by-symbol basis, outputs the sum 131 of the difference results, and supplies the difference 131 to the accumulated value memory 140. Circuit. The accumulated value memory 140 is a storage circuit that stores the total value 131 of the difference result, and the difference data stored therein is sequentially read out at each register shift timing described later and supplied to the timing operation circuit 150. You.

The timing operation circuit 150 is an operation circuit for detecting a register shift timing at which the accumulated value becomes minimum. The detected register shift timing is a timing synchronized with the clock phase on the transmission side, and based on this timing, the timing arithmetic circuit 150 sends the baseband phase correction signal 152 and the symbol clock to the automatic phase control circuit 106 and the clock recovery circuit 107, respectively. The synchronization correction signal 151 is output. The timing operation circuit 150 also supplies a signal 153 for controlling the operation mode of the register shift clock 161 to the register shift timing control unit 160.

The register shift timing control section 160
This is a control circuit that outputs a shift operation timing control signal (shift clock) 161 of the symbol shift register 120 in response to an operation mode control signal 153 from the timing operation circuit 150, and controls the shift operation timing of the shift register 120.

FIG. 2 shows a detailed block configuration of the shift register 120, the synchronous word difference information memory 128 and the difference circuit 130. As shown in FIG. 2, the symbol shift register 120 includes m stages of shift registers for each symbol period T. The number m of stages is set to a value predetermined according to the accuracy of dividing one symbol section T. The value m is an arbitrary number far smaller than the conventional [number of symbols × number of samples in one symbol section], as described later. Therefore, assuming that the number of symbols of the synchronization word is N, the entire synchronization word section (N-1) T includes m (N-1) shift registers.

The difference circuit 130 shown in FIG.
, The N-1 multiplication circuits 130-1, 130-2, ..., 130-
(N-1), and these calculate the difference for each symbol and output difference data 131-1, 131-2,..., 131- (N-1). The above-mentioned synchronization word difference pattern memory 128 is specifically composed of N-1 units 128-1, 128-2,..., 128- (N-1). The difference information of the word pattern information is accumulated, and the accumulated difference information is stored in the subtraction circuits 130-1, 130-2,.
(N-1). Each difference result 131-1, 131-2,
.. 131- (N-1) are added to each shift clock timing 161 and supplied to the accumulated value memory 140 for storage. In the timing operation circuit 150, each data is read from the accumulated value memory 140, and the register shift timing having the minimum value among the accumulated values stored in the synchronization word section T is detected.

The operation of this embodiment will be described below with reference to FIGS. 1, 2 and 3. First, a case where the reproduction clock is not stable will be described. In FIG. 1, a baseband input signal phase signal 101 of a reception detection signal is delayed by one symbol time in a one-symbol delay circuit 102,
In the difference circuit 103, the baseband input phase signal 101 and
The difference from the one-symbol delayed signal 104 is calculated to obtain a difference signal 105 from which the influence of the initial phase offset has been removed. The difference signal 105 is supplied to the symbol shift register 120. The difference data 105 input to the shift register 120 is sequentially shifted in response to the output shift clock 161 of the register shift timing control unit 160 controlled by the operation mode control signal 153 from the timing operation circuit 150.

On the other hand, in FIG. 1, the synchronization word difference information memory 128 stores difference information between the system-specific synchronization word and the symbol delay signal, and the data 129 read at the clock timing of the clock recovery circuit 107. Is supplied to the difference circuit 130. Difference circuit 130
Is the shift register output signal 1 in the phase correction circuit 124.
The shift data 125 and the sync word difference signal 129 whose absolute phase is finely adjusted by the sync word difference signal 127 and the sync word difference signal 127
Is calculated at each shift clock timing, the calculation results 131 are summed, sent to the accumulated value memory 141, and stored.

The above difference operation will be described in detail with reference to FIG. The output 105 of the difference circuit 103 is applied to the input of the first stage 120-1 of the shift register of FIG. The difference signal 105 input to the shift register 120-1 is sequentially shifted by a register shift clock 161 (the timing shown in FIG. 3B). The data shifted by the shift register 120 is output for every predetermined number of stages (in units of symbol intervals).
Output as 1-1, 121-2
The differences from the data 128-1, 128-2,... Read from the synchronous word difference information memory 128 in 130-1, 130-2,.

FIG. 3 is a time chart showing details of the register shift clock. In FIG. 3, a waveform (A) shows a one-symbol delayed difference signal 105 of the phase information obtained by the delay detection. The ideal symbol clock timing for symbol determination is indicated by a time point T ₀ , and the symbol section T
In the middle of The timing of the recovered clock, it is desirable to close as much as possible to the timing T _0. The waveform (B) shows the register shift timing in a state where the reproduced clock is not stable, and is evenly arranged in all sections of the symbol. In this embodiment, eight shift clocks 161 are provided at equal time intervals in one symbol section.
1, 120-2,. The shift timing and arrangement of these shift clocks 161 are controlled by the timing arithmetic circuit 150.

Returning to FIG. 2, each difference result output 131-1, 131
Are added in the subtraction circuit 130 and then stored in the accumulated value memory 140. Therefore, the difference between the system synchronization word difference signal 129 and the input baseband signal phase 125 is stored in the accumulated value memory at each register shift timing 161. The smaller this value is, the smaller the timing error between the input baseband signal and the reproduced clock is. Therefore, among the difference data for each shift clock timing stored in the accumulated value memory 140, the timing at which the accumulated value shows the minimum is closest to the clock phase on the transmission side. However, as a result, the accuracy of the reproduced clock is 1/8 of one symbol period T as shown in FIG. After the timing indicating the minimum value is detected by the timing calculation circuit 150, the symbol clock synchronization correction signal 151 and the baseband phase correction signal 1
52 are sent to the clock recovery circuit 107 and the automatic phase control circuit 106, respectively, to correct each timing and phase.

Next, the case where the phase error of the output of the clock recovery circuit is small and the synchronization of the symbol clock is almost established will be described. Figure 3 shows the register shift clock.
As shown in `` Register shift timing when the recovered clock is stable '' in (D), the clock recovery circuit 10
An intermittent operation is performed in which the shift timing interval is set close to, for example, the same time interval as the sampling clock in the vicinity of the symbol timing before and after the symbol timing by 7 and the output of the shift clock 161 is stopped during the remaining period. Since the reproduction clock timing is roughly synchronized with the clock phase on the transmission side, that is, the ideal symbol clock timing, the reproduction clock timing can be arranged in a range where the phase error can be covered without increasing the number of stages of the shift register 120.
The error between the ideal symbol clock position and the reproduced symbol clock can be increased to the accuracy of the sampling clock interval.

More specifically, the shift clock 161 from the register shift timing control section 160 is generated at the timing shown in FIG. 3D, thereby driving the symbol shift register 120, and in the same manner as described above, the synchronous word differential pattern is generated. Calculate the sum of the difference between the signal 128 and the shift register output 125, store it in the accumulated value memory 140, and search for the shift clock timing that minimizes the difference, so that the clock can be reproduced with the sample clock accuracy, The data can be determined well, and the error rate can be improved.

The control of whether the shift clocks are arranged uniformly or concentrated near the symbol clocks is controlled by the operation mode control signal 153 from the timing operation circuit 150.

As apparent from the above description, when the phase error of the clock recovery circuit 107 is large, the shift register 1
The 20 shift clocks 161 are coarsely and evenly arranged, and when the phase error is small, the time interval of the shift clocks is finely arranged in the vicinity of the symbol timing of the clock recovery circuit 107, and the shift is performed according to the state of the clock recovery circuit 107. By changing the time interval of the shift clock of the register 120, the number of stages of the shift register 120 can be reduced, and the circuit configuration can be greatly simplified.

In the embodiment described above, the time interval of the shift clock is variable in accordance with the state of the reproduced clock. However, in the state where the reproduced clock is not stable, the timing is first roughly adjusted in the first step. After that, in the second step, the shift clock is concentrated near the symbol clock at a fine time interval like the sampling clock, so that the clock can be reproduced with high precision by two steps so as to reproduce the clock with high precision. You can also raise it.

As shown in FIG. 3 (C), the synchronization can be gradually performed in several stages. The register shift timing in FIG. 3 shows the register shift timing of the shift clock having an intermediate time interval. Also at this time, the number of stages of the shift register 120 is equal to the first stage, that is, the shift register 12
The shift clock of 0 is transmitted intermittently, and when a predetermined number of clocks are transmitted, the transmission is stopped for the remaining time.

As is clear from the above description, by changing the time interval of the shift clock of the shift register 120 stepwise, the number of stages of the shift register 120 can be further reduced, and the configuration can be simplified.

In this embodiment, the phase information is stored by the register. However, it is not necessary to explain that the same result can be obtained even if the processing is performed by software.

Next, another embodiment of the present invention will be described. The configuration is the same as that of the above-described embodiment, and the shift timing control method of the shift register 120 is different from that of the previous embodiment. In other words, the timing signals generated by the register shift timing control section 160 are different. Therefore, different parts will be described, and the same components will be denoted by the same reference numerals and description thereof will be omitted.

FIG. 4 is an operation time chart for the embodiment. In FIG. 4, a waveform (A) is a phase signal obtained by differential detection, that is, a one-symbol difference signal 105, which is the same as FIG. 3 (A). FIG. 4 shows a synchronization word portion.

In the above embodiment, all the symbols of the synchronization word are always monitored, and the difference information between all the synchronization words and the one-symbol delay is taken into the symbol shift register 120. Since the configuration is such that the minimum synchronization word timing is searched for based on the accumulated value of the result of the subtraction with the synchronization word difference information,
At the end of one sync word, the sync timing was determined. Further, each register and the arithmetic circuit are always operating.

On the other hand, in the present embodiment, the first stage is configured to monitor not the entire synchronization word but only the first few symbols. The input baseband difference of the symbol shift register output 121 is compared with the synchronization word difference information of the section of the first several symbols of the synchronization word stored in advance (4 symbols in period (a) in FIG. 4B). The difference from the phase signal 125 is calculated. At this time, as described in the previous embodiment, the number of shift registers assigned to one symbol section is a fixed number of stages (four in FIG. 4, but may be eight as shown in FIG. 3; Accordingly, the shift clock time intervals of the registers corresponding to the number of stages of the shift register 120 are equally arranged in the symbol section as shown in a period (a) of FIG. 4B. Set roughly. When the approximate symbol timing is detected in the first few symbol sections in the same manner as described in the previous embodiment, in the next stage, all of the synchronization words or the remaining synchronization word sections excluding the first few symbols are re-examined. In FIG. 4, the shift clock 161 of the register 120 is arranged at a fine timing with a shorter time interval (for example, of a sampling clock) concentrated near the detected symbol timing (FIG. 4).
The symbol timing is extracted with high accuracy by the period (b) of (B). In this embodiment, the clock recovery circuit 107
No matter what the state of the symbol clock is, accurate symbol timing can be extracted in a short time, and synchronization can be restored in a short time when a received radio wave is interrupted.

[0035]

As described above, according to the present invention, in a digital radio synchronous demodulation circuit for performing clock synchronization using a synchronization word pattern, an input baseband signal and one
Using a shift register that accumulates a difference signal from the signal delayed by the symbol, calculates the difference between the output of the shift register and the difference information of each symbol data of the synchronization word pattern stored in advance, and calculates the phase difference for each symbol. In the clock recovery circuit for detecting the output timing of the shift register at which the value accumulated in the shift register becomes the minimum value, and correcting the phase of the recovered symbol clock based on the detected timing, the phase difference between the clock recovered output and the input baseband differential signal is calculated. Depending on the situation, the timing of the shift clock of the shift register that accumulates and transfers the input baseband difference signal is made variable, and when the synchronization of the reproduction clock is not established, the shift clock is evenly and roughly arranged in one symbol section, When the clock synchronization is almost established and the phase error is small, the playback clock The configuration is such that shift clocks are finely arranged near the symbol timing of clocks. Therefore, the number of stages of the shift register can be significantly reduced, and the circuit scale can be simplified.

In the first stage, symbol timing detection is first performed roughly using the first few symbols of the synchronization word, and in the second step, the fine synchronization is performed using the remaining synchronization word section excluding the first few symbols. Calibration may be performed to shift to symbol timing detection.
The symbol timing can be extracted at high speed with the same accuracy as the sampling clock regardless of the state of the reproduction clock of the clock reproduction circuit.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a configuration of an embodiment of a digital wireless synchronous demodulation circuit according to the present invention.

FIG. 2 is a functional block diagram showing a specific configuration example of a synchronous word phase difference detection circuit in the embodiment shown in FIG.

FIG. 3 is a time chart for explaining the operation of the embodiment.

FIG. 4 is a time chart for explaining the operation of another embodiment of the digital wireless synchronous demodulation circuit according to the present invention.

[Explanation of symbols]

 102 One-symbol delay circuit 103 Difference circuit 120 Symbol shift register 124 Phase correction circuit 128 Synchronization word difference information memory 130 Difference circuit 140 Accumulated value memory 150 Timing operation circuit 160 Register shift timing controller

Claims (2)

[Claims] 1. A digital wireless synchronization demodulation circuit for performing clock synchronization using an incoming synchronization word pattern, wherein the circuit obtains a difference between an input baseband signal and a signal obtained by delaying the baseband signal by one symbol. Difference means; shift register means of a predetermined number of stages for accumulating the difference; register shift timing control means for generating a shift clock for the shift register means; Storage means; and a difference between an input baseband differential signal read from the shift register means in symbol interval units and a synchronous word one-symbol delayed differential signal read in response to a reproduction clock from the first storage means. Difference calculating means for calculating each shift timing, and said difference calculating means over a synchronization word section Accumulating means for calculating the sum of the differences calculated in the above, second storage means for storing the sum, and among the difference accumulated values for the synchronization word period for each shift timing stored in the second storage means. Timing detection means for detecting the minimum shift timing; and timing correction means for correcting the timing of the reproduced symbol clock in accordance with the detected shift timing, whereby the register shift timing control means A digital wireless synchronous demodulation circuit, wherein a shift time interval of the digital wireless synchronous demodulation is variable. 2. The circuit according to claim 1, wherein the synchronization timing is roughly detected by using the first several symbols of the synchronization word, and then detected by using the synchronization word excluding the several symbols or all the synchronization words. By arranging shift clocks close to the synchronization timing,
A digital wireless synchronous demodulation circuit for extracting a symbol timing of a clock recovery circuit.