JPH02305028A - A/d converter - Google Patents

Abstract

PURPOSE:To simultaneously execute in parallel the measurement of high time resolution and the measurement extending over comparatively many hours by executing the measurement in a period of an independent sample clock at every device. CONSTITUTION:An A/D converter 2 converts an analog input signal to a digital signal in accordance with a clock CLK applied from a sample clock control circuit 1. A data memory 3 stores output data of the A/D converter 2, and a data memory control circuit 4 gives and receives plural measurement control signals consisting of a measurement enable signal AEN, a measurement start signal AST, and a trigger enable signal TEN to and from an external device, an in accordance with these measurement control signals, a data store operation of the data memory 3 is controlled. Subsequently, a trigger control circuit 5 outputs selectively an individual trigger signals and a synchronizing trigger signal applied from the outside to the outside as a synchronizing trigger signal, and also, outputs trigger signal TRIG synchronizing with a clock applied from the sample clock control circuit 1 to the data memory control circuit 4. In such a way, parallel driving between each device can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an A/D conversion device, and more specifically, it provides an A/D conversion device suitable for parallel driving.

<Prior Art> In order to convert analog input signals of a plurality of mutually related channels into digital signals and collect them, a plurality of data collection devices are used, as described in Japanese Patent Publication No. 62-46009, for example. It is being done to synchronize and drive in parallel.

<Problem to be solved by the invention> However, in such a conventional configuration, it is difficult to align the conversion start timing of the A/D converters that constitute each data acquisition device, or to correlate trigger operations between each data acquisition device. It is not possible to perform high time resolution measurements based on the measurement data stored in each data acquisition device, or to perform measurements with a high degree of freedom by combining arbitrary trigger operations. .

The present invention has focused on these points, and its purpose is to provide parallel drive that can align the start timing of A/D conversion of each device and control the trigger operations of each device in a related manner. The object of the present invention is to provide a possible A/D conversion device.

Means for Solving the Problems> The A/D conversion device of the present invention selectively outputs an internal reference clock, an external clock applied from the outside, and an external reference clock to the outside as an external reference clock, and also uses a frequency divider. an A/D converter that converts an analog input signal into a digital signal according to the clock applied from the frequency divider of this sample clock control circuit; a data memory that stores output data of the converter; and a data memory control circuit that transmits and receives a plurality of measurement control signals between the external device and controls the data storage operation of the data memory according to the plurality of measurement control signals. , via a timing control circuit that selectively outputs externally applied individual trigger signals and synchronized trigger signals to the outside as synchronized signals, and synchronizes them with the clock applied from the frequency divider of the sample clock control circuit. Therefore, the present invention is characterized in that it includes a trigger control circuit that outputs to the data memory control circuit, and an arithmetic control section that centrally controls each of these sections.

The A/D conversion device of the present invention enables measurement with high time resolution because the A/D conversion start timings of each device can be aligned, and trigger operations between each device can be controlled in relation to each other. Because of this, it is possible to perform measurements with a high degree of freedom by combining arbitrary trigger operations.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram illustrating the principle of the present invention.
is a sample clock control circuit that controls the generation and switching of the clock CLK, and selectively outputs the internal reference clock 1, an external clock applied from the outside, and an external reference clock to the outside as an external reference clock, as well as to each internal section. . 2 is an A/D converter, which converts an analog input signal into a digital signal in accordance with a clock CLK applied from the sample clock control circuit 1; 3
is a data memory that stores output data of the A/D converter 2. 4 exchanges a plurality of measurement control signals consisting of a measurement enable signal AEN, an iIl constant start signal AST, and a trigger enable signal TEN with an external device (not shown), and performs data storage operations in the data memory 2 according to these measurement control signals. This is a data memory control circuit that controls the data memory.

5 is a trigger control circuit which selectively outputs an externally applied individual trigger signal and a synchronous trigger signal to the outside as a synchronous trigger signal, and also outputs a trigger signal TRIG synchronized with the clock applied from the sample clock control circuit 1. It is output to the data memory control circuit 4. 6 is a calculation control unit (CPU) that centrally controls each unit, and bus 7
It is connected to each part via.

2nd 1 is an explanatory diagram of the parallel connection state of the A/D converter configured as shown in FIG. 1. In FIG. , NO12 to No. are connected as slave machines. The operation switching between the master machine and the slave machine is performed under the control of the respective internal arithmetic control sections. Individual trigger signals are applied only to the master machine.

Analog input signals are applied to each device individually.

An external clock is applied commonly to all devices as needed. The master device's external reference clock output terminal, measurement control signal output terminal, and synchronization 1 to rigging signal output terminal are N.
o, input terminal of external reference clock of slave unit 2, i
The external reference clock output terminal, the measurement control signal output terminal, and the synchronization i~trigger signal output terminal of the No. 2 slave unit are connected to the input terminal of the constant control signal and the synchronization trigger signal, and , 3 are connected to the external reference clock input terminal, the 1111 constant control signal input terminal, and the synchronization trigger signal input terminal, and the following is similarly connected to the external reference clock input terminal of the slave machine No., (K-1>). The output terminal, measurement control signal output terminal, and synchronization trigger signal output terminal are No.

Input terminal for external reference clock of K slave machine.

Connected to the measurement control signal input terminal and the synchronization trigger signal input terminal.

As mentioned above, the measurement control signal includes the measurement enable signal A.
There are three types: EN, measurement start signal AST, and trigger enable signal TEN. Here, the AEN signal is a signal indicating a measurable state, is output from all devices connected in parallel, and is enabled when output from all devices is completed. AST signal is AEN
After the signal is enabled, it is input from the master device to each slave device. Each slave device starts measurement by receiving the AST' signal. The TEN signal is a signal indicating the trigger standby state, and is output from all devices connected in parallel, and becomes enabled when output from all devices is completed.

The operation of the devices connected in this way will be explained.

First, the case where the device operates as a master device or as a standalone device will be explained.

An internal reference clock is selected as the time base clock, and this clock is also sent to each slave device. A/
As the sample clock of the D converter 2, an internal reference clock or a frequency-divided version of the internal reference clock is used. And A.E.
After the N signal is enabled, the A S 'f' signal is sent, and measurement is also started at the same time. In addition, after the 'T' E N signal is enabled, the TRG E N signal is enabled, and the 1-return control circuit 5 is activated, and the individual trigger signal that is input thereafter is accepted. The attached individual trigger signal is output to each slave device as a synchronous trigger signal.

Next, a case where the device operates as a slave device will be explained.

The time base clock input from the master machine is used, and this clock is also sent to subsequent slave machines. This clock or a frequency-divided version of this clock is used as the sample clock of the A/D converter 2. The measurement operation starts after receiving the AST signal input from the master device.

Note that the receiver also sends the attached AST' signal to the subsequent slave device. As a trigger signal, a synchronous trigger signal input from the master machine is accepted, and the received synchronous trigger signal is also sent to subsequent slave machines.

According to such a configuration, during parallel operation by parallel connection as shown in FIG. 2, a common reference clock is supplied to each A/D converter, and the frequency is divided individually by each A/D converter. Therefore, A/D conversion can be performed at individual sample rates.The trigger is invalid until all devices are in the trigger standby state, and the trigger function is valid only for the master device, and each slave The trigger timing of the machine will match the trigger timing of the master machine.Also, the measurement operation in each A/D converter starts at the same time when all devices are ready for measurement, but the end timing of the measurement operation is different. Since each can be set independently and the data length of the data memory 3 can be set arbitrarily, measurement with a high degree of freedom is possible.

FIG. 3 is a configuration explanatory diagram showing an example of the device in FIG. 1, and FIG. 4 is an explanatory diagram when the devices in FIG. 3 are connected in parallel.
The same parts as in the figure and FIG. 2 are given the same reference numerals.

In these figures, CLKIN is an external reference clock that is input from the sample clock generation circuit 1 of the preceding device to the sample clock generation circuit 1 of the subsequent device, and CLKO
UT is an external reference clock outputted from the sample clock generation circuit 1 of the preceding device to the sample clock generation circuit 1 of the subsequent device. AENS- is a signal indicating a measurable state that is output from the data memory control circuit 4 of the preceding device to the data memory control circuit 4 of the succeeding device, and is applied to the base of the transistor Tr1. AENR is a signal indicating a measurable state that is input from the data memory control circuit 4 of each device in the preceding stage to the data memory control circuit 4 of the subsequent device, and is applied to the collector of the transistor Tr1. AENI and AENO are all A/Ns connected in parallel.
This signal indicates the measurable state of the D conversion device, and these AENI and AENO signal lines are connected to the collector of the transistor Tri and have the same potential as the AENR signal, and the AENS- signal of all devices is enabled. It is enabled only when the Note that the transistor T
The collector of r1 is pulled up and the emitter is connected to a common potential point. ASTS is a measurement start signal output from the data memory control circuit 4 of the preceding device to the data memory control circuit 4 of the succeeding device, and is applied to one input terminal of the selector 8.

ASTI is a measurement start signal input from the data memory control circuit 4 of each device in the preceding stage to the data memory control circuit 4 of the subsequent device, and is applied to the other input terminal of the selector 8. ASTR is a measurement start signal that is input to the data memory control circuit 4 of each device via the selector 8. When operating as a master device, the ASTS signal is input, and when operating as a slave device, the ASTI signal is input. is input. ASTO is a measurement start signal output from the preceding device to the succeeding device, and ASTR is output via the selector 8.
The same signal as the signal is output. TENS- is a signal indicating the trigger standby state output from the data memory control circuit 4 of the preceding device to the data memory control circuit 4 of the succeeding device, and is applied to the base of the transistor Tr2.

TENR is a signal indicating the trigger standby state inputted from the data memory control circuit 4 of the preceding device to the data memory control circuit 4 of the subsequent device, and is applied to the collector of the transistor Tr2. TENI and TENO are connected in parallel, and the trigger standby of all A/D converters is a signal representing the state, and the signal lines of these TENI and TENO are connected to the collector of the transistor Tr2.
It has the same potential as the R signal, and becomes enabled only when the TENS- signals of all devices are enabled.

Note that the collector of the transistor Tr2 is pulled up, and the emitter is connected to a common potential point.

MSIDI is a setting operation mode identification signal that is input from the previous device to the subsequent device, and it goes to H level when it is set to operate as a master device, and goes to H level when it is set to operate as a slave device. becomes L level. MSIDO is a set operation mode identification signal output from the preceding device to the succeeding device, and the end of the signal line is connected to a common potential point. TRGEN is a signal that is output from the data memory control circuit 4 to the trigger control circuit 5 in each device and indicates a trigger acceptance state, and TRIG is a trigger signal that is input from the trigger control circuit 5 to the data memory control circuit 4. . TRGI is a synchronous trigger signal that is input from the trigger control circuit 5 of the preceding device to the trigger control circuit 5 of the succeeding device, and TRGO is a synchronous trigger signal that is output from the trigger control circuit 5 of the preceding device to the trigger control circuit 5 of the succeeding device. It's a signal.

FIG. 5 is a configuration explanatory diagram showing a specific example of the sample clock generation circuit 1 of FIG. 2. 9 is internal reference clock IN
Internal reference clock generation circuit that outputs TCLK, 10 is internal reference clock INTCLK, external clock EXTC
A switch 11 for selecting LK and an external reference clock CLKIN is a frequency divider that divides the clock selected by the switch 10 into a desired value and outputs it to each internal section. Note that the output signal of the switch 10 is outputted to a subsequent device as an external reference clock CLKOUT.

FIG. 6 is a configuration explanatory diagram showing a specific example of the trigger control circuit 5 of FIG. 2. In FIG. 12 is a switch for selecting an individual trigger signal and a synchronous trigger signal TRCI; 13 is a switch for selecting and outputting a trigger signal from switch 12; the analog input signal (trigger point data) at the trigger point is converted into digital by A/D converter 2; This is a timing control circuit that corrects the time difference between converting into a signal and outputting it, and then outputs it to the data memory control circuit 4 as a trigger signal TRIG.

Note that the output signal of the switch 12 is outputted to a subsequent device as a synchronization trigger signal TRGO.

The operation of the devices connected as shown in FIG. 4 will be explained.

First, the operation of the master machine will be explained.

The internal reference clock IN is used as a time base clock.
TCLK is selected and this clock is also sent to each slave device as the external reference clock CLKOUT. As the sample clock CLK of the A/D converter 2, an internal reference clock INTCLK or a clock CLK obtained by dividing this clock by a frequency divider 11 is used. ASTS is selected as the measurement start signal ASTR, and this measurement start signal ASTS is
No. 1 as TO. Output to the second slave machine. The trigger control circuit 5 selects one of the trigger signals and outputs it to the internal data memory control circuit 4 as the trigger signal TRIG, and also outputs the No. 1 trigger signal as the synchronous trigger signal TRGO. Output to the second slave machine.

Next, the operation of the slave machine will be explained.

The external reference clock CLKIN input from the master device is used as the time base clock, and this clock is also sent to subsequent slave devices as the external reference clock CLKOUT. As the measurement start signal ASTR, ASTI input from the master device is selected, and this measurement start signal ASTI is also sent to subsequent slave devices as ASTO. The trigger control circuit 5 selects the synchronous trigger signal TRGI inputted from the master device as a trigger signal, and sends it to the subsequent slave devices as a synchronous trigger signal TRGO.

According to such a configuration, a common reference clock is supplied to each A/D converter, and the frequency is divided individually by each A/D converter, so that A/D conversion is performed at individual sample rates. be able to. For example, if the frequency of the reference clock is 10
If it is MHz, the master device divides the frequency by 1/10 and becomes tMs.
ps, and a certain slave machine divides the frequency by 1/100 to 100.
KspS, and other slave machines divide the frequency by 1/2 to 5M5.
The operation ps... is possible.

Furthermore, the data length before and after the trigger point can be arbitrarily set for each device. Specifically, the signal TENS- of each device is enabled from the start of measurement until a predetermined number of data lengths of digital data are stored in the data memory 3 before the trigger point. As a result, only the triggers that occur after the TENS- signal of all devices is enabled, that is, after all devices have finished storing data before the trigger point, are enabled. The data length can be set arbitrarily. The data length after the trigger point can be arbitrarily set for each device as described above, and the data length before and after the trigger point can be arbitrarily set for each device.

FIG. 7 is a flowchart showing the flow of the parallel operation described above.

First, each device reads the level status of the MSIDI signal, and if it is at H level, sets it as the master device.
If it is at L level, it is set as a slave device.

When each device completes the setting operation before starting measurement, the ABNS
- Output a signal. When the AENS- signal is output from all the devices, the AENR signal is enabled all at once, and the measurement becomes possible for the first time at this point.

Thereafter, the master device outputs a measurement start signal ASTS to start measurement. The measurement start signal ASTS output from the master device becomes an ASTO signal for the slave device, and the slave device starts measurement according to this signal.

After the start of measurement, each device outputs a TENS' signal when settings for accepting a trigger, such as storing the required number of data before the trigger point, are completed. TENS from all devices
When the ' signal is output, the TENR signals are enabled all at once, and at this point all devices are in the trigger standby state. Before the TENR signal becomes enabled, neither device is in a state in which it cannot accept a trigger.

After this, when the individual tri-force signal is input to the master machine,
A synchronous trigger signal 7RGO is output from the master machine to all slave machines. The slave device outputs the trigger signal TRIG when this synchronized trigger signal TRGO is input as TRGI, and all devices are triggered.

This trigger signal TRIG stores the address where the trigger data of each device is stored.

1~ After inputting the reload signal, each device independently writes the data of the set data portion. When data writing of a predetermined data length is completed, each device independently ends measurement.

FIG. 8 is a connection diagram of the main parts of FIG. 3, and FIG. 9 is a timing chart for explaining the operation of FIG. 8.

The AENI signal line and the AENO signal line are connected to the collector of the transistor Tr and have the same potential as the AENR signal line. In each device, the AENS- signal is enabled at L level, and the initial state is F[level. Each device outputs the AENS- signal independently, or when the AEMS- signal of any one device goes to H level, the AENR signal goes to L level for all the devices. When the AENS signals of all devices become L level, the transistors Tr of each device are turned off, and the AENR signal becomes H level and enabled. In this way, the slowest AENS
All devices do not become ready for measurement until the - signal (AENS- signal of No and K in FIG. 9) is input.

Note that the TENR signal also operates in the same manner as the AENR signal.

In addition, although the above embodiment describes an example in which the reference clock is supplied from the master device, similar parallel operation is possible by supplying the same external clock to all devices and selecting the external clock in all devices. It is.

By the way, in such a configuration, in order to increase the degree of freedom in measurement, each device ends the measurement independently. This allows the data length of the data memory to be set individually for each device.

However, when inputting an external clock to the master device and supplying it to each slave device, when the clock is switched to the internal clock after the measurement of the master device is completed, the measurement operation of the slave device has not yet finished. Sometimes. In this case, the clock of the slave device will be switched from the external clock to the internal clock during the measurement, which is not preferable.

Such inconvenience can be solved by adding a measurement end signal AEND indicating a measurement end state to the measurement control signal.

FIG. 10 is an explanatory diagram of the configuration showing parts related to the end of measurement and switching of clocks when a measurement end signal AEND is added, and FIG. 11 is an explanatory diagram when the devices in FIG. 10 are connected in parallel. The same parts as in FIGS. 3 and 4 are given the same reference numerals.

AENDR is a signal indicating the measurement completion state that is input from the data memory control circuit 4 of the preceding device to the data memory control circuit 4 of the succeeding device, and is applied to the collector of the transistor Tr3. AENDI and AENDO are signals indicating the measurement end status of all A/D converters connected in parallel, and these AENDI and AENDO signal lines are connected to the collector of transistor Tr3.
Same potential as NDR signal, AENDS of all devices
- It is only enabled when the signal is enabled. Note that the collector of the transistor Tr3 is pulled up, and the emitter is connected to a common potential point. T.B.
CG is a clock switching signal, which is output from the data memory control circuit 4 to the sample clock generation circuit 1.

Since the basic operation of the parallel operation in such a configuration is the same as that of the above-described embodiment, it will be omitted here, and the operation at the end of measurement and the operation related to clock switching will be explained.

FIG. 12 is a connection diagram of the main parts of FIG. 3, and FIG. 13 is a timing chart for explaining the operation of FIG. 12.

The AENDI signal line and the AENDO signal line are connected to the collector of the transistor Tr and have the same potential as the AENDR signal line. In each device, the AENDS- signal is active at L level, and the initial state is H level. Each device outputs the ABNDS- signal independently, but if any one of the devices outputs the AENDS- signal at H level, the AEN
The DR signal goes to L level across all devices. When the AENDS signals of all devices become L level, the transistors Tr of each device are turned off, and the AENDR signal becomes H level and becomes active. in this way,
The slowest AENDS signal (No in Figure 12, A of 2)
All devices do not enter the measurement end state until the ENDS signal is input.

Next, switching of the time base clock will be explained.

When each device becomes capable of measurement, the AENS- signal is set to L level (active) as described above, and the clock switching signal TBCG signal is generated using these AENS- signals and the AENDR signal, and the clock switching signal is The switch 10 in FIG. 5 is controlled in accordance with the signal TBCG signal so that the internal clock is used at all times except during measurement, from when the AENS- signal becomes active until the AENDR signal becomes active.

FIG. 13 is a flowchart showing the flow of parallel operations of the apparatus configured as described above. The difference from the above-mentioned FIG. 7 is two points: the operation at the end of the measurement and the switching of the clock.

<Effects of the Invention> As explained above, according to the present invention, each device can perform measurements with an independent sample clock cycle, so it is possible to simultaneously perform high-time resolution measurements and relatively long-time measurements in parallel. It can be carried out.

Furthermore, since the measurement is configured to start simultaneously after all the devices become ready for measurement, it is not necessary to give a measurement start command to all the devices from the outside.

Further, since the trigger is not activated until all devices are set for trigger standby, the data length before the trigger point can be arbitrarily set for each device.

Furthermore, since the data length of each data memory can be arbitrarily set independently for each device, short-term and long-term measurements can be performed in parallel.

In addition, since the data length before and after the trigger point can be set arbitrarily for each device, for example, if the same analog input signal is input to two A/D converters, one device stores the data before the trigger point. By storing the data after the trigger point in the other device, measurement can be performed with the data length at the time of measurement being doubled.

Furthermore, even if an external clock is used as the time base clock during measurement and switched to an internal clock at other times, there will be no problem in parallel operation of a plurality of devices.

In this way, an A/D conversion device capable of performing various measurements with a high degree of freedom can be realized.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is a parallel connection diagram of the device shown in Fig. 1, Fig. 3 is a configuration explanatory diagram showing one embodiment of Honmaru Akira, and Fig. 4 is the device shown in Fig. 3. 5 is a configuration explanatory diagram showing a specific example of the sample clock generation circuit in the present invention, FIG. 6 is a configuration explanatory diagram showing a specific example of the tri-force control circuit in the present invention, and FIG. A flowchart showing the flow of the operation in Figure 4, Figure 8 is a connection diagram of the main parts in Figure 3, Figure 9 is a timing chart to explain the operation in Figure 8, and Figure 10 has added a measurement end signal. FIG. 11 is an explanatory diagram of the configuration when the devices of FIG. 10 are connected in parallel;
Fig. 12 is a connection diagram of the main parts of Fig. 3, Fig. 13 is a timing chart to explain the operation of Fig. 12, and Fig. 14 shows the flow of operation of the device to which the circuit of Fig. 10 is added. It is a flowchart. DESCRIPTION OF SYMBOLS 1... Sample clock generation circuit, 2... A/D converter, 3... Data memory, 4... Data memory control circuit, 5... Trigger control circuit, 6... Arithmetic control unit (CPU), 7... bus. Figure 5 CL Figure 3 Figure 9 1-t

Claims (1)

[Scope of Claims] A sample clock control circuit that selectively outputs an internal reference clock, an external clock applied from the outside, and an external reference clock to the outside as an external reference clock, and also outputs them to various internal parts via a frequency divider. , an A/D converter that converts an analog input signal into a digital signal according to a clock applied from a frequency divider of this sample clock control circuit, a data memory that stores output data of this A/D converter, and an external device. a data memory control circuit that sends and receives a plurality of measurement control signals between the two and controls the data storage operation of the data memory according to the plurality of measurement control signals; and a data memory control circuit that sends and receives a plurality of measurement control signals between the two; a trigger control circuit that selectively outputs a synchronous trigger signal to the outside and outputs the signal to the data memory control circuit via a timing control circuit that synchronizes with the clock applied from the frequency divider of the sample clock control circuit; An A/D conversion device comprising: an arithmetic control unit that performs overall control of the A/D conversion device.