JP2003196580A - Optional waveform generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To output a waveform from the forefront, while synchronizing with a trigger from the outside. <P>SOLUTION: This waveform generator for generating an assigned waveform by reading out in order respective data stored in respective assigned addresses while synchronizing with clocks has an address information outputting means 12 for outputting a start address AS and a finishing address AE in a waveform memory 11, an address counter 17 synchronized to the clocks to impress the addresses to the waveform memory in order starting from the start address, an address counter stopping means 18 for detecting that the addresses output from the address counter reach to the ending address, to stop the address counter, and a timing regulation means 16 for transmitting an output indication to the address information outputting means in response to the trigger, and for driving the address counter. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention stores waveform data in each address of a waveform memory and sequentially reads out each data stored in each address to generate a waveform. Waveform generator.

[0002]

2. Description of the Related Art To generate a waveform specified by a user,
Rather than using an analog signal generator, the method in which the waveform specified by the user is stored in each address of the waveform memory and the specified waveform is obtained by sequentially reading each data is specified by the user. Waveforms can be realized more accurately and easily.

An arbitrary waveform generator adopting such a method is constructed, for example, as shown in FIG.

At each address in the waveform memory 1, as shown in FIG. 8, each data of the target waveform 2 is stored. The address storage unit 3 stores the start address A _S and the end address A _E of the waveform 2 in the waveform memory 1. When the arbitrary waveform generator is activated, the start address A _S from the address storage unit 3 is transferred to the address counter 4
And the end address A _E is applied to the end address detection unit 5.

The address counter 4 increments or decrements the start address A _S by a predetermined number each time a clock c is input from the outside, and each address A incremented or decremented by a predetermined number is stored in the waveform memory. It is applied to 1 in order.
Further, the address A output from the address counter 4 is also input to the end address detecting unit 5.

The waveform memory 1 uses the data stored in the address A sequentially input in synchronization with the clock c to the next D / A.
It is sent to the conversion unit 6. The D / A converter 6 converts each input data into analog and outputs it as an analog waveform 2.

When the address A output from the address counter 4 matches the end address A _E , a load command is applied from the end address detection unit 5 to the address counter 4. As a result, the start address A _S stored in the address storage unit 2 is newly loaded into the address counter 4. Therefore, the same waveform 2 from the D / A converter 6
Is repeatedly output.

Although the arbitrary waveform generator shown in FIG. 7 is configured to output only one type of waveform 2, as shown in FIGS. 9 and 10, an arbitrary waveform generator capable of outputting a plurality of types of waveforms is also available. It has been proposed (Japanese Patent No. 2544210).

A plurality of types of waveforms are stored in the waveform memory 1a of the arbitrary waveform generator as shown in FIG. 10 (b). Further, as shown in FIG. 10A, a sequence storage unit 7 for storing the start address A _S and the end address A _{E of} each waveform stored in the waveform memory 1a, and a waveform switching unit 8 are provided. .

In the arbitrary waveform generator having such a configuration, when the operator (user) specifies the waveform to be output to the sequence storage unit 7, the sequence storage unit 7
The start address A _S and end address A _{E of the} corresponding waveform are sent from the address storage unit 2 to the address storage unit 2. As a result, the address A of the designated waveform is output from the address counter 4 to the waveform memory 1a, and the designated waveform 2 from the D / A converter 6 is output.
Is output.

When a trigger b for switching the output to another waveform is applied to the waveform switching section 8 during the output of one waveform 2, a waveform switching command is sent to the address storage section 2. As a result, the address memory 2 stores the start address A _{S of} the switching destination (next) waveform stored in the sequence memory 7.
And end address A _E.

When the waveform 2 currently being output ends after the trigger b is applied to the waveform switching unit 8, a load command is sent from the end address detecting unit 5 to the address counter 4. The output of the new waveform 2 switched at b is started.

[0013]

However, the arbitrary waveform generator shown in FIG. 9 still has the following problems to be solved.

That is, let us consider a case where the arbitrary waveform generator is used by incorporating it into a test apparatus for testing the operation of a terminal that performs various communications with a base station such as a mobile phone. In this case, a trigger (frame trigger signal) is received from the terminal under test at a substantially constant cycle, and the test apparatus is generated from the waveform generated by the arbitrary waveform generator in synchronization with this trigger (frame trigger signal). It is necessary to send the test signal to the corresponding terminal under test.

The output timing of the trigger (frame trigger signal) generated by the terminal under test having a substantially constant cycle is changed before and after the setting value (parameter) of transmission / reception of the terminal under test is changed for the test. In, there may occur a large change.

As an arbitrary waveform generator incorporated in the test apparatus, when a trigger (frame trigger signal) b is input,
In synchronism with this trigger (frame trigger signal) b, it is necessary to start the output of the waveform 2 from the tip (start address A _s ), but as shown in FIGS. Since the input timing of the frame trigger signal b changes, the time T from the input of the trigger (frame trigger signal) b to the actual start of output of the next waveform 2 is T
There is a problem that _A is not constant.

Moreover, since the clock cycle of the terminal under test does not completely match the clock cycle of the test apparatus, the timing of the trigger (frame trigger signal) b output from the terminal under test is equal to the clock of the test apparatus. I'm not always doing it.

Further, there is a case where one waveform having a relatively long period such as a pseudo-random code sequence waveform is divided into fixed-length blocks divided by a trigger (frame trigger signal) b and outputted. is there. For example, this corresponds to a case where a pseudo random code string waveform is divided into bursts of burst signals and transmitted.

In such a case, the start address and the end address of the waveform (partial waveform) output in each block of one waveform having a relatively long cycle are written in the sequence storage unit 7.

However, it is rare that the value obtained by dividing the length (the number of addresses) of one waveform having a relatively long cycle by the fixed length (the number of addresses) of the block becomes an integer.
It is necessary to continuously write a plurality of one waveform having a relatively long period in the waveform memory 1a so that the end address of the block coincides with the end of one waveform having a relatively long period.

As a result, the storage capacity required by the waveform memory 1a is at least the least common multiple of the fixed length of the block and the length (number of addresses) of one waveform,
Manufacturing costs rise. Further, the required storage capacity of the sequence storage unit 7 also increases.

The present invention has been made in view of such circumstances, and after a certain adjustment time has elapsed for a trigger input from the outside, the waveform starts to be output from the beginning, and the switching of the output waveform is sent as a trigger. It is an object of the present invention to provide an arbitrary waveform generator that can be accurately synchronized with the setting change of the original device and can be used for a wider range of devices.

Further, in addition to the above object, it is another object of the present invention to provide an arbitrary waveform generator capable of reducing the required storage capacity of the waveform memory.

[0024]

According to the present invention, each data for forming one or more kinds of waveforms is stored in each address of a waveform memory and stored in each address corresponding to a designated waveform. It is applied to an arbitrary waveform generator that generates at least one designated waveform by sequentially reading each of the data in synchronization with a clock.

In order to solve the above problem, in the arbitrary waveform generator of the present invention, an address for outputting the start address of the specified waveform in the waveform memory and the end address specifying information for specifying the end address. The information output means, an address counter which is loaded with a start address output from the address information output means, and applies an address which sequentially increases or decreases from the start address to the waveform memory in synchronization with a clock, and address information. Address counter stop means for stopping the address counter by detecting that the address output from the address counter reaches the end address of the waveform by using the end address specifying information output from the output means, and a trigger input from the outside. After adjusting the timing of, the trigger outputs address information. It is applied as the output instruction to start and end addresses specifying information to stage, and and a timing adjusting means for applying a load instruction start address to the address counter.

In the arbitrary waveform generator configured as described above, for example, a trigger (frame trigger signal) output from a device to which the waveform output from the arbitrary waveform generator is input is input to the arbitrary waveform generator. Then, the trigger is timing-time adjusted and applied to the address information output means as an output instruction of the start address and end address specifying information, and applied to the address counter as an instruction to load the start address.

Therefore, when a trigger is input to the address counter, for example, timing adjustment of less than one clock is performed, and then output of the next waveform is started from the next clock.

Therefore, even if this trigger is input during the output of one waveform, the output of the next waveform is started almost in synchronization with the input of this trigger without waiting until the output of this waveform is completed. Signal input / output can be synchronized with a device to which the waveform output from the arbitrary waveform generator is input.

According to another aspect of the invention, the address information output means in the arbitrary waveform generator of the above-mentioned invention outputs the start address stored by itself in response to the output instruction from the timing adjusting means. Storage means,
In response to the output instruction from the timing adjustment means, a start address to be output is calculated according to the output instruction next to this output instruction, and the start address stored in the next start address storage means is calculated at the calculated start address. And a start address calculating means for updating the address.

In the arbitrary waveform generator thus constructed, the start address stored in the next start address storage means is output every time a trigger (frame trigger signal) is input from the outside, and The start address to be output is automatically calculated according to the next output instruction.

In this way, each time a trigger is input from the outside, the start address of the waveform to be output next is calculated each time, so that one waveform having a relatively long cycle as described above is triggered to a fixed length block. Even in the case of dividing and outputting by (frame trigger signal), it is sufficient to prepare a waveform memory for storing only one waveform having a relatively long cycle.

Further, according to another invention, the end address specifying information in the arbitrary waveform generator of the above invention is constituted by the number of addresses indicating the length of the corresponding waveform. The address counter stopping means is composed of an address number counter that subtracts the number of input addresses in synchronization with the clock and stops the address counter when the number of addresses reaches zero.

Further, in another invention, the end address specifying information in the arbitrary waveform generator of the above-mentioned invention is composed of the end address of the corresponding waveform. Further, the address counter stop means is composed of an end address detection unit that stops the address counter when the address output from the address counter matches the input end address.

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing the schematic arrangement of an arbitrary waveform generator according to the first embodiment of the present invention. The arbitrary waveform generator of this embodiment is incorporated in a test apparatus that tests the operation of a terminal that performs various communications with a base station such as a mobile phone. Then, the arbitrary waveform generator receives a frame trigger signal output from the terminal under test at a substantially constant cycle, and generates a waveform in synchronization with the frame trigger signal. The test apparatus has a function of creating a test signal using the output waveform and transmitting it to the terminal under test.

In FIG. 1, each address in the waveform memory 11 stores each data of the target waveform. In the arbitrary waveform generator of the first embodiment, the waveform memory 11 stores only one waveform of a relatively long pseudo-random code string having a period of (2 ^N -1). (N = 9, 15, 23, etc.) And this (2 ^N
The waveform of the pseudo-random code sequence having the period of (1) is divided into blocks of fixed length N _B such as 120 by the number of addresses by a trigger (frame trigger signal) and output.

Within the address information output unit 12, a next start address storage unit 13, a next start address calculation unit 14, and a next address number storage unit 15 are provided. When the output instruction d from the timing adjustment unit 16 is input, the next start address storage unit 13 applies the start address A _S stored by itself to the address counter 17. Next address storage unit 1
When the output instruction d is input from the timing adjustment unit 16, the number 5 applies the address number N _A indicating the length of the waveform stored in itself to the address number counter 18.

When the output instruction d is input from the timing adjusting section 16, the next start address arithmetic unit 14 calculates the start address A _S to be output according to the output instruction d next to this output instruction d, and This calculated start address A _S
Then, the start address A _S stored in the next start address storage unit 13 is updated. Specifically, a value obtained by adding the fixed length N _B (= 120) of the block to the start address A _S output by the current output instruction d stored in the next start address storage unit 13 is used as the next start address A _{S. S.} Further, the next start address calculation unit 14 determines the number of addresses N _A stored in the next address number storage unit 15 with a fixed block length N _B.
To update.

The timing adjusting section 16 adjusts the timing of the trigger (frame trigger signal) e input from the external terminal under test to the clock timing, and then
The trigger e is applied to the address information output unit 12 as the output instruction d of the start address A _S and the number N _A of the waveform addresses as the end address specifying information, and is applied to the address counter 17 as the load instruction g of the start address A _S. To do.

When the load instruction g is applied from the timing adjusting section 16, the address counter 17 takes in the start address A _S output from the address information output section 12. Then, the address counter 17 increments or decrements the start address A _S by a predetermined number in synchronization with the clock generated by itself, and each address A incremented or decremented by a predetermined number is added to the waveform memory 11. Are applied in order.

The waveform memory 11 stores the data stored in the address A, which is sequentially input in synchronization with the clock, to the next D / A.
It is sent to the conversion unit 19. The D / A converter 19 converts each input data into analog and outputs it as an analog waveform j.

When the address number N _A is applied from the address information output unit 12, the address number counter 18 synchronizes the address number N _A with 1 by synchronizing with the clock generated by itself in synchronization with the clock of the address counter 17. The stop command h is applied to the address counter 17 when the subtracted address number N _A becomes 0.

As a result, the address counter 17 stops its operation and waits for the input of the load command g by the input of the next trigger (frame trigger signal) e.

In FIG. 2, the timing of the trigger (frame trigger signal) e input from the terminal under test to the arbitrary waveform generator due to, for example, changing the setting contents of the terminal under test is the same as in the previous block. It is a figure which shows the time chart which shows the state of each part when it generate | occur | produces during the output period of the waveform with respect to (frame trigger signal) e.

The trigger (frame trigger signal) e is time t
₁Entered at, time t₂~ T₃Next clock of i
Lock cycle T₁Then, the address counter 17 is
Start address output from the dress information output unit 12
A_S(= M) is loaded. At the same time, add at this point
Address number N output from the reply information output unit 12 _A
(= Y) is loaded into the address number counter 18.

Further, at the clock cycle T ₁ , the start address A _S is applied to the next start address calculation unit 14, and the next start address calculation unit 14 starts calculation of the next start address. When the calculation of the next start address is completed, the clock cycle of time t _3, the calculated next start address A _S (=
n) is output from the address information output unit 12. And
The output of the next waveform is started from the clock i (time t ₃ ) next to the clock cycle T ₁ .

As can be understood from the time chart of FIG. 2, even if the trigger (frame trigger signal) e is input during the output period of the waveform, 2 clocks from the input time of this trigger (frame trigger signal) e. When the cycle elapses, the output of the new waveform is surely started from the beginning.

In addition, in the arbitrary waveform generator of the first embodiment configured as described above, each time a trigger (frame trigger signal) e is input from the terminal under test, the waveform to be output next is output. The start address A _S is calculated by the next start address calculation unit 14. Therefore, even if the waveform memory 11 stores a waveform of a relatively long pseudo-random code string having a period of (2 ^N −1), even if only one waveform is stored, a fixed-length block is triggered (frame trigger signal) e. The waveform of each block is output normally when the data is separated by. Therefore, the storage capacity of the waveform memory 11 can be reduced.

Further, it is not necessary to use the sequence storage section 7 used in the conventional arbitrary waveform generator of FIG.

Further, by configuring the timing adjustment unit 16 with a delay counter, the time from the input of the trigger (frame trigger signal) e to the start of the output of a new waveform is set to an arbitrary clock cycle length ( Can be adjusted). By adopting the delay counter in this way, it is possible to absorb the time difference between the transmission timing of the trigger (frame trigger signal) e from the terminal under test and the reception timing of the trigger (frame trigger signal) e of the arbitrary waveform generator.

Furthermore, since a waveform is output in synchronization with the internal clock after a lapse of a fixed adjustment time from a clock (frame trigger signal) e input from the terminal under test at a substantially constant period, even if the waveform is Even if there is a difference between the clock cycle of the terminal under test that receives the signal and the internal clock cycle of the arbitrary waveform generator of the embodiment, before the transmission timing and the reception timing of the waveform due to this difference are significantly different, Will be resolved.

Therefore, it is not necessary to guide the clock of the terminal under test to this arbitrary waveform generator, so that the structure of the arbitrary waveform generator can be simplified.

(Second Embodiment) FIG. 3 is a block diagram showing the schematic arrangement of an arbitrary waveform generator according to the second embodiment of the present invention. The same parts as those of the arbitrary waveform generator according to the first embodiment shown in FIG. 1 are designated by the same reference numerals, and detailed description of the overlapping parts will be omitted.

In the arbitrary waveform generator of the second embodiment, in the address information output unit 12a, in addition to the next start address storage unit 13 and the next start address calculation unit 14 described above, the next end address storage unit 21 is provided. It is provided. In the next end address storage unit 21, the next start address calculation unit 1
The end address A _{E of the} waveform output according to the next output instruction d calculated in 4 is stored. Of course, when the next start address calculating unit 14 calculates a new end address A _E, end address A _E stored in the next end address storage unit 21
Is also updated to this new end address A _E.

Each time the output instruction d is input to the address information output unit 12a, the start address A _S and the next end address storage unit 2 stored in the next start address storage unit 13 are input.
The end address A _E stored in 1 is output.

The end address detection unit 20 monitors the address A output from the address counter 17, and the address A output from the address counter 17 matches the end address A _E output from the address information output unit 12a. Then, the stop command h is applied to the address counter 17.

As a result, the address counter 17 stops its operation and waits for the load command g to be input by the next trigger (sequence trigger signal) e input.

Also in the arbitrary waveform generator of the second embodiment having such a configuration, it is possible to obtain substantially the same operational effects as those of the arbitrary waveform generator of the first embodiment described above.

(Third Embodiment) FIG. 4 is a block diagram showing the schematic arrangement of an arbitrary waveform generator according to the third embodiment of the present invention. The same parts as those of the arbitrary waveform generator of the second embodiment shown in FIG. 3 are designated by the same reference numerals, and detailed description of the overlapping parts will be omitted.

In the arbitrary waveform generator of the third embodiment, with respect to the next start address storage unit 13 and the next end address storage unit 21 which compose the adrea information output unit 12a,
Dedicated output commands d ₁ and d ₂ are independently applied from the timing adjustment unit 16.

In the arbitrary waveform generator of the third embodiment configured as described above, for example, the cycle of the trigger (frame trigger signal) e input from the terminal under test and the input of each trigger (frame trigger signal) e. The length of the waveform output in response can be set independently of each other. For example, when the length of the waveform is longer than the trigger period, the waveform is forcibly cut off on the way. Further, when the length of the waveform is shorter than the trigger period, there is a period in which the waveform does not exist near the end of the trigger period.

(Fourth Embodiment) FIG. 5 is a block diagram showing the schematic arrangement of an arbitrary waveform generator according to the fourth embodiment of the present invention. The same parts as those of the arbitrary waveform generator of the third embodiment shown in FIG. 4 are designated by the same reference numerals, and detailed description of the overlapping parts will be omitted.

In the arbitrary waveform generator of the fourth embodiment, the start address A _{S of the} waveform output in synchronization with each trigger (frame trigger signal) e is set to the previous trigger (frame trigger signal) e. It is set equal to the end address A _{E of the} waveform output synchronously.

That is, when the output instructions d ₁ and d ₂ are input from the timing adjustment unit 16, the next start address storage unit 1
3, the start address A _S is output, and the next end address storage unit 21 outputs the end address A _E. Next, the start address A _S stored in the next start address storage unit 13 is updated with the end address A _E stored in the next end address storage unit 21. Then, the next end address calculation unit 22 is activated, and the end address A _E stored in the next end address storage unit 21 is used to end the waveform output when the next output instruction d ₂ is input. Address A _E
It is calculated and this calculated end address A _E updates the end address AE of the next end address storage unit 21.

The arbitrary waveform generator of the fourth embodiment having such a configuration can also achieve substantially the same effects as the arbitrary waveform generator of the third embodiment shown in FIG.

(Fifth Embodiment) FIG. 6 is a block diagram showing the schematic arrangement of an arbitrary waveform generator according to the fifth embodiment of the present invention. The same parts as those of the arbitrary waveform generator according to the first embodiment shown in FIG. 1 are designated by the same reference numerals, and detailed description of the overlapping parts will be omitted.

In the arbitrary waveform generator of the first embodiment, the waveform of the same length (the same number of addresses N _A ) is always synchronized with the trigger (frame trigger signal) e input from the terminal under test at a constant cycle. Is output.

Therefore, although the next start address storage unit 13 and the next start address calculation unit 14 are provided in the address information output unit 12b, the next address number storage unit 15 is provided.
Is not provided. Then, the address number counter 18
Is a fixed number N of addresses which is predetermined as an initial value according to the reset instruction d ₃ output from the timing adjustment unit 16 in synchronization with the trigger (frame trigger signal) e.
_A is set, and this fixed address number N _A is subtracted in synchronization with the internal clock. The number of subtracted addresses N _A is 0
Then, the stop command h is applied to the address counter 17. As a result, the address counter 17 stops its operation and waits for the input of the load command g by the input of the next trigger (frame trigger signal) e.

The arbitrary waveform generator of the fifth embodiment having such a configuration can also achieve substantially the same effects as the arbitrary waveform generator of the first embodiment shown in FIG.

The present invention is not limited to the above-mentioned first to fifth embodiments. In the arbitrary waveform generator of each embodiment, the address information output units 12, 12
The next start address calculation unit 14 or the next end address calculation unit 22 is incorporated in a and 12b, and the start address A _S or the end address A _E in the waveform memory 11 of the waveform to be output next from this arbitrary waveform generator is set. It was calculated each time.

However, each trigger (frame trigger signal)
When the output waveforms are independent according to the e input, the start address A _S and end address A _{E of} each waveform
A plurality of sets of (1) and (3) are stored and held in advance in the address information output unit 12, and each time a trigger (frame trigger signal) e is input, the set of the stored start address A _S and end address A _E is sequentially set. It is also possible to output to.

[0071]

As described above, in the arbitrary waveform generator of the present invention, the start address of the waveform output from the address information output section in response to the externally input trigger is loaded into the address counter. , The address counter is running. Therefore, after a certain adjustment time has elapsed from the trigger input time, the waveform starts to be output from the beginning, the switching of the output waveform can be accurately synchronized with the setting change of the trigger transmission source device, and the application of the arbitrary waveform generator can be expanded.

Further, every time a trigger is input, the start address in the waveform memory of the waveform to be generated next is calculated. Therefore, even when one waveform having a relatively long cycle is divided into blocks of a fixed length by a trigger (frame trigger signal) and output, a wavelength memory that stores only one waveform having a relatively long cycle should be prepared. I'm fine
The storage capacity of the required waveform memory can be saved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an arbitrary waveform generator according to a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the arbitrary waveform generator according to the first embodiment.

FIG. 3 is a block diagram showing a schematic configuration of an arbitrary waveform generator according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a schematic configuration of an arbitrary waveform generator according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a schematic configuration of an arbitrary waveform generator according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram showing a schematic configuration of an arbitrary waveform generator according to a fifth embodiment of the present invention.

FIG. 7 is a block diagram showing a schematic configuration of a conventional arbitrary waveform generator.

FIG. 8 is a diagram showing a relationship between each address of a waveform read from a waveform memory of the arbitrary waveform generator and a clock.

FIG. 9 is a block diagram showing a schematic configuration of still another conventional arbitrary waveform generator.

FIG. 10 is a diagram showing stored contents of a sequence storage section and a waveform memory in the arbitrary waveform generator.

FIG. 11 is a diagram for explaining a problem of the arbitrary waveform generator.

[Explanation of symbols]

11 ... Waveform memory 12, 12a, 12b ... Address information output unit 13 ... Next start address storage unit 14 ... Next start address calculation unit 15 ... Next address number storage unit 16 ... Timing adjustment unit 17 ... Address counter 18 ... Address number counter 19 ... D / A converter 20 ... End address detector 21 ... End address storage unit 22 ... Next end address calculator

Claims (4)

[Claims] 1. Each data for forming one or more kinds of waveforms is stored in each address of a waveform memory (11), and each data stored in each address corresponding to a designated waveform is clocked. In an arbitrary waveform generator for generating at least one type of waveform designated by sequentially reading in synchronization with, the start address and the end address of the designated waveform in the waveform memory are identified. Address information output means (12, 12a, 12) for outputting information and
b), an address counter (17) loaded with a start address output from the address information output means, and sequentially applying addresses from the start address to the waveform memory in synchronization with the clock; Address counter stop means (18, 20) for stopping the address counter by detecting that the address output from the address counter has reached the end address of the waveform by using the end address specifying information output from the information output means. ), The timing of the trigger input from the outside is adjusted, and then this trigger is applied to the address information output means as an output instruction of the start address and end address specifying information, and the address counter is instructed to load the start address. Timing adjusting means (16) for applying as Arbitrary waveform generator was. 2. The address information output means, in response to an output instruction from the timing adjustment means, a next start address storage means (13) for outputting a start address stored therein, and the timing adjustment means. In accordance with the output instruction from, the start address to be output according to the output instruction next to this output instruction is calculated, and the start address stored in the next start address storage means is calculated by the calculated start address. The arbitrary waveform generator according to claim 1, further comprising a start address calculating means (14) for updating. 3. The end address specifying information is the number of addresses indicating the length of the corresponding waveform, and the address counter stopping means subtracts the number of input addresses in synchronization with the clock, 3. The arbitrary waveform generator according to claim 1, wherein the arbitrary waveform generator is an address number counter (18) that stops the address counter when the number of addresses reaches zero. 4. The end address specifying information is an end address of a corresponding waveform, and the address counter stop means stops the address counter when the address output from the address counter matches the input end address. The arbitrary waveform generator according to claim 1 or 2, which is an end address detection unit (20) to be activated.