JP2008005336A - Receiver, reception processing method, and base band processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption by reproducing a high speed clock in a status prior to the shift of a normal mode to a sleep mode in recovering the normal mode from the sleep mode. <P>SOLUTION: The receiver includes a mode control part 110 for controlling the switching of a normal mode to perform the reception processing of a radio signal to be intermittently transmitted and a sleep mode to stop the reception processing; a high speed clock generator 10 for generating a high speed clock CLK1 to be used for the reception processing in the normal mode, and for stopping the high speed clock CLK1 in the sleep mode; a setting value storing part 120 for storing a frequency setting value for setting the frequency of the high speed clock CLK1 prior to the shift of the normal mode to the sleep mode; and a setting value supply part 130 for supplying the frequency setting value stored in the setting value storage part 120 to the high speed clock generator 10 when the normal mode is recovered from the sleep mode. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a reception apparatus that performs intermittent reception, a reception processing method in the reception apparatus, and a baseband processor.

  In mobile communication terminals such as mobile phones, intermittent reception is performed in order to suppress battery consumption during standby. In intermittent reception, a sleep mode in which most of the wireless communication circuit is powered off and a normal mode in which a circuit necessary for reception is turned on to receive a radio signal from the base station are alternately executed. In the normal mode, communication with the base station is performed, and the presence / absence of an incoming call and the state of radio waves are checked. As a result of the check, if it is determined that there is no incoming call or the like, most of the power of the wireless communication circuit is turned off again to shift to the sleep mode.

  In a state where the base station and the mobile communication terminal are not synchronized, the mobile communication terminal cannot normally receive a signal from the base station. Therefore, after returning from the sleep mode to the normal mode, it is necessary to capture the timing of the base station and synchronize the internal timing of the mobile communication terminal with the base station.

  In order to realize intermittent reception, two clock signals of a low-speed clock and a high-speed clock are used in the mobile communication terminal. The low-speed clock is a clock signal having a low frequency and low accuracy, and is used in both the normal mode and the sleep mode. On the other hand, the high-speed clock has a high frequency and high accuracy, and is used only in the normal mode.

  In order to synchronize the internal timing of the mobile communication terminal with the base station, a mobile communication terminal that performs intermittent reception is provided with a reference counter that counts a high-speed clock. The count value of the reference counter is used to measure, for example, one frame period or one time slot period defined by a time division multiple access (TDMA) system. For this reason, when returning from the sleep mode to the normal mode, it is important to quickly correct the count value of the reference counter. This is because when the correction of the count value of the reference counter requires a long time, the circuit for correcting the count value is operated for a long time, which increases power consumption.

As a technique for correcting the count value of the reference counter when returning from the sleep mode to the normal mode, the relative error of each frequency of the high-speed clock and the low-speed clock is measured. A method of correcting the count value of the reference counter based on the sleep state time has been proposed (see Patent Document 1). In Patent Document 1, a clock signal having a fixed frequency is used as a high-speed clock.
JP 2002-353869 A

  However, in recent mobile communication terminals, a high-speed clock is generally generated by a voltage-controlled oscillator such as a voltage-controlled temperature-compensated crystal oscillator (VCTCXO). In the case of using an oscillator with a variable oscillation frequency, in Patent Document 1, when returning from the sleep mode to the normal mode, the frequency of the high-speed clock at the time of error measurement may not match the frequency of the high-speed clock at the time of recovery.

  Therefore, even if the count value is corrected with high accuracy at the time of return, the reference counter may not operate in the period for measuring the relative error due to the error of the high-speed clock. As a result, since it is necessary to correct the count value of the reference counter again, there is a problem that synchronization establishment time and power consumption increase.

  In view of the above problems, the present invention, when returning from the sleep mode to the normal mode, reproduces a high-speed clock in a state before shifting to the sleep mode, thereby reducing power consumption, a reception processing method, and An object is to provide a baseband processor.

  In order to achieve the above object, a first feature of the present invention is a mode control for controlling switching between a first mode for receiving radio signals transmitted intermittently and a second mode for stopping reception processing. A high-speed clock generator for generating a high-speed clock used for reception processing in the first mode and stopping the high-speed clock in the second mode, and the frequency of the high-speed clock before the transition from the first mode to the second mode. A setting value holding unit that holds a frequency setting value to be set; and a setting value supply unit that supplies the frequency setting value held in the setting value holding unit to the high-speed clock generator when returning from the second mode to the first mode. The gist of the present invention is a receiving device.

  According to this feature, since the frequency setting value for setting the frequency of the high-speed clock is held before shifting to the second mode, the frequency of the high-speed clock can be accurately reproduced when returning to the first mode. Become. For this reason, the time required for synchronization recovery and incoming call confirmation is shortened, and the operation time of related circuits can be reduced. Therefore, it is possible to provide a receiving device that realizes power saving and can increase the battery driving time.

  A second feature of the present invention is a receiving device according to the first feature, wherein a reference counter for counting a high-speed clock, and a low-speed clock having a frequency lower than that of the high-speed clock in the first mode and the second mode are provided. A low-speed clock generator to be generated, an error measuring unit that measures a relative error of each frequency of the high-speed clock and the low-speed clock before the transition from the first mode to the second mode, and the relative error is associated with the frequency setting value And when the error mode is returned from the second mode to the first mode, a relative error corresponding to the frequency setting value held in the setting value holding unit is acquired from the error holding unit, and the acquired relative error and the first The gist is to further include a count value correction unit that corrects the count value of the reference counter based on the duration of the two modes.

  According to this feature, when the set value holding unit holds the frequency set value, the relative error of each frequency of the high-speed clock and the low-speed clock is measured, and the error is held when returning from the second mode to the first mode. Since the count value of the reference counter is corrected based on the relative error held in the section and the duration of the second mode, the count value can be corrected with high accuracy when returning.

  A third feature of the present invention is a receiving device according to the first or second feature, wherein temperature information indicating the ambient temperature of the terminal, time information indicating the current time, coordinate information indicating the coordinates of the terminal, Or a measuring device that obtains a measurement value by measuring at least one of speed information indicating the moving speed of the terminal itself, and the setting value holding unit holds the frequency setting value and the measurement value in association with each other. The supply unit rapidly outputs the frequency setting value held in the setting value holding unit according to the difference between the measurement value held in the setting value holding unit and the measurement value at the time when the mode is returned from the second mode to the first mode. The gist is to determine whether to supply to the clock generator or to correct the frequency setting value.

  According to this feature, when the change in the surrounding environment of the receiving apparatus is large between the transition from the first mode to the second mode and the return from the second mode to the first mode, the stored frequency setting value Therefore, in such a case, correct the setting value based on the stored frequency setting value and set the corrected setting value to the high-speed clock generator, or save the frequency. It is possible to control so that the set value is not supplied to the high-speed clock generator.

  A fourth feature of the present invention is a reception processing method in a receiving apparatus that switches between a first mode in which radio signals transmitted intermittently are received and a second mode in which reception processing is stopped. Generating a high-speed clock used for reception processing in the first mode, holding a frequency setting value for setting the frequency of the high-speed clock before shifting from the first mode to the second mode, and from the second mode to the first When returning to the mode, the gist of the present invention is a reception processing method including a step of generating a high-speed clock using the held frequency setting value and receiving a radio signal in the first mode.

  According to this feature, since it is possible to realize power saving of the receiving apparatus, it is possible to increase the battery driving time.

  A fifth feature of the present invention is a baseband processor used together with a high-speed clock generator for generating a high-speed clock used for reception processing in a first mode for receiving and processing radio signals transmitted intermittently, A mode control unit that controls switching between the first mode and the second mode in which the reception process is stopped, and a frequency setting value that sets the frequency of the high-speed clock are held before the transition from the first mode to the second mode. A baseband processor comprising a setting value holding unit and a setting value supply unit that supplies the frequency setting value held in the setting value holding unit to the high-speed clock generator when returning from the second mode to the first mode. Is the gist.

  According to this feature, it is possible to provide a baseband processor that can realize power saving and can increase battery driving time.

  According to the present invention, when returning from the sleep mode to the normal mode, the receiver, the reception processing method, and the baseband processor capable of reducing the power consumption by reproducing the high-speed clock in the state before the transition to the sleep mode. Can be provided.

  Next, an embodiment of the present invention will be described with reference to the drawings. In the description of the drawings in the following embodiments, the same or similar parts are denoted by the same or similar reference numerals.

(Configuration of mobile communication terminal)
As shown in FIG. 1, a mobile communication terminal according to an embodiment of the present invention has an antenna 11 that transmits and receives radio signals to and from a base station, a radio communication circuit 500 that performs amplification and frequency conversion of radio signals, and a high frequency. And a high-speed clock generator 10 that generates a high-speed clock CLK1 that is a high-precision clock signal, a low-speed clock generator 200 that generates a low-speed clock CLK2 that is a low-frequency and low-precision clock signal, and a base station A baseband processor 100 for controlling communication and a bus 600 for transmitting various data are provided. The wireless communication circuit 500, the high-speed clock generator 10, and the baseband processor 100 are connected to each other via a bus 600.

  The wireless communication circuit 500 includes a radio frequency (RF) circuit, an intermediate frequency (IF) processing circuit, and the like that are not shown. The wireless communication circuit 500 performs intermittent reception during standby. Specifically, the wireless communication circuit 500 uses the high-speed clock CLK1 as an operation clock, and the power consumption of the wireless communication circuit 500 is reduced by periodically stopping the high-speed clock CLK1. It should be noted that a mode in which most of the power of the wireless communication circuit 500 is turned off is “sleep mode”, and a mode in which a circuit necessary for reception is turned on to receive a radio signal from the base station is “normal mode”. Each is called.

  The high-speed clock generator 10 includes a digital / analog converter (DAC) 400 that converts digital data supplied from the baseband processor 100 via the bus 600 into an analog signal, and a frequency corresponding to the analog signal output from the DAC 400. And an oscillator 300 that oscillates. As the oscillator 300, a VCTCXO, a voltage controlled crystal oscillator (VCXO), or a voltage controlled oscillator (VCO) can be used.

  The low-speed clock generator 200 generates the low-speed clock CLK2 in the normal mode and the sleep mode.

(Baseband processor configuration)
Next, the baseband processor 100 will be described. The baseband processor 100 includes a mode control unit 110 that controls switching between the normal mode and the sleep mode, and a setting value that holds a frequency setting value that sets the frequency of the high-speed clock CLK1 before shifting from the normal mode to the sleep mode. A holding unit 120 and a setting value supply unit 130 that supplies the frequency setting value held in the setting value holding unit 120 to the high-speed clock generator 10 when returning from the sleep mode to the normal mode are provided. Here, the “frequency setting value” means digital data input to the DAC 400, but may be a value (voltage value) of an analog signal output from the DAC 400.

  In order to synchronize with the base station, the setting value supply unit 130 performs correlation calculation on the reception signal transmitted via the antenna 1, the wireless communication circuit 500, and the bus 600, thereby Perform timing correction control. As a result, the set value supply unit 130 outputs a frequency set value that establishes and maintains synchronization with the base station in the normal mode. Although a dedicated bus exists in the baseband processor 100, it is assumed to be included in the bus 600 for convenience of explanation.

  Therefore, by holding the frequency setting value before shifting to the sleep mode and resetting the held frequency setting value when returning to the normal mode, the frequency of the high-speed clock CLK1 can be accurately reproduced.

  The baseband processor 100 also includes a reference counter 140 that counts the high-speed clock CLK1, and an error measurement unit 150 that measures a relative error (hereinafter simply referred to as “relative error”) between the high-speed clock CLK1 and the low-speed clock CLK2. And the error holding unit 180 that holds the relative error, and the reference counter 140 counts based on the relative error held in the error holding unit 180 and the duration of the sleep mode when returning from the sleep mode to the normal mode. It further includes a count value correction unit 190 that corrects the value.

  Specifically, the error measuring unit 150 executes the count of the low-speed clock CLK2 and the count of the high-speed clock CLK1 in parallel, and measures the relative error by comparing both count values.

  The count value correction unit 190 calculates a new count value of the reference counter 140 when returning from the sleep mode to the normal mode. This new count value is the count value of the reference counter 140 when it is assumed that the reference counter 140 continues the counting operation during the sleep period.

  On the other hand, the frequency setting value may be changed in the normal mode. In this case, it is considered that the relative error corresponding to the changed frequency setting value is not measured from the time difference between the relative error measurement timing and the transition timing to the sleep state. For this reason, when measuring the relative error, it is preferable to store the frequency setting value and the relative error in association with each other.

  The baseband processor 100 inputs / outputs baseband signals to / from the wireless communication circuit 500 via the bus 600 and performs signal processing on the baseband signals, and the wireless communication circuit 500 and the baseband processor according to various communication protocols. A protocol control unit 170 that controls the entire baseband processor 100 is further provided.

(Operation of the reference counter)
Next, the operation of the reference counter 140 will be described with reference to FIGS. The reference counter 140 counts the high-speed clock CLK1 and determines the timing inside the mobile communication terminal (timing synchronized with the base station). Here, an example of measuring one frame period in the TDMA system using the reference counter 140 will be described.

  As shown in FIG. 2, the reference counter 140 is configured to be automatically reset when, for example, the high-speed clock CLK1 is counted by a certain count number C0. Therefore, each period of T1, T2, and T3 in FIG. 2 can be made to correspond to one frame period.

  In the sleep mode, as shown at times t1 to t2 in FIG. 3, the count operation is stopped by stopping the high-speed clock CLK1. When returning from the sleep mode to the normal mode at time t <b> 2 in FIG. 3, the count value correction unit 190 sets a new count value C <b> 1 in the reference counter 140.

  After time t2 in FIG. 3, the generation of the high-speed clock CLK1 is resumed, and the reference counter 140 resumes the counting operation. However, when the frequency of the high-speed clock CLK1 is inappropriate, as shown in “B” in FIG. In addition, it is different from the increasing tendency of the count value before time t2. Note that “B” in FIG. 3 shows an increasing tendency of the count value when the frequency of the high-speed clock CLK1 is lower than the original frequency.

  On the other hand, the setting value holding unit 120 holds the frequency setting value at time t1, and supplies the held frequency setting value to the high-speed clock generator 10 at time t2, thereby appropriately setting the frequency of the high-speed clock CLK1. Therefore, as shown by “A” in FIG. 3, it is possible to maintain the increasing tendency of the count value before time t2.

(Relative error measurement process flow)
Next, the relative error measurement processing flow will be described with reference to the flowchart shown in FIG.

  In step S11, the error measurement unit 150 measures a relative error.

  In step S12, the error holding unit 180 holds the relative error measured in step S11. Here, the error holding unit 180 preferably stores the relative error measured in step S11 in association with the frequency setting value output from the setting value supply unit 130. Further, the error holding unit 180 may store information related to the surrounding environment of the mobile communication terminal, as will be described later.

(Sleep mode transition flow)
Next, a transition flow from the normal mode to the sleep mode will be described with reference to the flowchart shown in FIG.

  In step S <b> 21, the set value holding unit 120 holds the frequency set value output from the set value supply unit 130. Furthermore, the set value holding unit 120 may store information related to the surrounding environment of the mobile communication terminal, as will be described later.

  In step S22, the mode control unit 110 switches the mode from the normal mode to the sleep mode. The protocol control unit 170 stops the high-speed clock CLK1 by stopping the supply of power to the DAC 400. As a result, the counting operation of the reference counter 140 is stopped.

(Normal mode return flow)
Next, a return flow from the sleep mode to the normal mode will be described with reference to the flowchart shown in FIG.

  In step S31, the set value supply unit 130 reads out the frequency set value held in step S21 in FIG. 5 from the set value holding unit 120 and supplies it to the DAC 400. As a result, the DAC 400 outputs a predetermined voltage to the oscillator 300, and the oscillation of the oscillator 300 starts.

  After waiting for the oscillation stabilization time of the oscillator 300 to elapse in step S32, in step S33, the count value correction unit 190 reads the relative error held in step S12 of FIG. In the error holding unit 180, when the frequency setting value and the relative error are stored in association with each other, the count value correction unit 190 reads the relative error corresponding to the frequency setting value supplied in step S31. The count value correction unit 190 corrects the count value of the reference counter 140 based on the read relative error and the duration of the sleep mode.

  As described above in detail, according to the embodiment of the present invention, the count value can be accurately corrected when returning from the sleep mode to the normal mode, and the high-speed clock CLK1 can be reproduced in the state before the transition to the sleep mode. Even after the correction of the count value, the count value of the reference counter 140 can be kept at an accurate value.

(Modification)
As shown in FIG. 7, the mobile communication terminal according to the modification of the embodiment of the present invention includes temperature information indicating the ambient temperature of the terminal, time information indicating the current time, coordinate information indicating the coordinates of the terminal, This is different from FIG. 1 in that it further includes a measuring device 700 that obtains a measured value by measuring at least one of speed information indicating the moving speed of the terminal. When measuring temperature information, for example, a temperature sensor can be used as the measuring device 700. When measuring time information, a time measuring device can be used as the measuring device 700. When measuring coordinate information, for example, a GPS receiver can be used as the measuring device 700. When measuring speed information, for example, a speed sensor can be used as the measuring device 700.

  The set value holding unit 1200 holds the frequency set value and the measured value in association with each other. The set value supply unit 1300 has a frequency setting held in the set value holding unit 1200 according to the difference between the measured value held in the set value holding unit 1200 and the measured value when the sleep mode returns to the normal mode. It is determined whether or not a value is supplied to the high-speed clock generator 10.

  A mobile communication terminal may be used in an environment where the temperature changes rapidly. Since the oscillation frequency of the oscillator 300 changes depending on the ambient temperature, if the frequency setting value held in the setting value holding unit 1200 is supplied to the high-speed clock generator 10 in an environment where the temperature changes rapidly, the high-speed clock generator 10 malfunctions. It can happen.

  Therefore, if the difference between the temperature information held in the set value holding unit 1200 and the temperature information at the time of returning from the sleep mode to the normal mode is equal to or greater than the threshold value, the held frequency setting value is considered to be low in reliability. .

  Moreover, the counter correction process may not be performed at the scheduled time depending on the processing status of the mobile communication terminal. Therefore, when returning from the sleep mode to the normal mode, the current time is measured, and the difference between the time information held in the set value holding unit 1200 and the time information at the time of return from the sleep mode to the normal mode is greater than or equal to the threshold value. In this case, the held frequency setting value is regarded as low reliability. The speed information and the coordinate information are similarly determined.

  Further, the error holding unit 1800 holds the relative error and the measurement value in association with each other. The count value correction unit 1900 uses the relative error held in the error holding unit 1800 in accordance with the difference between the measurement value held in the error holding unit 1800 and the measurement value when the sleep mode is returned to the normal mode. It is then determined whether or not the count value of the reference counter 140 is to be corrected. In this case, the count value correction unit 1900 holds the setting value holding unit 1200 in addition to determining whether or not to correct the count value of the reference counter 140 using the relative error held in the error holding unit 1800. You may make it correct | amend a frequency setting value suitably.

  According to the modification of the embodiment of the present invention, when the change in the surrounding environment of the mobile communication terminal is large at the time of shifting from the first mode to the second mode and at the time of returning from the second mode to the first mode. The stored frequency setting value and the relative error are regarded as having low reliability, and the stored frequency setting value and the relative error can be controlled not to be used. It is also possible to correct the count value of the reference counter 140 using the relative error corresponding to the corrected frequency setting value after correcting the frequency setting value.

(Other embodiments)
As mentioned above, although this invention was described by embodiment, it should not be understood that the description and drawing which form a part of this indication limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, the frequency setting value of an RF synthesizer (not shown) inside the wireless communication circuit 500 may be held as the frequency setting value held by the setting value holding unit 120. Further, the set value supply unit 130 supplies the RF synthesizer with the frequency set value of the RF synthesizer held in the set value holding unit 120 when returning from the sleep mode to the normal mode. Thus, by reproducing the frequency of the RF synthesizer, communication under high modulation can be quickly returned.

  In the above-described embodiment, the mobile communication terminal adopting the TDMA scheme has been described as an example. However, any mobile communication terminal that performs intermittent reception may be used, and other communication schemes such as a code division multiple access (CDMA) scheme may be used. May be adopted.

  Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters in the scope of claims reasonable from this disclosure.

It is a block diagram which shows the principal part structure of the mobile communication terminal which concerns on embodiment of this invention. It is a time chart for demonstrating operation | movement of the reference | standard counter which concerns on embodiment of this invention. It is a time chart for demonstrating operation | movement of the reference | standard counter which concerns on embodiment of this invention. It is a flowchart which shows the error measurement procedure of the mobile communication terminal which concerns on embodiment of this invention. It is a flowchart which shows the transfer procedure to the sleep mode of the mobile communication terminal which concerns on embodiment of this invention. It is a flowchart which shows the return procedure to the normal mode of the mobile communication terminal which concerns on embodiment of this invention. It is a block diagram which shows the principal part structure of the mobile communication terminal which concerns on the modification of embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Antenna 10 ... High-speed clock generator 11 ... Antenna 100 ... Baseband processor 110 ... Mode control part 120, 1200 ... Setting value holding part 130, 1300 ... Setting value supply part 140 ... Reference counter 150 ... Error measurement part 160 ... Base Band processing unit 170 ... Protocol control unit 180, 1800 ... Error holding unit 190, 1900 ... Count value correction unit 200 ... Low-speed clock generator 300 ... Oscillator 400 ... DAC
500 ... Wireless communication circuit 600 ... Bus 700 ... Measuring instrument

Claims (5)

A mode control unit that controls switching between a first mode in which a radio signal transmitted intermittently is received and a second mode in which the reception process is stopped;
A high-speed clock generator for generating a high-speed clock used for the reception processing in the first mode and stopping the high-speed clock in the second mode;
A set value holding unit for holding a frequency set value for setting the frequency of the high-speed clock before shifting from the first mode to the second mode;
And a setting value supply unit that supplies the frequency setting value held in the setting value holding unit to the high-speed clock generator when returning from the second mode to the first mode. A reference counter for counting the high-speed clock;
A low-speed clock generator for generating a low-speed clock having a frequency lower than that of the high-speed clock in the first and second modes;
An error measuring unit that measures a relative error of each frequency of the high-speed clock and the low-speed clock before the transition from the first mode to the second mode;
An error holding unit that holds the relative error in association with the frequency setting value;
When returning from the second mode to the first mode, the relative error corresponding to the frequency set value held in the set value holding unit is acquired from the error holding unit, and the acquired relative error and the second The receiving apparatus according to claim 1, further comprising: a count value correcting unit that corrects a count value of the reference counter based on a mode duration. A measuring device that obtains a measured value by measuring at least one of temperature information indicating the ambient temperature of the terminal, time information indicating the current time, coordinate information indicating the coordinates of the terminal, or speed information indicating the moving speed of the terminal. Further comprising
The set value holding unit holds the frequency set value and the measured value in association with each other,
The set value supply unit stores the set value in the set value holding unit according to a difference between the measured value held in the set value holding unit and the measured value at the time when the second mode returns to the first mode. The receiving apparatus according to claim 1, wherein it is determined whether or not the held frequency setting value is supplied to the high-speed clock generator, or the frequency setting value is corrected. A reception processing method in a reception device that switches between a first mode for receiving and processing a radio signal transmitted intermittently and a second mode for stopping the reception processing,
Generating a high-speed clock used for the reception process in the first mode;
Holding a frequency setting value for setting a frequency of the high-speed clock before shifting from the first mode to the second mode;
When returning from the second mode to the first mode, the method includes generating the high-speed clock using the held frequency setting value and receiving a radio signal in the first mode. The reception processing method. A baseband processor used together with a high-speed clock generator for generating a high-speed clock used for the reception processing in a first mode for receiving and processing a radio signal transmitted intermittently;
A mode control unit for controlling switching between the first mode and the second mode for stopping the reception process;
A set value holding unit for holding a frequency set value for setting the frequency of the high-speed clock before shifting from the first mode to the second mode;
A baseband processor, comprising: a setting value supply unit that supplies the frequency setting value held in the setting value holding unit to the high-speed clock generator when returning from the second mode to the first mode. .

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