JP2013109559A - Information processor and data return method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor capable of reducing consumption power at sleep time by suppressing an impact of a manufacturing process.SOLUTION: An information processor 100 includes saved data storage means for holding data during a second operation mode that is generated by working storage means during a first operation mode for executing a program, and the information processor includes: clock generation means 19 and 20 for generating an operation clock of the second operation mode and a greater operation clock of the first operation mode than the operation clock of the second operation mode; first data return means 41 for, at the time of return from the second mode, returning information processor status data showing a status of the information processor from the saved data storage means to the working storage means before an increase to the operation clock of the first operation mode by the clock generation mode; and second data return means 46 for returning the data generated during the first operation mode from the saved data storage means to the working storage means after the increase to the operation clock of the first operation mode by the clock generation means.

Description

  The present invention relates to an information processing apparatus having an execution mode for executing a program and a power saving mode for reducing power consumption compared to the execution mode.

  Many microcomputers have a sleep mode in which the operation of some circuits is stopped under a certain condition and the operation clock is reduced. In the sleep mode, power consumption is reduced by cutting off operation clocks and power supply to other circuits while leaving a circuit necessary for wake-up processing or the like.

  However, as the semiconductor manufacturing process becomes finer, a leakage current that flows through a circuit that is not supplied with power has hindered reduction in power consumption.

  FIG. 1 is an example of a diagram for explaining leakage current of a microcomputer. In the normal operation mode before entering the sleep mode, an operation clock and power are supplied to the register, CPU, RAM, CAN controller, A / D converter, and timer (shaded circuit). When the microcomputer enters the sleep mode, supply of the operation clock and power to other circuits is stopped, leaving the register, CPU, and RAM. In this case, a current should flow only between the register, the CPU, and the RAM, but the current may leak to a circuit whose operation is stopped depending on the manufacturing process.

  Such a current leak occurs because the register and RAM are connected to a circuit other than the CPU, and the wires connecting the other circuits in the microcomputer are in close contact with the register and RAM. When supplied, the current is considered to be leaked to the electric wire.

  Therefore, a technique for reducing the leakage current during sleep has been considered (see, for example, Patent Document 1). In Patent Document 1, the first and second blocks are manufactured by different manufacturing processes, and at the time of sleep, the second block is a first block created by a manufacturing process capable of reducing the amount of leakage current compared to the second block. A microcomputer for transferring data that needs to be retained is disclosed. Since the first block hardly generates a leak current, the leak current during sleep can be reduced.

JP 2007-226632 A

  However, as disclosed in Patent Document 1, manufacturing a microcomputer circuit by a different manufacturing process means that one microcomputer is manufactured by a different manufacturing process. For this reason, there exists a problem of reducing the cost reduction effect by refinement | miniaturization of a manufacturing process.

  In view of the above problems, an object of the present invention is to provide an information processing apparatus capable of reducing power consumption during sleep by suppressing the influence of a manufacturing process.

  The present invention is an information processing apparatus having save data storage means for holding data created in the work storage means during the first operation mode during the second operation mode, A clock generating means for generating an operating clock and an operating clock for the first operating mode that is larger than the operating clock for the second operating mode; and when returning from the second operating mode, the clock generating means A first data return means for returning information processing apparatus status data indicating the state of the information processing apparatus from the saved data storage means to the working storage means before raising the operation clock to the operation mode; After the means is raised to the operation clock of the first operation mode, the data created during the first operation mode is stored from the saved data storage means to the working memory. And having a second data restoring means for restoring the stage, the.

  It is possible to provide an information processing apparatus that can reduce the power consumption during sleep by suppressing the influence of the manufacturing process.

It is an example of the figure explaining the leakage current of a microcomputer. It is an example of the figure which illustrates the characteristic part of a microcomputer roughly. It is an example of the figure which shows the power supply state of backup RAM. It is an example of the functional block diagram of a microcomputer. It is an example of the flowchart figure explaining the transition of the operation mode of a microcomputer. It is an example of the figure which illustrates a wake-up procedure typically. It is an example of the flowchart figure explaining a wake-up procedure. FIG. 10 is an example of a flowchart for explaining an execution procedure of “wakeup determination” and “data restoration processing A”. FIG. 10 is an example of a flowchart for explaining an execution procedure of “wakeup determination” and “data recovery process B”.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  FIG. 2 is an example of a diagram schematically illustrating a characteristic part of the microcomputer according to the present embodiment. The figure shows the microcomputer 100 in the sleep state, and power and a clock are supplied to the shaded block (CPU in the figure).

  The microcomputer 100 of this embodiment newly has a backup RAM 17 that holds the data in the register 11 and the RAM 13 during sleep. The backup RAM 17 is connected only to the CPU 12. In other words, the CPU 12 is connected on a one-to-one basis, and only the CPU 12 can access the backup RAM 17.

  Since the data in the register 11 and the RAM 13 is saved in the backup RAM 17 before the sleep, it is necessary to supply the power source and the operation clock to the register 11, the RAM 13 and the backup RAM 17 (when the backup RAM is a non-volatile memory) during the sleep. Absent. For this reason, the power consumption during sleep can be greatly reduced as compared with the prior art.

  Further, the backup RAM 17 is created by the same manufacturing process (for example, 90 nm or less) as other circuits. Since the entire microcomputer 100 can be manufactured by the same manufacturing process, the cost can be easily reduced. Further, since the backup RAM 17 is not connected to a circuit other than the CPU, the leakage current during sleep can be greatly reduced even if the manufacturing process is fine. That is, when the backup RAM 17 is a volatile memory, power and a clock are supplied to the CPU 12 and the backup RAM 17 during sleep. However, since the backup RAM 17 is connected only to the CPU 12, current hardly leaks from the backup RAM 17 to other circuits. Therefore, even when the backup RAM 17 is a volatile memory, power consumption during sleep can be reduced.

[Configuration example]
The microcomputer 100 in FIG. 2 will be described. The microcomputer 100 includes a register 11, a CPU 12, a RAM 13, a CAN controller 14, an A / D converter 15, a timer 16, and a backup RAM 17. Further, the oscillator 18, the main clock generation circuit 19, the PLL circuit 20, and the power supply circuit 21 related to the sleep mode are illustrated. In addition, ROM, cache memory, DMAC, interrupt controller, IP (which differs depending on the microcomputer, for example, DSP, image processing circuit), etc. are omitted.

  The CPU 12 is connected to the register 11, the RAM 13, the CAN controller 14, the A / D converter 15, and the timer 16 via a main bus and a peripheral bus. The register 11 and the RAM 13 are also connected to these circuits because they are accessed from the CAN controller 14, the A / D converter 15, and the timer 16. On the other hand, the backup RAM 17 is connected only to the CPU 12.

  The CPU 12 executes a program stored in a ROM (not shown) and controls other circuits so that a target calculation result can be obtained. The register 11 includes a general-purpose register in which values used by the CPU 12 are stored, a program counter that stores the address of an instruction to be executed next, a microcomputer status register that indicates the state of the microcomputer 100, an interrupt control register, and various other types. Contains registers. The RAM 13 is a working memory that stores data during execution of the program, data for lookup, and the like. Some microcomputers 100 may be executed after copying the program to the RAM 13. The CAN controller 14 is a communication device for communicating with another microcomputer (for example, ECU: Electronic Control Unit) connected via the CAN bus. The CAN controller 14 generates a CAN frame in response to an instruction from the CPU 12 and transmits it on the CAN bus. Also, the CAN frame flowing on the CAN bus is monitored, received according to the CAN ID, and notified to the CPU 12. The A / D converter 15 converts an analog value detected by a sensor or the like into digital data, stores it in the RAM 13 and notifies the CPU 12 of it. The timer 16 notifies the CPU 12 of the elapse of the time set by the CPU 12. The timer 16 includes, for example, WDT. These peripheral circuits use the register 11 and the RAM 13 for communication with the CPU 12.

  The backup RAM 17 is described as a nonvolatile memory, but may be a volatile memory. If it is a non-volatile memory, for example, a flash memory, a magnetoresistive RAM (MRAM), a ferroelectric memory (FeRAM), a PCM (phase change memory), a ReRAM (resistance change type memory), etc. can be adopted as the storage element. If it is a volatile memory, SRAM, SDRAM, DRAM, etc. can be adopted as a storage element. Although the backup RAM 17 is paired with the CPU 12, in the case of a multi-core processor having a plurality of cores, one backup RAM 17 may be arranged in the multi-core processor, or one backup RAM 17 may be arranged for each core. If a backup RAM 17 is provided for each core, sleep can be performed in units of cores, and if one backup RAM 17 is provided in a multi-core processor, cost reduction is facilitated.

  It is assumed that the microcomputer 100 of this embodiment is mainly mounted on the ECU of the vehicle. In-vehicle ECUs include an engine ECU, a brake ECU, a body ECU, a navigation ECU (AV / information processing ECU), a gateway ECU, and the like depending on the main functions. The microcomputer 100 of the present embodiment can be mounted without being affected by the difference in ECU functions.

  The power consumption of the microcomputer 100 is said to be approximately proportional to the operation clock and proportional to the square of the voltage. Therefore, it is effective to reduce the operation clock and voltage during sleep, but only one of them may be reduced.

  The operation clock is generated by the oscillator 18, the main clock generation circuit 19, and the PLL circuit 20. The oscillator 18 is, for example, a crystal oscillator that generates a reference clock, the main clock generation circuit 19 is a circuit that lowers the reference clock to a specified frequency, and the PLL circuit 20 is a PLL clock that generates a main clock with a specified division ratio. It is a circuit to increase to. The CPU 12 controls the main clock and the PLL clock by setting a frequency instruction value in a predetermined register 11 at the time of start-up and wake-up. There is also a microcomputer 100 in which the main clock and the PLL clock are fixed. In this case, the CPU 12 may not control the frequency.

  The power supply circuit 21 steps down the battery voltage, generates several types of power supply voltages for several circuit groups, and supplies them to a circuit such as a CPU. The power supply circuit 21 can turn on / off the power at least for each group.

  When shifting to the sleep mode, the CPU 12 sets the instruction value of the operation clock for the sleep mode in the main clock generation circuit 19 and the PLL circuit 20 and requests the power supply circuit 21 to turn off the power supply other than the CPU. In this way, in the sleep mode, the clock frequency is reduced compared to the normal operation mode (an operation mode other than the sleep mode is referred to as a normal operation mode), and the circuit to which power is supplied can be limited to the CPU 12 alone. The operation clock in the sleep mode is about the reference clock. Note that the operation clocks in the sleep mode and the normal operation mode can be made variable by changing the indicated values of the main clock and the PLL clock.

  FIG. 3A shows an example of a power supply state when the backup RAM 17 is a nonvolatile memory. A hatched portion indicates a circuit to which power is supplied. The left side shows the power supply state in the normal operation mode. In FIG. 3A, power is supplied to all circuits. The right side shows the power supply state in the sleep mode, but no power is supplied except for the CPU 12. In this way, power consumption during sleep can be reduced by turning off the power supply of circuits other than the CPU.

  FIG. 3B shows a power supply state when the backup RAM 17 is a volatile memory. Similarly, the left side shows the power supply state in the normal operation mode. The right side shows the power supply state in the sleep mode, and power is supplied to the CPU 12 and the backup RAM 17. Even if power is supplied to the backup RAM 17, power consumption can be reduced so that power is supplied to the register 11 and the RAM 13. Even if the effect of reducing the power consumption is small, the backup RAM 17 connected only to the CPU 12 has a small leakage current during the sleep, so that the power consumption during the sleep can be reduced as compared with the conventional case.

[Transition to sleep mode]
FIG. 4 shows an example of a functional block diagram of the microcomputer 100. The microcomputer 100 performs a task A31 (hereinafter simply referred to as “task A”), a task B32 (hereinafter simply referred to as “task B”), and a state determination unit that determines the state of the microcomputer 100. 33, a power supply circuit control unit 34 that controls the power supply circuit 21, a sleep mode execution unit 35 that performs sleep processing, and a wakeup execution unit 41 that performs wakeup processing. Each functional block is realized by the CPU 12 executing a program in cooperation with hardware.

  A task management function such as an OS or basic software switches tasks assigned to the CPU 12 in accordance with the priority order of tasks. The task management function, for example, performs task scheduling every time one task is completed or periodically, and executes tasks such that, for example, task A, task B, and state determination unit 33 are executed at a predetermined frequency. .

  The state determination unit 33 confirms the execution states of the tasks A and B and determines whether or not to shift to the sleep mode. For example, the time when task A and task B were last executed may be recorded, and it may be determined that the mode is shifted to the sleep mode when a predetermined time has elapsed, or the sleep mode generated by task A and task B, respectively. The presence or absence of a migration request may be determined. Further, it may be determined whether or not permission for transition to sleep has been obtained from another microcomputer 100.

  When the state determination unit 33 determines to shift to the sleep mode, the sleep mode execution unit 35 performs a shift process to the sleep mode. The sleep mode execution unit 35 includes a data saving unit 36 and an operation clock setting unit 37. The data saving unit 36 saves the data in the register 11 and the RAM 13 to the backup RAM 17. When the saving is completed, the sleep mode execution unit 35 causes the operation clock setting unit 37 to set the operation clock for the sleep mode, and requests the power supply circuit control unit 34 to perform power control. Thereby, the microcomputer 100 shifts to the sleep mode.

  The wake-up execution unit 41 starts execution when an event that causes the microcomputer 100 to wake up occurs. There are various types of such events and differ depending on the microcomputer 100. Examples of such events include switch-on of predetermined parts, start of CAN communication, elapse of a predetermined time, and the like. The wake-up execution unit 41 is also started when the microcomputer 100 is reset by IG-ON (which means that the main system switch is turned on in a hybrid vehicle or an electric vehicle).

  The occurrence of an event is detected by, for example, the task management function in the sleep mode periodically referring to a specific register 11. The task management function that detects the occurrence of the event assigns the wake-up execution unit 41 to the CPU 12. When the microcomputer is reset, the microcomputer 100 starts normally instead of returning from the sleep mode. Therefore, the CPU 12 starts executing the wakeup execution unit 41 by executing a command at a predetermined address by a reset interrupt.

  The wakeup execution unit 41 includes a first data return unit 41, a wakeup factor determination unit 43, a wakeup boot hook unit 44, and a second data return unit 46. The first data restoration unit 41 performs a data restoration process A described later, and the second data restoration unit 46 performs a data restoration process B described later. The wake-up factor determination unit 43 determines whether the wake-up factor is a wake-up caused by returning from the sleep mode or not. This determination is made because the microcomputer 100 according to the present embodiment treats the return from the sleep mode as the return from the reset, so it is necessary to distinguish whether the return from the sleep mode or the activation by the reset is software. Because. The initial process changes depending on whether the device returns from the sleep mode or starts up from reset. For example, when it is not the return from the sleep mode, the data return from the backup RAM 17 is not necessary.

  The wake-up boot hook unit 44 performs hook processing at the time of wake-up (processing called at a specific part of the program). In the present embodiment, it is assumed that the operation clock setting unit 45 increases the operation clock as a representative process.

  FIG. 5 is an example of a flowchart for explaining the transition of the operation mode of the microcomputer 100. The procedure of FIG. 5 starts when the microcomputer 100 is activated.

  After startup, first, the wakeup execution unit 41 performs a wakeup boot process (S10). The wake-up boot process will be described in the second embodiment. The wake-up boot process includes a startup process from reset and a return process from sleep mode.

  When the wakeup execution unit 41 completes the wakeup boot process, it executes the program (S20). This program means, for example, the start of the main function (in the case of C language), and thereafter the main function is repeatedly executed. The tasks A and B and the state determination unit 33 are functions and routines executed from the main function.

  The state determination unit 33 determines, for example, whether or not the sleep condition is periodically satisfied (S30). When the sleep condition is not satisfied (No in S30), the CPU 12 continuously executes the program.

  When the sleep condition is satisfied (Yes in S30), the sleep mode execution unit 35 performs a transition process to the sleep mode (S40). First, the sleep mode execution unit 35 records the transition to the sleep mode in the microcomputer status register. Specifically, the sleep detection reset flag of the microcomputer status register is set to “1”. Therefore, at the time of wakeup, the CPU 12 can read out the microcomputer status register from the backup RAM 17 to determine whether to return from the sleep mode or to start from reset. Note that whether the flag “1” or “0” indicates ON / OFF of the flag is a design matter.

  In addition, the microcomputer status register includes a flag indicating the cause of reset. Causes of reset include IG-ON, occurrence of abnormality or external reset by WDT, battery low voltage, internal low voltage, and the like.

  The data saving unit 36 saves the data in the RAM 13 to the backup RAM 17 for each predetermined section. A section is an area (address range) or block of the RAM 13 or the backup RAM 17, and the areas of the backup RAM 17 and the RAM 13 can be specified by specifying a section name that does not overlap. Further, the data saving unit 36 saves the data of all the registers 11 to the backup RAM 17 by specifying the register name. It is clear to the first data restoration unit 41 and the second data restoration unit 46 in which section of the backup RAM 17 the data of the RAM 13 and the register 11 are stored. One of the saved registers 11 includes a microcomputer status register.

  Note that the RAM 13 does not have to save the data in the entire area to the backup RAM 17. Data required by the program after the return is data created by a program such as tasks A and B, parameters for optimizing control, and the like. By saving only the data obtained by such calculation, the saving time and the recovery time can be shortened. In this case, the data saving unit 36 selects data to be saved by saving only the section name and variable name designated in advance from the RAM 13.

  After saving the data, the operation clock setting unit 37 reduces the operation clock, and the power supply circuit control unit 34 turns off the power supply to circuits other than the CPU 12. Thereby, the microcomputer 100 shifts to the sleep mode.

  After shifting to the sleep mode, the CPU 12 waits until a wake-up event is detected (S50). When a wake-up event is detected (Yes in S50), the wake-up boot process in step S10 is executed.

  As described above, the microcomputer 100 of this embodiment saves data in the backup RAM 17 connected only to the CPU 12, so that the power of the register 11 and the RAM 13 can be turned off, and the leakage current can be reduced, so that the sleep mode can be reduced. Power consumption can be reduced.

  In the first embodiment, the backup RAM 17 is provided in the microcomputer 100. However, in such a microcomputer 100, data restoration processing from the backup RAM 17 to the register 11 or the RAM 13 is necessary at the time of wakeup, so that the execution of tasks A, B, etc. is started after the wakeup is started. There is a possibility that the time of the process becomes longer. In this embodiment, a wakeup method for shortening the wakeup time of the microcomputer 100 provided with the backup RAM 17 will be described.

  FIG. 6 is an example of a diagram for schematically explaining the wake-up procedure of the present embodiment. In FIG. 6, in order of time, microcomputer activation, register initialization, “data recovery process A (wakeup determination)”, wakeup boothook, main clock oscillation setting, main clock oscillation stabilization wait, PLL clock oscillation setting, PLL clock Waiting for oscillation stabilization, “Data recovery process B”. Among these, “data restoration processing A (wakeup determination)” and “data restoration processing B” are processing due to the installation of the backup RAM 17.

  As shown in the figure, it takes time to oscillate and stabilize the operation clock during wakeup. Although it varies greatly depending on the microcomputer 100, in the figure, the operation clock gradually increases such as a CR clock oscillation period (about 500 to 750 kHz), a main clock oscillation period (about 1 M to 4 MHz), and a PLL clock oscillation period (8 M to 128 MHz). To do. Note that the operation clock does not necessarily increase in three stages, and the number of steps of the operation clock at the time of the increase depends on the microcomputer 100. The CR clock is an operation clock during the sleep mode.

  Therefore, if the processing is started while the operation clock is low, the increase in the recovery time due to the mounting of the backup RAM 17 can be absorbed to some extent by the oscillation / stable time of the operation clock. The timing at which “data restoration processing A (wakeup determination)” and “data restoration processing B” are executed can be appropriately designed. In this embodiment, “data recovery processing A (wakeup determination)” is performed with the CR clock during sleep having the lowest operation clock, and “data recovery processing B” is executed when the clock clock is stabilized to the highest PLL clock. . In the “data restoration process A”, only the minimum necessary data is restored, and most data is restored in the “data restoration process B”, so that the delay of the wakeup time can be minimized.

  Note that the “data recovery process B” may be started while the operation clock is the CR clock. Further, “data recovery processing A” may be started when the main clock is stabilized, and “data recovery processing B” may be started when the main clock is stabilized. “Data restoration processing B” may be started.

・ Data restoration processing A
Essential processing: This is because the microcomputer status register is read from the backup RAM 17 to determine whether or not to return from the sleep mode based on the sleep detection reset flag of the microcomputer status register. Further, the data recovery process A includes a wake-up determination as to whether or not to return from the sleep mode.
Option processing 1: Main clock oscillation setting and data required for PLL clock oscillation setting (operation clock indication value) are read from the backup RAM 17 as an option. Depending on the microcomputer 100, the main clock oscillation setting and the PLL clock setting value are optional. This is because there is no need to read from the backup RAM 17 because it is fixed.
Option processing 2: Read out necessary data from the backup RAM 17 at an early stage Since the data necessary at an early stage varies depending on the microcomputer 100 and the program executed by the microcomputer 100, the developer sets the first data return unit 41 in advance. .

・ Data restoration processing B
Mandatory processing: The data of the RAM 13 and the register 11 held in the backup RAM 17 before the sleep is written to the RAM 13 and the register 11. Some specifications do not write data. For such a microcomputer 100, the essential process of the data restoration process B is not required. If the data restoration process B is unnecessary, the second data restoration unit that performs the data restoration process B at the time of linking the program may not be linked.

[Operation procedure]
7 to 9 are examples of flowcharts for explaining the wake-up procedure. The procedure of FIG. 7 starts when an event that wakes up the microcomputer 100 is detected or when the microcomputer 100 is reset (activated). The process of FIG. 7 corresponds to the process of step S10 of FIG.

  Note that the power supply circuit control unit 34 supplies power to all the circuits from the power supply circuit 21 by wakeup. The operation clock is stable to the CR clock when returning from the sleep mode, and the wake-up process is executed after the CR clock is stabilized when starting from reset.

  First, the wakeup execution unit 41 sets the processor to disable interrupts (S101). By disabling interrupts, it is possible to prevent an interrupt from entering and another process from being executed during wakeup. In order to set the interrupt prohibition, a predetermined value is set in the interrupt prohibition register.

  Next, the wakeup execution unit 41 initializes a dedicated register for wakeup (S102). The dedicated register is a register for storing an index of a pointer or an address.

  Then, before the operation clock is raised, “data recovery process A & wakeup determination” is executed (S200). This process will be described with reference to FIG.

  Next, the wakeup boot hook unit 44 performs hook processing at the time of wakeup (S103). As described above, in this hook process, the operation clock is increased.

  First, the operation clock setting unit 45 sets the instruction value of the main clock acquired in the data restoration process A in the main clock generation circuit 19 (S104). As a result, the operation clock rises to the main clock.

  The operation clock setting unit 45 waits for a predetermined time until the operation clock is stabilized by the main clock (S105).

  Next, the operation clock setting unit 45 sets the instruction value of the PLL clock acquired in the data restoration process A in the PLL circuit 20 (S106). As a result, the operation clock rises to the PLL clock.

  The operation clock setting unit 45 waits for a predetermined time until the operation clock is stabilized by the PLL clock (S107).

  Next, the second data restoration unit 46 initializes the RAM 13 and the like for the data restoration process B. First, the second data return unit 46 initializes the stack area in the RAM 13 (S108). By initializing only the area to be used instead of the entire RAM 13, the time for the restoration process can be shortened.

  Next, the second data return unit 46 initializes the general-purpose register (S109).

  Then, the second data restoration unit 46 executes “data restoration process B” (S300). This process will be described with reference to FIG.

  When the data restoration process B is completed, the CPU 12 executes programs such as the mainsks A and B (S110). In other words, the process proceeds to step S20 in FIG.

  FIG. 8 is an example of a flowchart for explaining an execution procedure of “data restoration process A & wakeup determination”.

  The first data return unit 41 reads data in the microcomputer status register from the CPU 12 (S201). This process corresponds to the essential process of the data restoration process A described above. Thereafter, the wakeup factor determination unit 43 determines the wakeup factor.

  The wake-up factor determination unit 43 performs a logical operation on the data in the microcomputer status register and a predetermined MASK value to extract a power-on detection reset flag. Then, the wakeup factor determination unit 43 determines whether or not the power-on detection reset flag is ON (S202).

  If the power-on detection reset flag is ON, the wake-up process is caused not by the return from the sleep mode but by a reset by IG-ON. Therefore, when the power-on detection reset flag is ON (Yes in S202), the process proceeds to step S210.

  When the power-on detection reset flag is not ON (No in S202), the wakeup factor determination unit 43 determines whether or not the external reset detection flag is ON (S203). That is, the external reset detection flag is extracted by performing a logical operation on the data in the microcomputer status register and a predetermined MASK value.

  If the external reset detection flag is ON, the wake-up process is caused not by the return from the sleep mode but by an external reset. Accordingly, when the external reset detection flag is ON (Yes in S203), the process proceeds to step S210.

  When the external reset detection flag is not ON (No in S203), the wakeup factor determination unit 43 determines whether the external low voltage reset detection flag is ON (S204). That is, the external low voltage reset detection flag is extracted by performing a logical operation on the data in the microcomputer status register and a predetermined MASK value.

  When the external low voltage reset detection flag is ON, the reset factor is that the wake-up process is not the return from the sleep mode but the battery voltage is equal to or lower than the threshold value. Therefore, when the external low voltage reset detection flag is ON (Yes in S204), the process proceeds to step S210.

  When the external low voltage reset detection reset flag is not ON (No in S204), the wakeup factor determination unit 43 determines whether or not the internal low voltage reset detection flag is ON (S205). That is, the internal low voltage reset detection flag is extracted by performing a logical operation on the data in the microcomputer status register and a predetermined MASK value.

  When the internal low voltage reset detection flag is ON, the reset factor is that the wake-up process is not the return from the sleep mode but the voltage of the power supply circuit 21 is equal to or lower than the threshold value. Therefore, when the internal low voltage reset detection flag is ON (Yes in S205), the process proceeds to step S210.

  When the internal low voltage reset detection reset flag is not ON (No in S205), the wakeup factor determination unit 43 similarly determines whether or not to return from sleep (S206). That is, the sleep detection flag is extracted by performing a logical operation on the data in the microcomputer status register and a predetermined MASK value.

  If the sleep detection flag is not ON (No in S206), the process similarly proceeds to step S210.

  When the sleep detection flag is ON (Yes in S206), it is determined that the wake-up factor is the return from the sleep mode. Therefore, the first data restoration unit 41 executes the option process of the data restoration process A. The optional processing of the microcomputer 100 according to the present embodiment is to read the main clock and PLL clock instruction values necessary for setting the operation clock from the backup RAM 17.

  The first data return unit 41 reads the instruction value of the main clock or PLL clock from the backup RAM 17 (S207). Thereafter, the process returns to S103 of FIG.

  When the process transitions to step S210, the data recovery is not performed and the activation process from reset is performed. After the activation process from reset, programs such as tasks A and B are executed.

  FIG. 9 is an example of a flowchart for explaining the execution procedure (S300) of “data restoration processing B”. Steps S103 to S110 including step S300 in FIG. 7 are executed when it is determined in step S200 to return from the sleep mode. Therefore, the second data restoration unit 46 may restore the data in the RAM 13 and the register 11 from the backup RAM 17.

  The second data restoration unit 46 writes the data read from the backup RAM 17 to the RAM 13 and the register 11 respectively (S301). This process corresponds to the essential process of the data restoration process B.

  In addition, the second data restoration unit 46 restores any necessary data or sets data in the peripheral circuit (S302). Thereafter, the process returns to S110 of FIG.

  As described above, the microcomputer of this embodiment restores a minimum amount of data while the operation clock is slow, and restores most of the data after the operation clock becomes fast. For this reason, the wake-up time of the microcomputer 100 including the backup RAM 17 that holds the data during sleep can be shortened.

11 Register 12 CPU
13 RAM
17 Backup RAM
18 Oscillator 35 Sleep mode execution unit 41 Wake-up execution unit 100 Microcomputer

Claims (8)

An information processing apparatus having saved data storage means for holding data created in the work storage means during the first operation mode during the second operation mode,
Clock generating means for generating an operation clock for the second operation mode and an operation clock for the first operation mode that is larger than the operation clock for the second operation mode;
When returning from the second operation mode, before the clock generation means raises the operation clock to the first operation mode, the information processing apparatus status data indicating the state of the information processing apparatus is read from the saved data storage means. First data return means for returning to the working storage means;
After the clock generation means raises the operation clock to the first operation mode, the second data restoration for restoring the data created during the first operation mode from the saved data storage means to the working storage means Means,
An information processing apparatus. The first data restoration means restores predetermined early restoration data from the saved data storage means to the work storage means before the clock generation means raises the operation clock to the first operation mode. ,
The information processing apparatus according to claim 1. The information processing apparatus status flag has information indicating whether the state of the information processing apparatus is a return from the second operation mode or a start from reset,
The information processing apparatus according to claim 1 or 2.   The information processing apparatus according to claim 2, wherein the early return data is data indicating an operation clock of the first operation mode. Only when the information processing apparatus status flag includes information that the state of the information processing apparatus is a return from the second operation mode,
The first data return means returns information processing apparatus status data from the saved data storage means to the work storage means, and the second data return means transfers the data created during the first operation mode to the work data storage means. Returning from the saved data storage means to the working storage means;
The information processing apparatus according to claim 3.   6. The information processing apparatus according to claim 1, wherein the save data storage unit is connected only to a processor included in the information processing apparatus.   7. The information processing apparatus according to claim 6, wherein when the saved data storage means is a non-volatile memory, the power to the saved data storage means is shut off in the second operation mode. A data restoration method for an information processing apparatus having saved data storage means for holding data created in a working storage means during a first operation mode for executing a program during a second operation mode,
A step of generating a clock for the second operation mode by the clock generation means;
Before the clock generation means raises the operation clock to the first operation mode, the first data restoration means sends the information processing apparatus status data indicating the state of the information processing apparatus from the saved data storage means to the work data. Returning to the storage means;
The clock generation means generating an operation clock of the first operation mode that is larger than the second operation mode;
After the clock generation unit raises the operation clock to the first operation mode, the second data restoration unit transfers the data created during the first operation mode from the saved data storage unit to the work storage unit. Step to return to
A data recovery method.

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