JP2008234046A - Oscillation circuit and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simultaneously reduce power consumption and increas speed of an MCU after power supply, after a reset, and after recovery from a standby state, in an oscillation circuit and a semiconductor device. <P>SOLUTION: This oscillation circuit has: a first oscillation circuit; a second oscillation circuit having a longer oscillation stable time than the first oscillation circuit; a signal generation circuit outputting a stable signal showing a lapse of the oscillation stable time of the second oscillation circuit; a switch circuit selectively outputting one of output of the first and second oscillation circuits based on a selection signal; and an inhibit circuit inhibiting start of the second oscillation circuit based on an inhibit signal. The oscillation circuit has: a mode to start the first and second oscillation circuits simultaneously, and switch to output of the second oscillator circuit after output of the first oscillation circuit is selectively outputted by the switch circuit; and a mode to start the first oscillator circuit, while not starting the second oscillation circuit by the inhibit circuit, and selectively output only the output of the first oscillator circuit by the switch circuit. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an oscillation circuit and a semiconductor device, and more particularly to an oscillation circuit suitable for a clock generation circuit that generates a clock and a semiconductor device having such an oscillation circuit.

  Conventionally, some semiconductor devices (or semiconductor chips) such as a microcontroller (MCU) have a configuration in which a clock generation circuit is incorporated. The clock generation circuit includes a CR oscillation circuit, a ring oscillator, or the like, and supplies the MCU clock to the CPU in the MCU. Oscillation circuits that use crystal or ceramic resonators have a long start-up time (or oscillation stabilization time) until the output frequency of the oscillation circuit stabilizes. It may be desirable to use a CR oscillation circuit, a ring oscillator, or the like with a short start-up time (or oscillation stabilization time) as a clock source. In applications where the stop and start of the oscillation circuit are frequently repeated, reducing power consumption during the start-up time of the oscillation circuit (that is, the oscillation stabilization time) is a viewpoint of improving the overall performance of the MCU. May be desirable.

  In general, an oscillation circuit using a frequency control element having a high Q value indicating the sharpness of oscillation, such as a ceramic oscillator or a crystal oscillator, can oscillate with extremely high accuracy and has a small frequency deviation with respect to a nominal frequency. However, for example, the time required to sufficiently stabilize the oscillation frequency and the signal amplitude of the oscillation circuit after power is applied (hereinafter referred to as oscillation stabilization time) is as long as several tens to several hundreds of microseconds. On the other hand, a CR oscillation circuit using an element having a low Q value (frequency control element, resistance, capacitance) having a low Q value is not high in oscillation frequency accuracy, contrary to a ceramic oscillation circuit or a crystal oscillation circuit. The waiting time (oscillation stabilization time) at the start of the circuit is short.

  Various proposals have been made, for example, in Patent Documents 1 to 5, in which a combination of such oscillation circuits having different oscillation frequency accuracy and oscillation stabilization time is used to improve the overall system performance.

  FIG. 1 is a circuit diagram showing an example of a conventional oscillation circuit, and FIG. 2 is a timing chart for explaining the operation of the oscillation circuit of FIG. The oscillation circuit shown in FIG. 1 is described, for example, in FIG.

  The oscillation circuit includes a CR oscillation circuit CRO101, a crystal or ceramic oscillation circuit OSC101, switch circuits SW102 and SW103, a counter circuit CUNT101, a D flip-flop circuit DFF101, a buffer circuit BUF101, and an AND circuit AND101 connected as shown in FIG. The oscillation circuit OSC101 includes a switch circuit SW101, capacitors C101 and C102, a resistor R101, a crystal resonator or ceramic resonator XTAL101, and an inverter circuit INV101 that are connected as shown in FIG. In the following description, for the sake of convenience, it is assumed that the oscillation circuit OSC101 is a ceramic oscillation circuit having the ceramic resonator XTAL101. In FIG. 1, Vdd is a positive power supply voltage (for example, +3 V), GND is a ground potential (0 V), COUT is an output of the counter circuit CUNT101, DFO is a positive output of the flip-flop circuit DFF101, and DFOX is an output of the flip-flop circuit DFF101. Negative output, CLCNT is the output of the AND circuit AND101, VDDCR is an input to the power supply terminal of the CR oscillation circuit CRO101, NX100 and NX101 are external connection terminals of the ceramic oscillation circuit OSC101, OSCO1 is the oscillation output of the ceramic oscillation circuit OSC101, OSCO2 is The oscillation output of the CR oscillation circuit CRO101, OSCEN indicates an input signal to the enable terminal of the ceramic oscillation circuit OSC101, and CKO indicates an output clock.

  The waiting time (oscillation stabilization time) when starting up the oscillation circuit OSC101 is long, but the oscillation frequency accuracy is high. On the other hand, the oscillation frequency accuracy of the CR oscillation circuit CRO101 is low, but the waiting time (oscillation stabilization time) at startup is short. In the oscillation circuit of FIG. 1, two oscillation circuits OSC101 and CRO101 having different characteristics are used to improve the overall performance of the MCU.

  Since the waiting time when starting up the CR oscillation circuit CRO101 is short, the output OSCO2 of the CR oscillation oscillation circuit CRO101 is stabilized before the output OSCO1 of the ceramic oscillation circuit OSC101 after the MCU is turned on or reset. When only the output OSCO1 is used, for example, MCU processing cannot be started until the output OSCO1 is stabilized. However, by using the output OSCO2 as a clock, for example, processing of the MCU is performed during the period until the output OSCO1 is stabilized. Can proceed. After the output OSCO1 is stabilized, the output OSCO1 with high frequency accuracy can be used as a clock source by switching the clock from the output OSCO2 to the output OSCO1.

  FIG. 2 shows the details of such a switching operation. Immediately after the MCU is powered on or reset, the signal OSCEN is at a low (L) level. Since the signal OSCEN is at L level, the output CLCNT of the AND circuit AND101 is also at L level. Since the output CLCNT is at L level, the counter circuit CUNT101 is cleared and the output COUT is at L level. Also, the counter circuit CUNT101 is initialized. Similarly, since the signal OSCEN is at L level, the D flip-flop circuit DFF101 is also cleared and the output DFO is at L level. Since the output DFOX is an inverted signal of the output DFO, it is at a high (H) level.

  After the power is turned on or reset, the operation of the oscillation circuits OSC101 and CRO101 is started by changing the signal OSCEN from the L level to the H level. When the signal OSCEN is set to the H level, the switch circuit SW101 is turned on, the power supply voltage Vdd is supplied to the inverter circuit INV101, and the ceramic oscillation circuit OSC101 starts operating. Since the output DFOX is at the H level, if the signal OSCEN is at the H level, the output CLCNT of the AND circuit AND101 is also at the H level. When the output CLCNT becomes H level, the switch circuit SW102 is turned on, the input VDDCR becomes H level, the power supply voltage Vdd is supplied to the CR oscillation circuit CRO101, and the CR oscillation circuit CRO101 also starts operation.

  After the switch circuit SW102 is turned on, the output OSCO2 is stabilized. After the signal amplitude and the oscillation frequency of the output OSCO2 are stabilized, the signal amplitude and the oscillation frequency of the output OSCO1 are stabilized. After the output OSCO2 is stabilized, the output OSCO2 is output as the output clock CKO by the switch circuit SW103. For example, the operation of the MCU can be started using the output clock CKO as a reference clock.

  In the example shown in FIG. 2, the oscillation frequency of the output OSCO2 is lower than the oscillation frequency of the output OSCO1. Since the oscillation frequency accuracy of the ceramic oscillation circuit OSC101 is high, the oscillation frequency may be set to a specified frequency at which the MCU operates. However, since the oscillation frequency accuracy of the CR oscillation circuit CRO101 is low, even when the oscillation frequency becomes maximum. The design must be such that the MCU can operate. For this reason, the center value of the oscillation frequency of the CR oscillation circuit CRO101 must be designed to be small to some extent. In view of such circumstances, the oscillation frequency of the output OSCO2 is shown as being lower than the oscillation frequency of the output OSCO1.

  When a certain amount of time elapses after the output OSCO1 starts oscillating, the signal amplitude and oscillation frequency of the ceramic oscillation circuit OSC101 are stabilized. In order to know the passage of this time, the output OSCO1 is counted by the counter circuit CUNT101. The output COUT of the counter circuit CUNT101 changes from the L level to the H level by repeating the change between the H level and the L level by the predetermined number of times of output OSCO1. As the output COUT changes from L level to H level, the output DFO of the flip-flop circuit DFF101 also changes from L level to H level. When the output DFO changes from the L level to the H level, the switch circuit SW103 is switched, and the output OSCO1 is output as the output clock CKO.

  As the output DFO changes from L level to H level, the output DFOX of the flip-flop circuit DFF101 changes from H level to L level. When the output DFOX becomes L level, the output CLCNT of the AND circuit AND101 also becomes L level. Since the clear terminal CL of the counter circuit CUNT101 becomes L level, the counter circuit CUNT101 stops its operation and is cleared, and the output COUT becomes L level. When the output CLCNT of the AND circuit AND101 becomes L level, the switch circuit SW102 is turned off, the power supply voltage Vdd is not supplied to the CR oscillation circuit CRO101, and the CR oscillation circuit CRO101 stops its operation. In FIG. 2, the change of the input VDDCR from the H level to the L level indicates that the power supply is stopped by the output CLCNT of the AND circuit AND101.

With the configuration and operation as described above, the output OSCO2 of the CR oscillation circuit CRO101 is used as the output clock CKO immediately after the power is turned on, and after the output of the ceramic oscillation circuit OSC101 is stabilized, the output OSCO1 of the ceramic oscillation circuit OSC101 is output clock. It is used as CKO and the operation of the CR oscillation circuit CRO101 is stopped. In this way, until the output OSCO1 of the ceramic oscillation circuit OSC101 is stabilized, the MCU processing can be advanced by using the output OSCO2 of the CR oscillation circuit CRO101 as the output clock CKO, and the output OSCO1 of the ceramic oscillation circuit OSC101. Is stabilized, the output OSCO1 of the ceramic oscillation circuit OSC101 with high oscillation frequency accuracy can be used as the output clock CKO.
JP 2002-314336 A JP 2001-251140 A Japanese Patent Laid-Open No. 10-161768 JP-A-4-171513 JP-A-53-60149

  In the oscillation circuit shown in FIG. 1, the counter circuit CUNT101 counts the output OSCO1 of the ceramic oscillation circuit OSC101, and after a predetermined time has elapsed, the output clock CKO is changed from the output OSCO2 of the CR oscillation circuit CRO101 to the output OSCO1 of the ceramic oscillation circuit OSC101. Switch. If the program to be executed is large after the MCU power is turned on, there is no problem with the circuit configuration as shown in FIG. 1, but the following problems occur when applied to a general control MCU. The present inventors have noticed.

  For example, when the program execution is restarted (interrupt program is executed) by an interrupt from the standby state (assuming that the oscillation circuit is stopped), or when the interrupt program is large, the ceramic oscillation circuit It is more efficient to activate the OSC 101 and proceed with the processing at the maximum operating frequency with a clock with high frequency accuracy. However, if the interrupt program is small and the amount of processing is small, the necessary processing may be completed before the output OSCO1 of the ceramic oscillation circuit OSC101 is stabilized. In such a case, it is more efficient to supply the clock by the CR oscillation circuit CRO101 without activating the ceramic oscillation circuit OSC101, to end the processing, and to set the standby state again to wait for the next interrupt. high.

  In other words, whether or not it is better to use the output OSCO2 of the ceramic oscillation circuit CRO101 depends on the program in the case of a general MCU, and in order to perform appropriate clock control in various situations, the circuit shown in FIG. However, if it is controlled uniformly by hardware, waste will occur.

  As an example, the operation of the oscillation circuit of FIG. 1 will be described in the case where the MCU executes a small interrupt program from the standby state and again enters the standby state. Here, it is assumed that interrupt program execution starts when the output OSCO2 of the CR oscillation circuit CRO101 becomes stable. Simultaneously with activation of the CR oscillation circuit CRO101, the ceramic oscillation circuit OSC101 is also activated in the oscillation circuit of FIG. Before the output OSCO1 of the ceramic oscillation circuit OSC101 is stabilized, the interrupt program processing is completed, and the MCU is again in the standby state. In such a situation, in the oscillation circuit of FIG. 1, the ceramic oscillation circuit OSC101 that is not used is started up every time, and a portion corresponding to the power consumption of the ceramic oscillation circuit OSC101 is wasted.

  That is, in the oscillation circuit of FIG. 1, the CR oscillation circuit CRO101 and the ceramic oscillation circuit OSC101 are simultaneously activated based on hardware control, and the clock CKO is changed from the output OSCO2 of the CR oscillation circuit CRO101 to the output OSCO1 of the ceramic oscillation circuit OSC101. Since it is configured to be switched, there is a problem that optimal control for reducing power consumption cannot be performed according to the program status.

  Therefore, an object of the present invention is to provide an oscillation circuit and a semiconductor device that can achieve both high speed processing and low power consumption of an MCU after power-on, reset, and recovery from a standby state.

  The above-described problem is that a first oscillation circuit, a second oscillation circuit having an oscillation stabilization time longer than the first oscillation circuit, and a stabilization signal indicating the passage of the oscillation stabilization time of the second oscillation circuit are output. A signal generation circuit that performs selection, a switch circuit that selectively outputs one of the outputs of the first and second oscillation circuits based on a selection signal, and a suppression circuit that suppresses activation of the second oscillation circuit based on a suppression signal A mode in which the first and second oscillation circuits are activated simultaneously and the switch circuit selects and outputs the output of the first oscillation circuit and then is switched to the output of the second oscillation circuit; The first oscillation circuit is activated, and the second oscillation circuit is not activated by the suppression circuit, and only the output of the first oscillation circuit is selectively output by the switch circuit. This can be achieved by an oscillation circuit.

  The above problem is that the first oscillation circuit, the second oscillation circuit having an oscillation stabilization time longer than the first oscillation circuit, information that can be set from the outside, and information that is set from the outside Is set in the control register unit, a signal generation circuit that outputs a stability flag indicating the passage of the oscillation stabilization time of the second oscillation circuit and sets the control register unit in the control register unit And a switch circuit that selectively outputs one of the outputs of the first and second oscillation circuits based on a selection bit, and the first and second oscillation circuits are activated simultaneously and are switched by the switch circuit. This can be achieved by an oscillation circuit characterized by having a first mode that is switched to the output of the second oscillation circuit after the output of the oscillation circuit is selectively output.

  The above-described problem is a semiconductor device including a clock generation circuit, a control register unit, and a CPU, and the clock generation circuit has a first oscillation circuit and an oscillation stabilization time longer than that of the first oscillation circuit. The second oscillation circuit, the control register unit that can set information from the software of the CPU and can refer to the information set by the software, and the passage of the oscillation stabilization time of the second oscillation circuit A signal generation circuit that outputs a stability flag to set in the control register unit, and selectively outputs one of the outputs of the first and second oscillation circuits based on a selection bit set in the control register unit A switch circuit, and after the semiconductor device is turned on, after resetting or after returning from the standby state to the operating state, the first and second oscillation circuits are activated simultaneously, and the switch It can be achieved by a semiconductor device and having a first mode in which the output of the first oscillator circuit is switched to the output of the second oscillator circuit after the selected output by road.

  According to the present invention, it is possible to realize an oscillation circuit and a semiconductor device that can achieve both high speed processing and low power consumption of an MCU after power-on, reset, and recovery from a standby state.

  In the present invention, the first and second oscillation circuits are provided in the oscillation circuit so as to be selectable by software. The first oscillation circuit uses an element having a low Q value (frequency control element, resistance, capacitance) having a low Q value, and the oscillation frequency accuracy is not high, but the waiting time at startup (oscillation stabilization time) is relatively short. . The second oscillation circuit uses a frequency control element having a high Q value and can oscillate with very high accuracy and has a small frequency deviation with respect to the nominal frequency. For example, the oscillation frequency and signal amplitude after the power supply is applied. The time required to sufficiently stabilize (oscillation stabilization time) is relatively long, for example, from several tens of microseconds to several hundreds of microseconds.

  In the present invention, a mode in which the output of the first oscillation circuit and the output of the second oscillation circuit are switched and used, and a mode in which only the output of the first oscillation circuit is used and the second oscillation circuit is not activated are selected. Is possible. In other words, the designer who designs the program can specify the optimum clock source from the software, and when only the first oscillation circuit is used, the second oscillation circuit is not started. Can be reduced.

  Hereinafter, embodiments of the oscillation circuit and the semiconductor device of the present invention will be described with reference to FIG.

  FIG. 3 is a block diagram showing an embodiment of the present invention. 3 includes a clock generation circuit 11, a CPU 12, and a control register unit 13. The MCU 1 constituting the semiconductor device is a so-called one-chip microcomputer. The clock generation circuit 11 has an oscillation circuit 110 described later, and supplies a clock to the CPU 12. The clock supplied to the CPU 12 may be a clock output from the oscillation circuit 110 or a clock generated in the clock generation circuit 11 based on the clock output from the oscillation circuit 110. The control register unit 13 can be configured by various storage means such as a memory, information of the oscillation circuit 110 can be set from the oscillation circuit 110, can be referred to by software of the CPU 12, and information is set by software. Is possible.

  Note that the control register unit 13 may constitute a part of the oscillation circuit 110 in the clock generation circuit 11.

  As will be described later with reference to FIG. 4, the oscillation circuit 110 is provided with first and second oscillation circuits that can be selected by software via the control register unit 13. The first oscillation circuit uses an element having a low Q value (frequency control element, resistance, capacitance) having a low Q value, and the oscillation frequency accuracy is not high, but the waiting time at startup (oscillation stabilization time) is relatively short. . The second oscillation circuit uses a frequency control element having a high Q value and can oscillate with very high accuracy and has a small frequency deviation with respect to the nominal frequency. For example, the oscillation frequency and signal amplitude after the power supply is applied. The time required to sufficiently stabilize (oscillation stabilization time) is relatively long, for example, from several tens of microseconds to several hundreds of microseconds.

  FIG. 4 is a circuit diagram showing the configuration of the oscillation circuit 110 together with the control register unit 13. The oscillation circuit 110 includes a CR oscillation circuit CRO1, a crystal or ceramic oscillation circuit OSC1, a switch circuit SW2, SW3, a counter circuit CUNT1, a D flip-flop circuit DFF1, a buffer circuit BUF1, and AND circuits AND1, AND2 connected as shown in FIG. , AND3. The AND circuit AND3 has a configuration that inverts one input and then calculates a logical product with the other input. The oscillation circuit OSC1 includes a switch circuit SW1, capacitors C1 and C2, a resistor R1, a crystal resonator or ceramic resonator XTAL1, and an inverter circuit INV1, which are connected as shown in FIG. In the following description, for the sake of convenience, it is assumed that the oscillation circuit OSC1 is a ceramic oscillation circuit having a ceramic resonator XTAL1. The CR oscillation circuit CRO1 constitutes the first oscillation circuit, and the ceramic oscillation circuit OSC1 constitutes the second oscillation circuit. The AND circuit AND1, the counter circuit CUNT1, and the D flip-flop circuit DFF1 output a stable signal indicating the lapse of the oscillation stabilization time of the second oscillation circuit (that is, the OSC1 stable negative rough OSF is set in the control register unit 13). A signal generation circuit is configured. The switch circuit SW3 constitutes a switch circuit that selects and outputs one of the outputs of the first and second oscillation circuits based on the selection signal (that is, the OS1 selection bit SOS1 from the control register unit 13). The AND circuit AND2, the switch circuit SW1, and the inverter circuit INV1 constitute a suppression circuit that suppresses activation of the second oscillation circuit based on the inhibition signal (that is, the OSC1 activation inhibition bit IHOS1 from the control register unit 13). .

  In FIG. 4, Vdd is a positive power supply voltage (for example, +3 V), GND is a ground potential (0 V), COUT is an output of the counter circuit CUNT1, DFO is a positive output of the flip-flop circuit DFF1, and DFOX is an output of the flip-flop circuit DFF1. Negative output, CLCNT is output of AND circuit AND1, VDDCR is input to the power supply terminal of CR oscillation circuit CRO1, NX0 and NX1 are external connection terminals of ceramic oscillation circuit OSC1, OSCO1 is oscillation output of ceramic oscillation circuit OSC1, and OSCO2 is The oscillation output of the CR oscillation circuit CRO1, OSCEN indicates an enable signal for the ceramic oscillation circuit OSC1, and CKO indicates an output clock. Further, CSW1 is a control signal for the switch circuit SW1, CSW2 is a control signal for the switch circuit SW2, OSCCR is a control register for switching and controlling the oscillation circuit 110 from software, OSIF is an interrupt flag for generating an interrupt signal, OSF Is a flag indicating that the output of the ceramic oscillation circuit OSC1 has been stabilized, OSFIE is a bit for permitting an interrupt when the interrupt flag OSIF is set, SOS1 is the software to explicitly set the oscillation circuit 110 to the CR oscillation circuit CRO1 Is a bit for switching from 1 to ceramic oscillation circuit OSC1, IHOS1 is a bit for suppressing activation of ceramic oscillation circuit OSC1, and IRQOSC is an interrupt signal generated when the output of ceramic oscillation circuit OSC1 is stabilized.

  Although the waiting time (oscillation stabilization time) when starting up the oscillation circuit OSC1 is long, the oscillation frequency accuracy is high. On the other hand, the oscillation frequency accuracy of the CR oscillation circuit CRO1 is low, but the waiting time (oscillation stabilization time) at startup is short. In the oscillation circuit 110 of FIG. 4, the two oscillation circuits OSC1 and CRO1 having different characteristics are used to improve the overall performance of the MCU1.

  As will be described later, the control register unit 13 is set with an OSC1 selection bit SOS1, an OSC1 stable interrupt permission bit OSFIE, an OSC1 stability flag OSF, an OSC1 interrupt flag, an OSC1 activation inhibition bit, and the like.

  In the conventional oscillation circuit shown in FIG. 1, after the output OSCO1 of the ceramic oscillation circuit OSC101 is stabilized using the switch circuit SW103, the counter circuit CUNT101, and the D flip-flop circuit DFF101, the clock CKO is automatically CR-oscillated by hardware. The output OSCO2 of the circuit CRO1 is switched to the output OSCO1 of the ceramic oscillation circuit OSC101.

  On the other hand, in the oscillation circuit 110 of this embodiment shown in FIG. 4, the clock supplied to the MCU 1 is switched from the output OSCO2 of the CR oscillation circuit CRO1 to the output OSCO1 of the ceramic oscillation circuit OSC1 by an interrupt signal and an interrupt program.

  Next, an outline of the processing flow will be described with reference to FIG. 5 to FIG. 8 on the assumption that the MCU 1 is restored from the standby state where the operation of the oscillation circuit 110 is completely stopped and the MCU 1 proceeds with the program processing. . Note that the flow of processing of the oscillation circuit 110 after powering on or resetting the MCU 1 is the same as the flow of processing after returning from the standby state to the operating state, and a description thereof will be omitted. 5 and 8 are timing charts for explaining the operation of the oscillation circuit 110, where H indicates a high level and L indicates a low level. 6 and 7 are flowcharts for explaining the operation of the oscillation circuit 110. FIG. Specifically, FIGS. 6A and 7 show processing of the main program, and FIG. 6B shows processing of the interrupt program.

  Here, for convenience of explanation, it is assumed that the MCU 1 is in a standby state and, for example, the return to the operation state is started by an interrupt signal. When the MCU1 returns to the operating state, the CR oscillation CRO1 and the ceramic oscillation circuit OSC1 start to start. Since the output OSCO2 of the CR oscillation circuit CRO1 is stabilized in a short time, the output OSCO2 is output as the output clock CKO of the oscillation circuit 110. In this example, the output clock CKO is supplied as it is to the CPU 12 as the clock of the MCU1, and as shown in FIG. 6A, the processing of the MCU1 that does not require the oscillation frequency accuracy is started in step S1. As an example of the processing of the MCU 1 that does not require the oscillation frequency accuracy, for example, initialization of values of registers and memories in the MCU 1 can be cited. Examples of processing of the MCU 1 that requires oscillation frequency accuracy include processing such as communication, measurement of time by a timer, generation of pulses at a constant time interval, and the like.

  By using the output OSCO2 of the CR oscillation circuit CRO1 and executing the processing of the MCU1 that does not require the oscillation frequency accuracy, the execution of the program can be advanced without waiting for the stabilization of the output OSCO1 of the ceramic oscillation circuit OSC1. It is possible to speed up the processing of the MCU1.

  As shown in FIG. 6 (a), before executing the processing of MCU1 that requires oscillation frequency accuracy in step S4, step S2 for confirming that the output OSCO1 of the ceramic oscillation circuit CRO1 is stable, and the CPU 12 in the MCU1. Step S3 for confirming that the clock supplied to the output OSCO1 of the ceramic oscillation circuit OSC1 is performed. If the output OSCO1 of the ceramic oscillation circuit OSC1 is not stable, the determination result of step S2 is NO, and therefore step S2 is repeated until the output OSCO1 becomes stable. In step S3, it is confirmed that the output OSCO1 is stable, the determination result in step S2 is YES, and the clock CKO of the MCU1 is switched from the output OSCO2 of the CR oscillation circuit CRO1 to the output OSCO1 of the ceramic oscillation circuit OSC1. If the result is YES, in step S4, the processing of MCU1 that requires oscillation frequency accuracy is executed. By configuring the program in this way, it is possible to prevent the processing that requires the oscillation frequency accuracy from being executed using the output OSCO2 of the CR oscillation circuit CRO1 as the clock CKO.

  FIG. 6B shows an outline of processing of an interrupt program for switching the clock CKO of the MCU1 from the output OSCO2 of the CR oscillation circuit CRO1 to the output OSCO1 of the ceramic oscillation circuit OSC1. It is assumed that the interrupt signal IRQOSC shown in FIG. 4 is generated when the output OSCO1 is stabilized. The processing in FIG. 6B is described as an interrupt program executed by the interrupt signal IRQOSC. When the interrupt signal IRQOSC is generated, the output OSCO1 is stable at this time, so the clock CKO supplied to the CPU 12 is switched from the output OSCO2 to the output OSCO1 in step S11. Further, after switching the clock CKO of the MCU 1 from the output OSCO 2 to the output OSCO 1, the control of the program is returned to the time when the interruption of the original program occurs in step S 12.

  For example, it is assumed that the time when the output OSCO1 is stabilized and the interrupt signal IRQOSC is generated is during a process that does not require oscillation frequency accuracy. In this case, an OSC1 stable interrupt (IRQOSC) is generated during processing that does not require oscillation frequency accuracy, and the clock CKO of MCU1 is switched from the output OSCO2 of the CR oscillation circuit CRO1 to the output OSCO1 of the ceramic oscillation circuit OSC1. Since processing that does not require oscillation frequency accuracy is in progress, there is no problem even when the clock CKO is switched to a clock with high oscillation frequency accuracy. Step S1 in FIG. 6A ends the processing that does not require the oscillation frequency accuracy using the output OSCO1 of the ceramic oscillation circuit OSC1 as a clock source, and step S2 determines whether the output OSCO1 is stable. In this case, since the output OSCO1 is already stable and the clock CKO of the MCU1 is the output OSCO1, the determination results in steps S2 and S3 are both YES, and the oscillation frequency accuracy is required in step S4. Processing is executed.

  Further, it is assumed that the time when the output signal OSCO1 is stabilized and the interrupt signal IRQOSC is generated is the time when the processing that does not require the oscillation frequency accuracy is finished and the output OSCO1 is waiting for stabilization. Also in this case, as in the above case, when the output OSCO1 is stabilized, the interrupt signal IRQOSC is generated, and the clock CKO of the MCU1 is switched from the output OSCO2 to the output OSCO1 by the interrupt program. Step S1 ends the process that does not require the oscillation frequency accuracy, and then, after the determinations in steps S2 and S3, the process that requires the oscillation frequency accuracy is executed in step S4.

  As described above, according to the oscillation circuit 110 having the configuration shown in FIG. 4, the output OSCO2 of the CR oscillation circuit CRO1 can be obtained even when the interrupt signal and the interrupt program are used, as in the case of the conventional oscillation circuit shown in FIG. It is possible to start processing of the MCU 1 before the output OSCO 1 of the ceramic oscillation circuit OSC 1 is stabilized.

  Further, according to the oscillation circuit 110 having the configuration shown in FIG. 4, unlike the conventional oscillation circuit shown in FIG. 1, the MCU 1 can be programmed not to use the ceramic oscillation circuit CRO1. For example, assuming that the MCU 1 returns from the standby state in response to the interrupt signal and immediately returns to the standby state after confirming the value of a certain sensor, the CR oscillation can be performed without bothering the ceramic oscillation circuit OSC1 to start. There may be no problem as long as the circuit CRO1 is activated to perform a very short process. In such a case, the power consumption of the oscillation circuit 110 can be reduced by activating only the CR oscillation circuit CRO1, and the power consumption of the MCU 1 as a whole can be reduced.

  FIG. 7 shows the processing of the main program in such a case. If the MCU 1 is expected to return from the standby state to the operating state in advance and the processing time is expected to be very short, the processing as shown in FIG. 7 can be performed. Is desirable. When the MCU 1 returns from the standby state to the operating state in response to the interrupt signal, the activation of the CR oscillation circuit CRO1 is started. At this time, however, the ceramic oscillation circuit OSC1 is not activated. When the output OSCO2 of the CR oscillation circuit CRO1 is stabilized, the output OSCO2 is supplied to the CPU 12 as the clock CKO, and processing that does not require oscillation accuracy is executed in step S22. When the process of step S22 is completed, the operation of the CR oscillation circuit CRO1 is stopped in step S23, and the MCU 1 is again set to the standby state.

  In the conventional oscillation circuit shown in FIG. 1, the ceramic oscillation circuit is activated even in such a situation, whereas the oscillation circuit 110 having the configuration shown in FIG. 4 suppresses activation of the ceramic oscillation circuit OSC1. Therefore, the power consumption of the MCU 1 can be reduced.

  Next, with reference to FIGS. 4, 5 and 8, a description will be given including more specific circuit connections.

  As in the case of the conventional oscillation circuit shown in FIG. 1, it is assumed that the enable signal OSCEN is at L level immediately after the MCU 1 is powered on, immediately after reset, or in a standby state. Since the enable signal OSCEN is at L level, the output CLCNT of the AND circuit AND1 is also at L level. Since the output CLCNT is at L level, the counter circuit CUNT1 is cleared and its output COUT becomes L level. In addition, the counter circuit CUNT1 is initialized. Similarly, since the enable signal OSCEN is at L level, the D flip-flop circuit DFF1 is also cleared and its output DFO becomes L level. Since the output DFOX is an inverted signal of the output DFO, it becomes H level. Assume that the OSC1 activation inhibition bit IHOS1 is at the H level as shown in FIG. It is assumed that the ceramic oscillation circuit OSC1 is also activated when the OSC1 activation inhibition bit IHOS1 is at the H level.

  The operation of the oscillation circuits OSC1 and CRO1 is started by changing the enable signal OSCEN from L level to H level after power-on or reset. When the enable signal OSCEN is set to H level, since the OSC1 activation inhibition bit IHOS1 is at H level, the output CSW1 of the AND circuit AND2 also becomes H level. When the output CSW1 becomes H level, the switch circuit SW1 is turned on, the power supply voltage Vdd is supplied to the inverter circuit INV1, and the oscillation circuit OSC1 starts operating. Since the output DFOX is at the H level, when the enable signal OSCEN becomes the H level, the output CLCNT of the AND circuit AND1 also becomes the H level. Since the output CLCNT becomes H level, when the ceramic oscillation circuit OSC1 starts operation, the counter circuit CUNT1 counts a change in the output OSCO1 of the ceramic oscillation circuit OSC1. As shown in FIG. 5, the OSC1 selection bit SOS1 is assumed to be L level immediately after the MCU1 returns from the standby state. Since the OSC1 selection bit SOS1 is at L level, when the enable signal OSCEN becomes H level, the output CSW2 of the AND circuit AND3 becomes H level. When the output CSW2 of the AND circuit AND3 becomes H level, the switch circuit SW2 is turned on. When the switch circuit SW2 is turned on, the input VDDCR becomes H level, the power supply voltage Vdd is supplied to the CR oscillation circuit CRO1, and the CR oscillation circuit CRO1 also starts its operation.

  The output OSCO2 of the CR oscillation circuit CRO1 stabilizes in a very short time after the switch circuit SW2 is turned on. After the signal amplitude and oscillation frequency of the output OSCO2 are stabilized, the signal amplitude and oscillation frequency of the output OSCO1 of the ceramic oscillation circuit OSC1 are stabilized. After the output OSCO2 of the CR oscillation circuit CRO1 is stabilized, the output OSCO2 is output as the output clock CKO by the switch circuit SW3. The operation of the MCU 1 can be started using the output clock CKO as a reference clock.

  When a certain amount of time elapses after the ceramic oscillation circuit OSC1 starts oscillating, the signal amplitude and oscillation frequency of the output OSCO1 are stabilized. In order to know the passage of this time, the output OSCO1 is counted by the counter circuit CUNT1. By repeating the change of the output OSC1 between the H level and the L level for a predetermined number of times, the output COUT of the counter circuit CUNT1 changes from the L level to the H level.

  As the output COUT of the counter circuit CUNT1 changes from L level to H level, the output DFO of the D flip-flop circuit DFF1 also changes from L level to H level. When the output DFO changes from the L level to the H level, the OSC1 interrupt flag OSIF for the interrupt signal and the OSC1 stability flag OSF indicating that the output OSCO1 of the ceramic oscillation circuit OSC1 is stabilized become the H level. At this time, the OSC1 stable interrupt signal IRQOSC is generated by previously setting the OSC1 stable interrupt permission bit OSFIE to the H level.

  As the output DFO of the D flip-flop circuit DFF1 changes from the L level to the H level, the output DFOX changes from the H level to the L level. When the output DFOX becomes L level, the output CLCNT of the AND circuit AND1 also becomes L level. Since the clear terminal CL of the counter circuit CUNT1 becomes L level, the counter circuit CUNT1 stops its operation and is cleared. As a result, the output COUT of the counter circuit CUNT1 becomes L level.

  As shown in FIG. 5, when the OSC1 stable interrupt signal IRQOSC becomes H level, the program control shifts to the interrupt program. In this interrupt program, first, for example, the OSC1 interrupt flag OSIF is cleared (rewritten to L level). As a result, when the MCU 1 returns from the clock switching interrupt program to the original program, control can be prevented from being transferred to the clock switching interrupt program again. Further, as shown in FIG. 5, the OSC1 stable interrupt signal IRQOSC returns to, for example, the L level. On the other hand, although not shown in FIG. 5, the OSC1 stability flag OSF indicating that the output OSCO1 of the ceramic oscillation circuit OSC1 is stabilized is kept at the H level. Thereby, even after MCU1 returns from the interrupt program, it is possible to determine whether or not the output OSCO1 of the ceramic oscillation circuit OSC1 is stable by referring to the OSC1 stability flag OSF.

  That is, by providing the OSC1 interrupt flag OSIF for generating an interrupt and the OSC1 stability flag OSF indicating that the output OSCO1 of the ceramic oscillation circuit OSC1 is stable, the transfer of control from the main program of the MCU1 to the interrupt program, Even after the control returns from the interrupt program to the main program, it is possible to achieve both functions of determining whether or not the output OSCO1 of the ceramic oscillation circuit OSC1 is stable.

  After clearing the OSC1 interrupt flag OSIF, the OSC1 selection bit SOS1 for clock switching is rewritten to H level in the interrupt program for clock switching. When the OSC1 selection bit SOS1 becomes H level, the switch circuit SW3 is switched, and the output OSCO1 of the ceramic oscillation circuit OSC1 is output as the output clock CKO. The output clock CKO shown in FIG. 5 shows a waveform in such an operation.

  When the OSC selection bit SOS1 becomes H level, the output CSW2 of the AND circuit AND3 becomes L level. When the output CSW2 becomes L level, the switch circuit SW2 is turned off, the power supply voltage Vdd is not supplied to the CR oscillation circuit CRO1, and the CR oscillation circuit CRO1 stops its operation. Further, the input VDDCR becomes L level.

  As described above, the clock of MCU1 is supplied by the CR oscillation circuit CRO1 immediately after the power is turned on, and after the output OSCO1 of the ceramic oscillation circuit OSC1 is stabilized, the clock of the MCU1 is supplied by the ceramic oscillation circuit OSC1 and the CR oscillation circuit. The operation of CRO1 is stopped. With such a configuration of the oscillation circuit 110, even before the output OSCO1 of the ceramic oscillation circuit OSC1 is stabilized, the processing of the MCU1 can be advanced by supplying the output OSCO2 of the CR oscillation circuit CRO1 as the clock of the MCU1, In addition, after the output OSCO1 of the ceramic oscillation circuit OSC1 is stabilized, the output OSCO1 of the ceramic oscillation circuit OSC1 with high oscillation frequency accuracy can be used as the clock of the MCU1.

  FIG. 5 shows waveforms at various parts of the oscillation circuit 110 when the clock supplied to the MCU 1 is switched from the output OSCO2 of the CR oscillation circuit CRO1 to the output OSCO1 of the ceramic oscillation circuit OSC1. On the other hand, FIG. 8 shows waveforms at various parts of the oscillation circuit 110 when only the output OSCO2 of the CR oscillation circuit CRO1 is used.

  In the case of FIG. 8, as in the case of FIG. 5, the enable signal OSCEN is at the L level in the standby state of the MCU1. The activation of the CR oscillation circuit CRO1 by the return of the MCU1 from the standby state to the operating state is the same as in the case of FIG. The difference from FIG. 5 is that the OSC1 activation inhibition bit IHOS1 is at L level in FIG. If the OSC1 activation inhibition bit IHOS1 for inhibiting activation of the ceramic oscillation circuit OSC1 is provided and set to L level in advance, it can be controlled not to activate the ceramic oscillation circuit OSC1. Alternatively, once the ceramic oscillation circuit OSC1 starts to be activated, when the output OSCO2 of the CR oscillation circuit CRO1 is stabilized and the MCU1 starts to operate, the control register OSCCR (in FIG. 4, the address is temporarily shown as 000FFF) By setting the OSC1 activation inhibition bit IHOS1 to L level, the activation of the ceramic oscillation circuit OSC1 can be stopped.

  Next, the operation of the oscillation circuit 110 when the output OSCO1 of the ceramic oscillation circuit OSC1 is not used will be described with reference to FIGS. In this case, MCU1 starts executing the program when the enable signal OSCEN becomes H level and the output OSCO2 of the CR oscillation circuit CRO1 becomes stable. For example, when the OSC1 activation inhibition bit IHOS1 is set to L level after the MCU1 operates, the output CSW1 of the AND circuit AND2 becomes L level, and the power supply voltage Vdd is not supplied to the ceramic oscillation circuit OSC1. Therefore, the operation of the ceramic oscillation circuit OSC1 is stopped and the output OSCO1 remains stopped. The OSC1 selection bit SOS1 is set to L level because the ceramic oscillation circuit OSC1 is not selected. Accordingly, the output OSCO2 of the CR oscillation circuit CRO1 is supplied as the clock CKO of the MCU1. Since the OSC1 selection bit SOS1 is not set to the H level as in the case of FIG. 5, the power supply voltage Vdd is continuously supplied to the CR oscillation circuit CRO1, and the output OSCO2 is supplied as the clock CKO of the MCU1 to continue the processing of the MCU1. .

  Thus, in this embodiment, it is possible to stop the operation of the ceramic oscillation circuit OSC1 and use only the output OSCO2 of the CR oscillation circuit CRO1. For this reason, when the amount of processing required to complete the processing of MCU1 before the output OSCO1 of the ceramic oscillation circuit OSC1 is stabilized is small, the ceramic oscillation circuit OSC1 is not activated and the CR oscillation circuit CRO1 A mode in which the clock CKO is supplied to end the processing of the MCU 1 and the standby state is set again becomes possible. In this case, the ceramic oscillation circuit OSC1 that is not used can be controlled so as not to be activated, so that the power consumption of the entire MCU1 can be reduced.

  FIG. 9 is a circuit diagram showing an example of the configuration of the CR oscillation circuit CRO1 shown in FIG. Needless to say, the configuration of the CR oscillation circuit CRO1 is not limited to the configuration shown in FIG. 9, the same signals as those in FIG. 4 are denoted by the same reference numerals, and the description thereof is omitted. The CR oscillation circuit CRO1 includes a NAND circuit NA21, inverter circuits INV2, INV3, and INV4, a capacitor CT1, a resistor RT1, AND circuits AND4 and AND5, a counter CUNT2, and a D flip-flop circuit DFF2 connected as shown in FIG. In FIG. 9, Vdd is a positive power supply (for example, + 3V), COUT2 is an output of the counter circuit CUNT2, CDFO2 is a positive output of the D flip-flop circuit DFF2, DFOX2 is a negative output of the D flip-flop circuit DFF2, and CRE is CR oscillation. An enable control signal of the circuit CRO1 (a signal having substantially the same function as the output CSW2 of the AND circuit AND3 in FIG. 4), NODE1 to NODE5 indicate nodes.

  FIG. 10 is a timing chart for explaining the operation of the CR oscillation circuit CRO1 shown in FIG. Specifically, FIG. 10 shows signal waveforms at the nodes NODE1 to NODE4. The enable control signal CRE is at L level when the operation of the CR oscillation circuit CRO1 is stopped.

  When the enable control signal CRE is at L level, the output (NODE1) of the NAND circuit NA21 is fixed at L level, so that the CR oscillation circuit CRO1 is stopped. An operation of the circuit portion including the NAND circuit NA21, the inverter circuits INV2 and INV3, the resistor RT1, and the capacitor CT1 when the enable control signal CRE becomes H level will be described.

  As shown in FIG. 10, the signal waveforms at the nodes NODE1, NODE2, and NODE3 are rectangular waves that are general output waveforms of the CMOS circuit. The signal waveform at the node NODE4 is a waveform in which the potential of the node NODE4 changes in the same direction as the node NODE2 at the time of the potential change of the node NODE2 due to capacitive coupling with the node NODE2, and then is gradually charged / discharged by the potential of the node NODE3. It becomes.

  Since an oscillation waveform as shown in FIG. 10 is obtained at the node NODE2, for example, as shown in FIG. 9, an oscillation waveform can be obtained at the node NODE5 by using the inverter circuit INV4. The circuit portion including the counter circuit CUNT2, the D flip-flop circuit DFF2, and the AND circuit AND5 operates in the same manner as the circuit portion including the counter circuit CUNT1, the D flip-flop circuit DFF1, and the AND circuit AND1 shown in FIG. It is assumed that the change in the level of the oscillation waveform at the node NODE5 is counted by the counter circuit CUNT2, and the output COUT2 changes from the L level to the H level when the specified number of times is reached. Since the enable control signal CRE is at L level before the CR oscillation circuit CRO1 is activated, the AND circuit AND5 output is at L level, and the counter circuit CUNT2 is cleared and initialized. Similarly, the D flip-flop circuit DFF2 is also initialized. When the change in the node NODE5 reaches a specified number of times and the output COUT2 of the counter circuit CUNT2 changes from L level to H level, the output CDFO2 of the D flip-flop circuit DFF2 changes to H level. Further, the output DFOX2 of the D flip-flop circuit DFF2 changes to the L level, and the counter circuit CUNT2 is cleared and initialized. When the output CDFO2 of the D flip-flop circuit DFF2 becomes H level, a signal in phase with the node NODE5 appears at the output of the AND circuit AND4, and is output as the output OSCO2 of the CR oscillation circuit CRO1.

  FIG. 11 is a circuit diagram showing an example of the configuration of the switch circuit SW3 shown in FIG. Needless to say, the configuration of the switch circuit SW3 is not limited to the configuration shown in FIG. In FIG. 11, the same parts as those of FIG. The switch circuit SW3 includes inverter circuits INV5, INV6, INV7, NAND circuits NA22 to NA25, an AND circuit AND6, and D flip-flop circuits DFF3 to DFF6 connected as shown in FIG. In FIG. 11, NA22O through NA25O indicate outputs from the NAND circuits NA22 through NA25, DFF3O through DFF6O indicate outputs from the D flip-flop circuits DFF3 through DFF6, and SELI and SELIX indicate selector control signals.

  FIG. 12 is a timing chart for explaining the operation of the switch circuit SW3 shown in FIG. The switch circuit SW3 shown in FIG. 11 has an H level width (period) or an L level width (period) when the clock CKO is switched from the output OSCO2 of the CR oscillation circuit CRO1 to the output OSCO1 of the ceramic oscillation circuit OSC1. The circuit configuration is such that a pulse that is too short is not output as the clock CKO. Here, for convenience of explanation, it is assumed that after the MCU 1 returns from the standby state, the oscillation circuits CRO1 and OSC1 are started and the outputs OSCO2 and OSCO1 are in the state shown in FIG. Assume that the OSC1 selection bit SOS1 is initially at the L level. Since the OSC1 selection bit SOS1 is at L level, the D flip-flop circuits DFF3 to DFF6 are cleared. Since the D flip-flop circuit DFF5 is cleared, the selector control signal SELI is also at the L level.

  Since the selector control signal SELI is at L level, the output NA23O of the NAND circuit NA23 is fixed at H level. Since the selector control signal SELIX is at the H level, the output NA24O of the NAND circuit NA24 is a signal in phase with the output OSCO2 of the CR oscillation circuit CRO1. The NAND circuits NA22, NA23, NA24 function as selector circuits, and selectively output the output OSCO2 of the CR oscillation circuit CRO1 or the output OSCO1 of the ceramic oscillation circuit OSC1 as the output NA24O. In FIG. 12, when the selector control signal SELI is at the L level, the output OSCO2 of the CR oscillation circuit CRO1 and the output NA24O of the NAND circuit NA24 have the same waveform.

  Since the OSC1 selection bit SOS1 is L level, the output DFF4O of the D flip-flop circuit DFF4 is L level. Since the output DFF4O of the D flip-flop circuit DFF4 is L level, the output NA25O of the NAND circuit NA25 is H level. Since the output NA25O of the NAND circuit NA25 is at the H level, the clock CKO becomes a signal in phase with the output NA24O of the NAND circuit NA24, and the output OSCO2 of the CR oscillation circuit CRO1 is output as the clock CKO of the MCU1. Since the OSC1 selection bit SOS1 is at L level, the output DFF6O of the D flip-flop circuit DFF6 is at L level.

  When the output OSCO1 of the ceramic oscillation circuit OSC1 is stabilized, an OSC1 stability interrupt (IRQOSC) is generated, and the OSC1 selection bit SOS1 is rewritten to the H level by the interrupt program. In FIG. 12, the change of the OSC1 selection bit SOS1 from the L level to the H level represents the rewriting of the OSC1 selection bit SOS1 from the L level to the H level by this interrupt program. When the OSC1 selection bit SOS1 becomes H level, the D input of the D flip-flop DFF3 becomes H level, so that the output DFF3O of the D flip-flop circuit DFF3 at the next rising edge of the clock CKO (that is, the next rising edge of the output OSCO2). Becomes H level. Since the signal obtained by inverting the output OSCO2 by the inverter circuit INV6 is input to the clock input terminal CK of the D flip-flop circuit DFF4, the output DFF4O of the D flip-flop circuit DFF4 becomes H level at the next fall of the output OSCO2. . When the output DFF4O of the D flip-flop circuit DFF4 becomes H level, since the output DFF6O of the D flip-flop circuit DFF6 is L level at this time, the output of the inverter circuit INV7 is H level. When the output of the inverter circuit INV7 and the output DFF4O of the D flip-flop circuit DFF4 simultaneously become H level, the output NA25O of the NAND circuit NA25 becomes L level.

  After the output DFF4O of the D flip-flop circuit DFF4 becomes H level, the selector control signal SELI becomes H level at the next rise of the output OSCO2 by the D flip-flop circuit DFF5. Since the selector control signal SELI becomes H level, the selector circuit constituted by the NAND circuits NA22, NA23, NA24 selects and outputs the output OSCO1. FIG. 12 shows a case where the output clock CKO is switched from the output OSCO2 to the output OSCO1 by the output NA24O of the NAND circuit NA24 after the selector control signal SELI becomes H level.

  Since the outputs OSCO1 and OSCO2 of the oscillation circuits OSC1 and CRO1 do not oscillate synchronously, depending on the switching timing, a pulse having a very short H level width or L level width may be output NA24O of the NAND circuit NA24. May appear in Therefore, this undesirable short pulse is removed by an AND circuit AND6 or the like. In FIG. 11, before the selector control signal SELI switches from the L level to the H level, the output NA25O of the NAND circuit NA25 is set to the L level and the output NA25O is output until the output OSCO1 rises after the selector control signal SELI changes. A circuit configuration is employed in which the L level is maintained. Thus, the clock CKO is fixed at the L level during the period when the output NA25O of the NAND circuit NA25 is at the L level by the AND circuit AND6 circuit.

  As indicated by a broken line in FIG. 12, when the selector control signal SELI changes to H level, the D input of the D flip-flop circuit DFF6 also becomes H level, so that the output of the D flip-flop circuit DFF6 is output at the next rise of the output OSCO1. DFF6O becomes H level. Since the inverter circuit INV7 supplies an L level signal to the NAND circuit NA25, the output NA25O of the NAND circuit NA25 returns from the L level to the H level. That is, during the period from the fall of the output OSCO2 before switching to the rise of the output OSCO1 after switching, the output NA25O of the NAND circuit NA25 becomes L level, and the clock CKO is fixed to L level only during this period. As a result, as shown in FIG. 12, a waveform in which a slightly longer L level period is inserted when the waveform of the output OSCO2 and the waveform of the output OSCO1 are switched is obtained.

  5 to 8, a process in which the MCU 1 program designer explicitly uses only the CR oscillation circuit CRO1 or both the CR oscillation circuit CRO1 and the ceramic oscillation circuit OSC1 and uses them by switching them. Explained.

  When the time accuracy of the timer or the pulse generator is required, or when the communication is scheduled and the frequency accuracy of the clock is required in advance, as described with reference to FIGS. In this process, the clock CKO may be switched from the output OSCO2 of the CR oscillation circuit CRO1 to the output OSCO1 of the ceramic oscillation circuit OSC1. When it is known in advance that the oscillation frequency accuracy is not necessary for a series of processing of a program, only the CR oscillation circuit CRO1 is activated and the clock CKO of MCU1 is set by the processing described with reference to FIGS. Just output.

  However, it may be desirable to configure the MPU so that it can cope with, for example, a case where communication is requested from the outside while processing that does not require the oscillation frequency accuracy is in progress. In other words, even if the program is configured assuming that the processing that does not require the oscillation frequency accuracy is advanced and the operation of the CR oscillation circuit is stopped and the operation returns to the standby state when the processing is completed, the program is configured asynchronously from the outside. For example, if there is a possibility that communication is required, it may be desirable to configure the MPU so that the ceramic oscillation circuit can be activated when communication is requested.

  Next, a process when, for example, communication is requested asynchronously from some external device or device while the process that does not require the oscillation frequency accuracy is advanced by the MCU 1 to return to the standby state will be described with reference to FIG. To do. FIG. 13 is a flowchart for explaining the processing of the oscillation circuit 110. FIG. 13A shows the main program processing, FIG. 13B shows the communication request acceptance interrupt program processing, and FIG. 13C shows the OSC1 stable interrupt. Indicates the processing of the program. As described above, when there is a possibility that communication is requested asynchronously from the outside, the processing shown in FIG. 13 can be advanced by generating an interrupt signal in response to a communication request from the outside.

  In FIG. 13A, after the MCU 1 is released from the standby state, in step S31, only the CR oscillation circuit CRO1 is activated and the operation of the ceramic oscillation circuit OSC1 is stopped. In step S32, a process that does not require the oscillation frequency accuracy is performed. When the process is completed, the operation of the CR oscillation circuit CRO1 is stopped and the MCU1 is returned to the standby state again in step S33.

  When communication is requested from the outside, an interrupt signal is generated by the communication request, and the process proceeds to the communication request acceptance interrupt program of FIG. In step S41, the ceramic oscillation circuit OSC1 is activated according to the communication request. Specifically, the OSC1 activation inhibition bit IHOS1 is rewritten from L level to H level to activate the ceramic oscillation circuit OSC1. After starting the ceramic oscillation circuit OSC1, the process returns to the original main program in step S42, and the remaining processes are executed. At this time, since the communication request is not processed even when the processing of the main program is completed, the program is configured so that the MCU 1 enters a waiting state so as not to return to the standby state.

  Since the OSC1 stable interrupt IRQOSC is generated when the output OSCO1 is stabilized after the ceramic oscillation circuit OSC1 is started, the OSC1 stable interrupt program shown in FIG. 13C performs CR oscillation on the clock CKO of the MCU1, for example, in step S51. The output OSCO2 of the circuit CRO1 is switched to the output OSCO1 of the ceramic oscillation circuit OSC1, and a communication request is processed in step S52. In step S53, the process is returned to the main program.

  The details of the program configuration can be variously modified, and it is necessary to adopt a configuration suitable for the actual hardware configuration. In the OSC1 stable interrupt, the clock CKO may be switched from the output OSCO2 of the CR oscillation circuit CRO1 to the output OSCO1 of the ceramic oscillation circuit OSC1, and communication may be processed in the main program. In this case, when the processing that does not require the oscillation frequency accuracy is completed, it is confirmed whether or not the communication request has been processed. Alternatively, when it is detected that the output OSCO1 of the ceramic oscillation circuit OSC1 is stable at the time when the communication request is received and the communication processing has not been completed, an interrupt signal for executing dedicated communication is generated. A program corresponding to the interrupt signal may be described.

  Considering the situation described in conjunction with FIG. 13, it becomes possible to use the ceramic oscillation circuit OSC1 and the CR oscillation circuit CRO1 properly in the program situation by using the oscillation circuit 110 of FIG. The power consumption can be reduced by reducing the number of activations of the ceramic oscillation circuit OSC1.

  As described above, in this embodiment, the control register unit 13 for switching and controlling the oscillation circuit 110 can be set from the oscillation circuit 110 and the OSC1 stability flag OSF indicating that the output of the ceramic oscillation circuit OSC1 is stabilized. Can be referred to from the software of the MCU 1, it becomes possible to determine whether or not the output of the ceramic oscillation circuit OSC 1 is stabilized by the software. Further, the control register unit 13 is provided with an OSC1 interrupt flag OSIF that can be set from the oscillation circuit 110 and can be referred to from the MCU1 software, and can be set from the MCU1 software, and the OSC1 interrupt flag OSIF. By setting the OSC1 stable interrupt permission bit OSFIE for allowing an interrupt when the signal is set and the OSC stable interrupt signal IRQOSC generated when the output of the ceramic oscillation circuit OS1 is stabilized, the output of the ceramic oscillation circuit OSC1 is set. When stable, the OSC1 stable interrupt signal IRQOSC can be generated.

  Further, the control register unit 13 is provided with an OSC1 selection bit SOS1 that can be set from the MCU1 software and explicitly switches the oscillation circuit 110 from the CR oscillation circuit CRO1 to the ceramic oscillation circuit OSC1, and this OSC1 selection bit SOS1 is provided in the interrupt program. By setting, the clock CKO of MCU1 can be switched from the output of CR oscillation circuit CRO1 to the output of ceramic oscillation circuit OSC1 by software. Further, by providing the OSC1 selection bit SOS1, the operation of the CR oscillation circuit CRO1 can be stopped after the clock CKO is switched from the output of the CR oscillation circuit CRO1 to the output of the ceramic oscillation circuit OSC1.

  If the output of the ceramic oscillation circuit OSC1 is not used by providing the control register unit 13 with the OSC1 activation inhibition bit IHOS1 that can be set from the software of the MCU1 and inhibits the activation of the ceramic oscillation circuit OSC1, the ceramic oscillation circuit The activation of the circuit OSC1 can be suppressed.

  By providing the control register unit 13 as described above, a mode in which the output OSCO2 of the CR oscillation circuit CRO1 and the output OSCO1 of the ceramic oscillation circuit OSC1 are switched and used, and only the output OSCO2 of the CR oscillation circuit CRO1 is used. It is possible to select a mode in which the OSC 1 is not activated. When only the CR oscillation circuit CRO1 is used, it is possible to reduce the power consumption of the entire MCU 1 by not activating the ceramic oscillation circuit OSC1.

In addition, this invention also includes the invention attached to the following.
(Appendix 1)
A first oscillation circuit;
A second oscillation circuit having an oscillation stabilization time longer than that of the first oscillation circuit;
A signal generation circuit that outputs a stability signal indicating the lapse of the oscillation stabilization time of the second oscillation circuit;
A switch circuit that selectively outputs one of the outputs of the first and second oscillation circuits based on a selection signal;
A suppression circuit that suppresses activation of the second oscillation circuit based on a suppression signal;
A mode in which the first and second oscillating circuits are simultaneously activated and the switch circuit selects and outputs the output of the first oscillating circuit and then is switched to the output of the second oscillating circuit;
A mode in which the first oscillation circuit is activated, the second oscillation circuit is not activated by the suppression circuit, and only the output of the first oscillation circuit is selectively output by the switch circuit. Oscillator circuit to perform.
(Appendix 2)
The oscillation circuit according to appendix 1, wherein the signal generation circuit counts the output of the first oscillation circuit to generate the stable signal.
(Appendix 3)
The oscillation circuit according to appendix 1 or 2, wherein the first oscillation circuit comprises a CR oscillation circuit, and the second oscillation circuit comprises a crystal oscillation circuit or a ceramic oscillation circuit.
(Appendix 4)
The stability signal is set so that it can be referred to by the software of the MCU from the signal generation circuit, and further includes a control register unit in which the selection signal and the suppression signal are set by the software 4. The oscillation circuit according to any one of 3.
(Appendix 5)
A first oscillation circuit;
A second oscillation circuit having an oscillation stabilization time longer than that of the first oscillation circuit;
A control register unit that can set information from outside and can refer to information set from outside,
A signal generation circuit that outputs a stability flag indicating the lapse of the oscillation stabilization time of the second oscillation circuit and sets it in the control register unit;
A switch circuit that selectively outputs one of the outputs of the first and second oscillation circuits based on a selection bit set in the control register unit;
A first mode in which the first and second oscillating circuits are activated simultaneously and the switch circuit selects and outputs the output of the first oscillating circuit and then is switched to the output of the second oscillating circuit; An oscillation circuit characterized by.
(Appendix 6)
A suppression circuit that suppresses activation of the second oscillation circuit based on a suppression signal set in the control register unit;
A second mode in which the first oscillation circuit is activated, the second oscillation circuit is not activated by the suppression circuit, and only the output of the first oscillation circuit is selectively output by the switch circuit; The oscillation circuit according to appendix 5, which is characterized.
(Appendix 7)
The control register unit sets an interrupt flag for generating an interrupt signal to the outside from the signal generation circuit, and sets a bit for permitting an interrupt when the interrupt flag is set from the outside. The oscillation circuit according to appendix 6, wherein an interrupt signal is generated after the oscillation stabilization time of the second oscillation circuit has elapsed.
(Appendix 8)
A semiconductor device including a clock generation circuit, a control register unit, and a CPU,
The clock generation circuit can set information from the first oscillation circuit, the second oscillation circuit having an oscillation stabilization time longer than that of the first oscillation circuit, and software of the CPU and is set by the software. A control register unit that can refer to the information stored therein, a signal generation circuit that outputs a stability flag indicating the lapse of the oscillation stabilization time of the second oscillation circuit and sets the control register unit, and a setting in the control register unit A switching circuit that selectively outputs one of the outputs of the first and second oscillation circuits based on the selected bit.
After powering on the semiconductor device, after resetting or returning from the standby state to the operating state, the first and second oscillation circuits are activated simultaneously, and the output of the first oscillation circuit is selected and output by the switch circuit. A semiconductor device having a first mode that is switched to the output of the second oscillation circuit after being turned on.
(Appendix 9)
The clock generation circuit further includes a suppression circuit that suppresses activation of the second oscillation circuit based on a suppression signal set in the control register unit,
In the semiconductor device, the first oscillation circuit is activated, the second oscillation circuit is not activated by the suppression circuit, and only the output of the first oscillation circuit is selectively output by the switch circuit. 9. The semiconductor device according to appendix 8, which has a mode.
(Appendix 10)
The control register unit has an interrupt flag for generating an interrupt signal for the software set from the signal generation circuit, and a bit for permitting an interrupt to the software when the interrupt flag is set. The semiconductor device according to appendix 9, wherein the semiconductor device is set by the software and generates an interrupt signal after an elapse of a stable oscillation time of the second oscillation circuit.
(Appendix 11)
11. The semiconductor device according to claim 8, wherein an output of the switch circuit is supplied to the CPU as a clock.
(Appendix 12)
12. The semiconductor device according to appendix 11, wherein the control register unit constitutes a part of the clock generation circuit.

  While the present invention has been described with reference to the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments, and various modifications and improvements can be made within the scope of the present invention.

It is an example of the oscillation circuit which combined the conventional CR oscillation circuit and the ceramic oscillation circuit. It is an example of an operation waveform of the circuit of FIG. It is a block diagram which shows one Example of this invention. It is a circuit diagram which shows the structure of an oscillation circuit with a control register part. 3 is a timing chart for explaining the operation of the oscillation circuit. It is a flowchart explaining operation | movement of an oscillation circuit. It is a flowchart explaining operation | movement of an oscillation circuit. 3 is a timing chart for explaining the operation of the oscillation circuit. It is a circuit diagram which shows an example of a structure of CR oscillation circuit. 6 is a timing chart for explaining the operation of the CR oscillation circuit. It is a circuit diagram which shows an example of a structure of a switch circuit. 6 is a timing chart for explaining the operation of the switch circuit. It is a flowchart explaining the process of an oscillation circuit.

Explanation of symbols

1 MCU
11 Clock generation circuit 12 CPU
13 register unit 110 oscillation circuit CRO1 CR oscillation circuit OSC1 ceramic oscillation circuit

Claims (5)

A first oscillation circuit;
A second oscillation circuit having an oscillation stabilization time longer than that of the first oscillation circuit;
A signal generation circuit that outputs a stability signal indicating the lapse of the oscillation stabilization time of the second oscillation circuit;
A switch circuit that selectively outputs one of the outputs of the first and second oscillation circuits based on a selection signal;
A suppression circuit that suppresses activation of the second oscillation circuit based on a suppression signal;
A mode in which the first and second oscillating circuits are simultaneously activated and the switch circuit selects and outputs the output of the first oscillating circuit and then is switched to the output of the second oscillating circuit;
A mode in which the first oscillation circuit is activated, the second oscillation circuit is not activated by the suppression circuit, and only the output of the first oscillation circuit is selectively output by the switch circuit. Oscillator circuit to perform. A first oscillation circuit;
A second oscillation circuit having an oscillation stabilization time longer than that of the first oscillation circuit;
A control register unit that can set information from outside and can refer to information set from outside,
A signal generation circuit that outputs a stability flag indicating the lapse of the oscillation stabilization time of the second oscillation circuit and sets it in the control register unit;
A switch circuit that selectively outputs one of the outputs of the first and second oscillation circuits based on a selection bit set in the control register unit;
A first mode in which the first and second oscillating circuits are activated simultaneously and the switch circuit selects and outputs the output of the first oscillating circuit and then is switched to the output of the second oscillating circuit; An oscillation circuit characterized by. A suppression circuit that suppresses activation of the second oscillation circuit based on a suppression signal set in the control register unit;
A second mode in which the first oscillation circuit is activated, the second oscillation circuit is not activated by the suppression circuit, and only the output of the first oscillation circuit is selectively output by the switch circuit; The oscillation circuit according to claim 2.   The control register unit sets an interrupt flag for generating an interrupt signal to the outside from the signal generation circuit, and sets a bit for permitting an interrupt when the interrupt flag is set from the outside. 4. The oscillation circuit according to claim 3, wherein an interrupt signal is generated after the oscillation stabilization time of the second oscillation circuit has elapsed. A semiconductor device including a clock generation circuit, a control register unit, and a CPU,
The clock generation circuit can set information from the first oscillation circuit, the second oscillation circuit having an oscillation stabilization time longer than that of the first oscillation circuit, and software of the CPU and is set by the software. A control register unit that can refer to the information stored therein, a signal generation circuit that outputs a stability flag indicating the lapse of the oscillation stabilization time of the second oscillation circuit and sets the control register unit, and a setting in the control register unit A switching circuit that selectively outputs one of the outputs of the first and second oscillation circuits based on the selected bit.
After powering on the semiconductor device, after resetting or returning from the standby state to the operating state, the first and second oscillation circuits are activated simultaneously, and the output of the first oscillation circuit is selected and output by the switch circuit. A semiconductor device having a first mode that is switched to the output of the second oscillation circuit after being turned on.

Images