JP2007140878A - System clock generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide stable operation in restarting in a microcomputer having a plurality of oscillators built therein. <P>SOLUTION: The system clock generation circuit has: a system clock selection signal for selecting a system clock from a plurality of clock signals; an operating state setting register 15 for storing a desired operating state by a write signal and outputting the system clock selection signal on the basis of the stored operating state; and an operating state maintenance register 16 for maintaining the operating state stored in the operating state setting register 15 and outputting the maintained operating state to the operating state setting register 15 so that the system clock selection signal is not initialized when a reset signal is inputted. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a system clock generation circuit, and more particularly to a system clock generation circuit in a microcomputer incorporating a plurality of oscillators.

  Portable devices typified by mobile phones and digital cameras rely on batteries for their power sources, and it is required to reduce current consumption as much as possible in order to ensure the usable time of the devices. A microcomputer intended to be incorporated in such a portable device has a low-speed operation mode that operates at a lower frequency in addition to a normal high-speed operation mode in order to reduce current consumption. These operation modes are changed by setting an operation mode flag in a register for setting an operation state (see, for example, “Patent Document 1”).

  FIG. 3 is a circuit block diagram showing a conventional system clock generation circuit in a microcomputer incorporating an oscillator. As shown in FIG. 3, the conventional system clock generation circuit includes a clock generation unit 33 including a high-speed oscillator 31 and a low-speed oscillator 32, and a selector 34 that selects a clock signal from the clock generation unit 33 and outputs it as a system clock. And an operation state setting register 35 that outputs an operation state by a write signal and outputs a high-speed oscillation control signal, a low-speed oscillation control signal, and a system clock selection signal according to the value of the operation mode flag. The conventional system clock generation circuit outputs the high-speed clock from the high-speed oscillator 31 as the system clock and stops the low-speed oscillator 32 if the operation mode flag indicates high-speed operation. If the operation mode flag indicates low speed operation, the system clock generation circuit outputs the low speed clock from the low speed oscillator 32 as the system clock and stops the high speed oscillator 31.

  By the way, in the microcomputer incorporating such a conventional system clock generation circuit, the operation state setting register 35 is configured to select the high-speed oscillator 31 in the initial state. For this reason, when the reset signal is input to the microcomputer, the operation state setting register 35 is initialized, and the microcomputer is restarted in the high-speed operation mode in which the microcomputer 31 operates.

However, when the reset signal is input, if the microcomputer is in the low-speed operation mode in which the microcomputer operates with the low-speed oscillator 32 to suppress current consumption, the oscillation operation of the restarted high-speed oscillator 31 is immediately stabilized. Thus, there is a problem that the abnormal oscillation state occurs, the synchronous reset release signal is not normally received, and the microcomputer malfunctions.
Japanese Patent Laying-Open No. 2004-13337 (FIG. 1)

  The present invention provides a system clock generation circuit capable of ensuring a stable operation at the time of restart in a microcomputer incorporating a plurality of oscillators.

  According to one aspect of the present invention, a desired operation state is stored by a selection signal for selecting a system clock from a plurality of clock signals and a write signal, and the selection signal is output based on the stored operation state The first storage means to be stored and the operation state stored in the first storage means so that the selection signal is not initialized when a reset signal is input. There is provided a system clock generation circuit comprising second storage means for outputting the state to the first storage means.

  According to the present invention, the microcomputer is restarted by the clock signal of the selected oscillator, so that stable operation of the microcomputer can be ensured.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit block diagram showing a system clock generation circuit according to Embodiment 1 of the present invention. Here, the part mainly related to the reset operation when an internal factor reset, for example, a watchdog timer reset, an address trap reset, an undefined instruction execution reset, or the like is input as a reset signal is shown.

  The system clock generation circuit according to the first embodiment of the present invention includes a clock generation unit 13 including a high-speed oscillator 11 and a low-speed oscillator 12, a selector 14 that selects a clock signal from the clock generation unit 13, a clock generation unit 13, and a selector 14. An operation state setting register 15 to be controlled, an operation state holding register 16 for holding a state before a reset signal is input, and a bidirectional bus 17 for connecting the operation state setting register 15 and the operation state holding register 16 are provided.

  A high-speed oscillation control signal from the operation state setting register 15 is input to the control signal input of the high-speed oscillator 11, and the output of the high-speed oscillator 11 is supplied to the first input of the selector 14 as a high-speed clock.

  The control signal input of the low-speed oscillator 12 is input with the low-speed oscillation control signal from the operation state setting register 15, and the output of the low-speed oscillator 12 is supplied to the second input of the selector 14 as a low-speed clock.

  A system clock selection signal from the operation state setting register 15 is input to the control signal input of the selector 14, and the output of the selector 14 is another circuit block (not shown) of the microcomputer (hereinafter referred to as “system”) as a system clock. Not supplied).

  A write signal is input to the control signal input of the operation state setting register 15, and the data input / output of the operation state setting register 15 is connected to the bidirectional bus 17.

  A write signal is input to the first control signal input of the operation state holding register 16, a reset signal is input to the second control signal input, and the data input / output of the operation state holding register 16 is connected to the bidirectional bus 17. Has been.

  Based on the high-speed oscillation control signal from the operation state setting register 15, the high-speed oscillator 11 generates a high-speed clock that the system uses in normal operation (hereinafter referred to as “high-speed operation mode”), and outputs the high-speed clock to the selector 14.

  That is, when the high-speed oscillation control signal is “1” (operation), the high-speed oscillator 11 outputs a high-speed clock, and when the high-speed oscillation control signal is “0” (stop), the high-speed oscillator 11 stops the oscillation operation. To do.

  The low-speed oscillator 12 uses a low-speed clock to be used when the system operates at a low speed to suppress current consumption (hereinafter referred to as “low-speed operation mode”) based on the low-speed oscillation control signal from the operation state setting register 15. Generate and output to the selector 14.

  That is, when the low-speed oscillation control signal is “1” (operation), the low-speed oscillator 12 outputs a low-speed clock, and when the low-speed oscillation control signal is “0” (stop), the low-speed oscillator 12 stops the oscillation operation. To do.

  The selector 14 selects a high-speed clock or a low-speed clock from the clock generation unit 13 based on the system clock selection signal from the operation state setting register 15, and outputs this as the system clock.

  That is, if the system clock selection signal is “high-speed clock”, the selector 14 selects the high-speed clock from the high-speed oscillator 11, and if the system clock selection signal is “low-speed clock”, the selector 14 receives from the low-speed oscillator 12. Select a low-speed clock.

  The operation state setting register 15 is a multi-bit register that stores a set value indicating the internal state of the system (hereinafter referred to as “operation state”), and is set to the value of an operation mode flag that is one of the operation states. Based on this, a system clock selection signal is output to the selector 14.

  That is, if the stored operation mode flag is “1” (high-speed operation mode), the operation state setting register 15 outputs “high-speed clock” as the system clock selection signal, and the stored operation mode flag is “0”. In the case of (low speed operation mode), the operation state setting register 15 outputs “low speed clock” as the system clock selection signal.

  The operation state setting register 15 outputs a high-speed oscillation control signal to the high-speed oscillator 11 and outputs a low-speed oscillation control signal to the low-speed oscillator 12 based on the value of the operation mode flag.

  That is, if the stored operation mode flag is “1”, the operation state setting register 15 outputs “1” as the high-speed oscillation control signal and “0” as the low-speed oscillation control signal. If the stored operation mode flag is “0”, the operation state setting register 15 outputs “0” as the high-speed oscillation control signal and “1” as the low-speed oscillation control signal.

  The operation state is written into the operation state setting register 15 by a write signal. When the entire system is reset upon power-on or external reset, the operation state setting register 15 is initialized, the operation state is cleared to a predetermined initial state, and the operation mode flag is set to “1”. Reset.

  The operation state holding register 16 is configured by a register having the same number of bits as the operation state setting register 15. The operation state holding register 16 stores the operation state transferred from the operation state setting register 15 via the bidirectional bus 17 by a write signal.

  When the operation state holding register 16 receives an internal factor reset as a reset signal, the operation state holding register 16 outputs the held operation state to the bidirectional bus 17 and transfers it to the operation state setting register 15.

  Next, the operation of the system clock generation circuit having the above configuration will be described. Here, as an example, a case where a reset signal is input when the system is operating in the low-speed operation mode in order to suppress current consumption will be described.

  First, when the low-speed operation mode is set as the operation state in the operation state setting register 15 by the write signal, the operation state is also written to the operation state holding register 16 via the bidirectional bus 17 and saved.

  At this time, since the system clock selection signal from the operation state setting register 15 is a “low-speed clock” indicating the low-speed operation mode, the low-speed clock output from the low-speed oscillator 12 is selected by the selector 14 and is output as the system clock. . Thus, the system starts operating in a low-speed operation mode with reduced current consumption.

  Next, when an internal factor reset is input to the operation state holding register 16 as a reset signal in this state, the saved operation state is transferred to the operation state setting register 15 via the bidirectional bus 17.

  The operation state setting register 15 is set to the same operation state as before the internal factor reset is input, and the selector 14 selects and outputs the low speed clock from the low speed oscillator 12 in which the oscillation operation is stable.

  In this way, since the set value of the operation state setting register 15 is always saved in the operation state holding register 16, when the internal factor reset is accepted, the system is restarted with a stable system clock and performs stable operation. Can be secured.

  According to the first embodiment, since the restart is performed by the clock signal of the oscillator selected before the reset signal is input, it is possible to realize the system clock generation circuit that can ensure the stable operation of the system.

  FIG. 2 is a circuit block diagram showing a system clock generation circuit according to the second embodiment of the present invention. Here, as in the first embodiment, the part mainly related to the reset operation when the internal factor reset is input as the reset signal is shown.

  The system clock generation circuit according to the second embodiment of the present invention includes a clock generation unit 23 including a high-speed oscillator 21 and a low-speed oscillator 22, a selector 24 that selects a clock signal from the clock generation unit 23, a clock generation unit 23, and a selector 24. An operation state setting register 25 for controlling, an operation state holding EEPROM 26 for holding a state before a reset signal is input, an operation state saving / setting control circuit 27 for controlling the operation state holding EEPROM 26, and an operation state setting register 25 and an operation state holding EEPROM 26; The bidirectional bus 28 is connected.

  A high-speed oscillation control signal from the operation state setting register 25 is input to the control signal input of the high-speed oscillator 21, and the output of the high-speed oscillator 21 is supplied to the first input of the selector 24 as a high-speed clock.

  The control signal input of the low-speed oscillator 22 is supplied with a low-speed oscillation control signal from the operation state setting register 25, and the output of the low-speed oscillator 22 is supplied to the second input of the selector 24 as a low-speed clock.

  The system clock selection signal from the operation state setting register 25 is input to the control signal input of the selector 24, and the output of the selector 24 is another circuit block (not shown) of the microcomputer (hereinafter referred to as “system”) as the system clock. Not supplied).

  A write signal is input to the control signal input of the operation state setting register 25, and the data input / output of the operation state setting register 25 is connected to the bidirectional bus 28.

  A control signal from the operation state saving / setting control circuit 27 is input to the control signal input of the operation state holding EEPROM 26, and data input / output of the operation state holding EEPROM 26 is connected to the bidirectional bus 28.

  A write signal is input to the first control signal input of the operation state saving / setting control circuit 27, and a reset signal is input to the second control signal input.

  Since the configurations, operations, and functions of the high-speed oscillator 21, the low-speed oscillator 22, the selector 24, and the operation state setting register 25 are the same as those in the first embodiment, detailed description thereof is omitted.

  The operation state holding EEPROM 26 is an electrically rewritable nonvolatile memory, and the operation received from the operation state setting register 25 via the bidirectional bus 28 based on a control signal from the operation state saving / setting control circuit 27. Remember state.

  The operation state holding EEPROM 26 transfers the held operation state to the operation state holding EEPROM 26 based on the control signal.

  The operation state saving / setting control circuit 27 generates and outputs a control signal for controlling the operation state holding EEPROM 26 based on the write signal and the reset signal.

  That is, the operation state saving / setting control circuit 27 stores the operation state transferred from the operation state setting register 25 in the operation state holding EEPROM 26 by the write signal in order to save the current operation state. Is generated.

  When the operation state saving / setting control circuit 27 receives an internal factor reset as a reset signal, the operation state holding EEPROM 26 holds the operation state of the operation state setting register 25 to return to the state before the reset signal is input. A control signal is generated so as to transfer the selected operation state to the operation state setting register 25.

  Next, the operation of the system clock generation circuit having the above configuration will be described. Here, as an example, a case where a reset signal is input when the system is operating in the low-speed operation mode in order to suppress current consumption will be described.

  First, when the low-speed operation mode is set as the operation state in the operation state setting register 25 by the write signal, the operation state is written and saved in the operation state holding EEPROM 26 via the bidirectional bus 28.

  At this time, since the system clock selection signal from the operation state setting register 25 is a “low speed clock” indicating the low speed operation mode, the low speed clock that is the output of the low speed oscillator 22 is selected by the selector 24 and output as the system clock. . Thus, the system starts operating in a low-speed operation mode with reduced current consumption.

  Next, when an internal factor reset is input to the operation state saving / setting control circuit 27 as a reset signal in this state, the operation state saved in the operation state holding EEPROM 26 is set via the bidirectional bus 28 to the operation state setting. Transferred to the register 25.

  The operation state setting register 25 is set to the same operation state as before the internal factor reset is input, and the selector 24 selects and outputs the low-speed clock from the low-speed oscillator 22 in which the oscillation operation is stable.

  In this way, the set value of the operation state setting register 25 is always saved in the operation state holding EEPROM 26. Therefore, when an internal factor reset is accepted, the system is restarted with a stable system clock to ensure stable operation. can do.

  According to the second embodiment, since the restart is performed by the clock signal of the oscillator selected before the reset signal is input, it is possible to realize the system clock generation circuit that can ensure the stable operation of the system.

  In the second embodiment, the internal factor reset is input to the operation state saving / setting control circuit 27 as the reset signal. However, the present invention is not limited to this, and for example, a part of the external reset is used as the reset signal. By inputting the power, the system can be restarted in the operation state immediately before the power is turned off when the power is turned on again.

  In the first embodiment and the second embodiment described above, for ease of explanation, the clock generator is composed of two, a high-speed oscillator and a low-speed oscillator. However, the present invention is not limited to this, and three clock generators are provided. The present invention can also be configured so as to be applicable to a clock generator composed of the above oscillators.

1 is a circuit block diagram showing a system clock generation circuit according to Embodiment 1 of the present invention. The circuit block diagram which shows the system clock generation circuit concerning Example 2 of this invention. 1 is a circuit block diagram showing a conventional system clock generation circuit in a microcomputer incorporating an oscillator.

Explanation of symbols

11, 21 High-speed oscillator 12, 22 Low-speed oscillator 13, 23 Clock generator 14, 24 Selector 15, 25 Operation state setting register 16 Operation state holding register 17, 28 Bidirectional bus 26 Operation state holding EEPROM
27 Operation state saving / setting control circuit

Claims (3)

A selection signal for selecting a system clock from a plurality of clock signals;
A first storage means for storing a desired operating state by a write signal and outputting the selection signal based on the stored operating state;
The operation state stored in the first storage means is held, and the held operation state is stored in the first storage means so that the selection signal is not initialized when a reset signal is input. A system clock generation circuit comprising second storage means for outputting. The second storage means is
An electrically rewritable nonvolatile memory in which the operating state is stored;
Control means operable to write the operation state to the nonvolatile memory by the write signal, read the operation state held in the nonvolatile memory by the reset signal, and output the read operation state to the first storage means. The system clock generation circuit according to claim 1. Clock generating means for generating first and second clock signals having different frequencies based on an oscillation control signal from the first storage means;
2. The system clock generation circuit according to claim 1, further comprising selection means for selecting the first or second clock signal based on the selection signal and outputting it as a system clock.

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