JP2002328912A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer capable of reducing consumed current in writing in an electrically writable nonvolatile memory. SOLUTION: A CPU waits for a predetermined time (e.g. 5. 6 ms) while writing to a flash EEPROM 2 is performed by a control logic 61 (a page load), during which time it controls a CR clock dividing circuit 72 and shifts an operation clock from a high speed operation clock to a low speed operation clock of a lower frequency. In this way, while the CPU 3 is waiting at the time of the page load, the clock is operated at a low speed, holding down a waste of current consumed by the CPU 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a microcomputer,
More specifically, the present invention relates to a microcomputer having a nonvolatile memory capable of electrically writing desired information.

[0002]

2. Description of the Related Art At present, an electrically writable non-volatile memory such as an EEPROM or a flash memory in which desired information can be electrically written and erased and data stored in the non-volatile memory without using a hardware, that is, without using a program. 2. Description of the Related Art Microcomputers incorporating a writing circuit for writing have been put to practical use.

A CP in such a microcomputer
Some U (control circuits) enter a wait state (wait state) while a write circuit for writing in hardware is operating, that is, while data is being written to the nonvolatile memory.

[0004]

While the write circuit is operating, that is, while data is being written to the nonvolatile memory, the CPU (control circuit) in the microcomputer which is in a wait state (wait state) is: During this time, the need to operate at high speed is extremely low.

[0005] However, the CPU in the conventional microcomputer still operates at the same high-speed operation clock as during normal operation. In other words, the operation clock is used faster than necessary even in the wait state (wait state). Use of the operation clock faster than necessary wastes unnecessary current consumption. Had the problem of being

Further, since a large amount of current is consumed when data is written to the nonvolatile memory, a CPU (control circuit) in a microcomputer which does not enter a wait state (wait state) while the write circuit is operating is usually used. However, if the microcomputer operates at the same high-speed operation clock as that of the microcomputer, the current consumption of the microcomputer as a whole increases. Further, there is a problem in that the power supply voltage is reduced due to the increase in current consumption, the voltage required for writing is reduced, and data may be erroneously written in the nonvolatile memory.

SUMMARY OF THE INVENTION An object of the present invention is to reduce current consumption when writing to an electrically writable nonvolatile memory,
Another object of the present invention is to provide a microcomputer capable of preventing erroneous writing of data.

[0008]

According to the present invention, a nonvolatile memory capable of electrically writing desired information, a write circuit for writing desired information to the nonvolatile memory, and an operation clock having a different frequency are output. An operation clock output unit,
A control circuit that operates based on the operation clock and reduces current consumption when the frequency of the operation clock decreases.The control circuit operates at a frequency lower than a predetermined frequency while the write circuit operates. It is configured to operate with the above operation clock. According to such a configuration, while the write circuit is operating, the control circuit operates with an operation clock having a frequency lower than the predetermined frequency.
The current consumption of the control circuit at the time of writing to the nonvolatile memory can be reduced, and power can be saved.

[0009] The storage device further includes a storage circuit in which desired information to be written to the nonvolatile memory is written by the control circuit before the desired information is written to the nonvolatile memory, wherein the write circuit stores the desired information stored in the storage circuit. Writing the information into the non-volatile memory, wherein the control circuit has a frequency lower than the frequency of the operation clock used while writing the desired information to the storage circuit while the write circuit is operating. It is configured to operate with the operation clock. According to such a configuration,
The control circuit operates with the operation clock having a lower frequency than the frequency of the operation clock used while writing desired information to the storage circuit while the write circuit is operating.
Writing to the storage circuit can be performed at high speed, and current consumption of the control circuit at the time of writing to the nonvolatile memory can be reduced.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below based on an embodiment shown in the drawings.

In FIG. 1, a one-chip microcomputer 1 includes a flash EEPROM 2 as an electrically writable nonvolatile memory and a CPU as a control circuit.
3, an address buffer and a latch circuit as a storage circuit (hereinafter, referred to as an "address buffer") 4, an I / O buffer and a data latch circuit as a storage circuit (hereinafter, referred to as a "data buffer") 5, a write circuit 6, and a CP
An operation clock output unit 7 for outputting an operation clock of U3,
A RAM 8, an address bus 9 and a data bus 10 are provided for storing desired information (hereinafter referred to as "data") to be written into the flash EEPROM 2 input from the outside and addresses for designating an area for storing the data.

In this example, the flash EEPROM 2 is 1
A writing program in which writing is performed in units of one page with 28 bytes as one page is adopted, and a writing program storage area 2a in which a writing program is stored is provided. Note that the flash EEPROM 2 is not limited to the one in which writing is performed in units of one page with 128 bytes as one page, and the number of bytes in one page can be changed as appropriate. The CPU 3 increases the current consumption as the frequency of the operation clock increases, and controls various operations in accordance with a program or the like written in the flash EEPROM 2. The address buffer 4 stores the address of the flash EEPROM 2 stored in the RAM 8 under the control of the CPU 3. The data buffer 5 stores the flash EE stored in the RAM 8
Data to be written to the PROM 2 is stored under the control of the CPU 3. The write circuit 6 includes a control logic 61 and a decoder 62. The address of the flash EEPROM 2 stored in the address buffer 4 is decoded by the decoder 62, and is stored in the data buffer 5 in a storage area of the flash EEPROM 2 designated by the decoded address. The stored data is stored. The control logic 61 is, as described above, the flash EEPROM 2
In this case, data is written in a hardware manner, that is, without using a program. The operation clock output unit 7 includes a CR oscillation circuit 71 that outputs a basic clock and a CR clock frequency dividing circuit 72, and outputs operation clocks having different frequencies to the CPU 3 under the control of the CPU 3. CR oscillation circuit 71
Is connected to a resistor 11 for adjusting the oscillation frequency.
The oscillation circuit that outputs the basic clock is not limited to the CR oscillation circuit, but may be, for example, a crystal oscillation circuit or a ceramic oscillation circuit. RAM8 has flash EEP
A write program storage area 8a to which a write program stored in the write program storage area 2a of the ROM 2 is transferred, data to be written to the flash EEPROM 2, and a flash EEPROM corresponding to the data.
A write data storage area 8b for storing the address 2 is provided. 12 is a battery as a power supply, 13 is a booster circuit for boosting the battery voltage, and 14 is an input terminal.

[0013]

[Description of Operation] First, a normal application operation (program operation) different from writing to the flash EEPROM 2 will be described. When the microcomputer 1 is in the standby state, the operation clock output unit 7 does not output the operation clock, and the CPU 3 does not operate. At this time, the operating voltage of the microcomputer 1 is at the voltage level of the battery 12 (3 V).

When a start is input by a start input by any switch operation, the CR oscillation circuit 71 in the operation clock output section 7 starts oscillating, and the CR clock frequency dividing circuit 72 outputs a low-speed operation clock of a predetermined frequency to the CPU 3. I do. The CPU 3 operates according to the low-speed operation clock, and performs a startup process according to a startup operation program stored in the flash EEPROM 2. In this example, the operation of the CPU 3 using the low-speed operation clock is referred to as an operation in the CR low-speed mode.

The CPU 3 outputs a boosting clock to the boosting circuit 13 according to a start-up operation program, and the boosting circuit 13
To perform the boost operation. When the output of the booster circuit 13 is boosted to 5 V, the CPU 3 controls the CR clock frequency divider 72 to output a high-speed operation clock having a higher frequency than the low-speed operation clock. The CPU 3 starts operating by the high-speed operation clock, and performs an operation according to the read application (program) while reading out from the flash EEPROM 2 an application (program) corresponding to an operation of any switch to which a start input has been made.
In this example, the operation of the CPU 3 using the high-speed operation clock is referred to as an operation in the CR high-speed mode.

Here, the operation of the CPU 3 in the low-speed CR mode and the operation in the high-speed CR mode are compared.
In the CR low-speed mode, the current consumption of the CPU 3 is small, so that the operation can be performed even with the battery voltage, but the operation speed becomes slow.
In the CR high-speed mode, since the current consumption of the CPU 3 is large, a voltage higher than the battery voltage is required, and the operation speed is increased.

For example, in a microcomputer mounted on a camera, a period from an activation to a CR high-speed mode to a standby mode again (actual operation period) is as follows.
Maintain the CR high-speed mode. This is because the time during which the operation for actually moving the load is actually performed is about one to several seconds on the application of the camera, and the current consumption does not matter much even if the CR high-speed mode is maintained. Such a situation can occur not only in microcomputers mounted on cameras but also in microcomputers mounted on various devices.

However, when writing to an electrically writable nonvolatile memory, a larger amount of current is consumed than in a normal application operation (program operation).

Next, the operation at the time of writing will be described with reference to FIG.

When a write request signal (startup input) is input to the CPU 3 from a device (not shown) or the like, the CP
U3 is in CR high-speed mode and flash EEPROM
2, the write data input from the input terminal 14 is stored in the write data storage area 8b of the RAM 8 (step 2a). The write data input from the input terminal 14 includes data to be written to the flash EEPROM 2 and a flash EEPROM corresponding to the data.
EPROM 2 address.

When the writing of the write data to the RAM 8 is completed, the write program stored in the write program storage area 2a in the flash EEPROM 2 is written to the RA.
Copy (transfer) to the write program storage area 8a in M8 (step 2b).

When the copy (transfer) of the write program to the write program storage area 8a is completed, the CPU 3 switches the program operation from the flash EEPROM 2 to the write program storage area 8a (step 2).
c). This is because when the flash EEPROM 2 is operating, that is, when the CPU 3
Since the program cannot be written to the flash EEPROM 2 when the program is read from the
3 is to read the program from flash EEPROM 2
From the flash program to the write program storage area 8a in the RAM 8,
2 is an operation for enabling rewriting.

The CPU 3 controls the control logic 61 according to the write program written in the RAM 8.
(Step 2d), and the flash EEPROM stored in the write data storage area 8b in the RAM 8
Data to be written to the data buffer 5 and a flash EEPROM corresponding to the data.
2 is written into the address buffer 4 (step 2e). In this example, writing to the address buffer 4 and the data buffer 5 is called byte loading. In this example, since the flash EEPROM 2 which writes data in units of one page with 128 bytes as one page is used, data (information) of up to 128 bytes is stored in the data buffer 5 and the page address is stored in the address buffer 4. It is stored. At this time, the CPU 3
Since the operation is performed in the R high-speed mode, data (information) is stored in the data buffer 5 and the address buffer 4 at a high speed, and the writing time can be reduced. When one page of the flash EEPROM 2 has an information amount different from 128 bytes, it is desirable that the maximum value of data stored in the data buffer 5 be an information amount different from the 128 bytes.

When a predetermined time (for example, 200 μs) elapses after the byte loading is completed, the control logic 6
1 operates to write the data (information) stored in the data buffer 5 to the address of the flash EEPROM 2 designated by the address buffer 4 (step 2).
f). This operation is performed by the control logic 61 by hardware, is not controlled by software by a program, and is executed independently of the operation of the CPU 3.
In this example, writing to the flash EEPROM 2 by the control logic 61 is called page load.

The CPU 3 waits for a predetermined time (for example, 5.6 ms) while the page is being loaded by the control logic 61. During this wait, the CPU 3 controls the CR clock frequency dividing circuit 72 to switch from the CR high-speed mode to the CR high-speed mode.
The mode shifts to the low-speed mode (steps 2g and 2h). Thus, the wait period of the CPU 3 at the time of page loading is C
Since the low-speed mode is set, it is possible to suppress unnecessary current consumption by the CPU 3. Also, by suppressing the current consumption of the CPU 3, the flash EEPROM
The load on the power supply during writing to M2 can be reduced, and the flash EEP caused by the decrease in the power supply voltage can be reduced.
It is possible to reduce the probability of erroneous writing in the ROM 2.

After a lapse of a predetermined time (5.6 ms), C
PU3 determines that the page loading by the control logic 61 is completed, and controls the CR clock frequency dividing circuit 72 to switch from the CR low-speed mode to the CR high-speed mode.
Further, the operation is switched from the operation of reading the program from the RAM 8 to the operation of reading the program from the flash EEPROM 2, and the operation is terminated.

[0027]

According to the present invention, while the write circuit for writing desired information to the nonvolatile memory is operating, the control circuit operates with an operation clock having a frequency lower than the predetermined frequency. The current consumption of the control circuit at the time of writing to the memory can be reduced, and power saving can be achieved.

The control circuit operates with an operation clock having a frequency lower than the frequency of the operation clock used during writing of desired information to the storage circuit while the write circuit is operating. Can be performed at high speed, and current consumption of the control circuit at the time of writing to the nonvolatile memory can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of FIG. 1;

[Explanation of symbols]

 2 Electrically writable non-volatile memory 6 Write circuit 7 Operation clock output unit 3 Control circuit 4 Storage circuit 5 Storage circuit

 ────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kazuyuki Akiyama 1-1-1 Akanehama, Narashino-shi, Chiba F-term in Seiko Precision Co., Ltd. (Reference) 5B062 AA05 AA08 CC03 HH02 5B079 AA07 BA01 BC01

Claims (2)

[Claims] A nonvolatile memory capable of electrically writing desired information; a write circuit for writing desired information to the nonvolatile memory; an operation clock output unit for outputting an operation clock of a different frequency; A control circuit that operates based on a clock and reduces current consumption when the frequency of the operation clock decreases. The control circuit operates at a frequency lower than a predetermined frequency while the write circuit operates. A microcomputer which operates with a clock. 2. The storage circuit according to claim 1, further comprising a storage circuit to be written by the control circuit before desired information to be written to the non-volatile memory is written to the non-volatile memory, Writing the desired information stored in the non-volatile memory into the nonvolatile memory, and the control circuit controls the operation clock used while the desired information is written in the storage circuit while the write circuit is operating. A microcomputer which operates with the operation clock having a frequency lower than the frequency of the microcomputer.