JP6585977B2 - Semiconductor device and oscillation circuit control method - Google Patents

Description

  The present invention relates to a semiconductor device and an oscillation circuit control method.

  The following techniques are known as techniques related to an oscillation circuit using a crystal resonator. For example, Patent Document 1 discloses a crystal oscillator including a CMOS inverter, a resistor and a crystal oscillator, a MOS transistor inserted between a power supply voltage source and a crystal oscillator, and detecting an oscillation stop state in the crystal oscillator. An oscillation stop detector that outputs a control signal 1, detects an oscillation state in the crystal oscillator, outputs a second control signal, and controls the conduction state of the MOS transistor via the first and second control signals And a crystal oscillation circuit including the same.

  In Patent Document 2, an oscillator including a crystal resonator and an inverter connected in parallel and a current source that supplies current to the inverter is connected to a power source terminal of the current source and the inverter, and an output request signal is given. A predetermined voltage is applied to the power source terminal of the current source and the inverter by switching to the on state at a predetermined timing, and a predetermined voltage is applied to the power source terminal of the current source and the inverter by switching to the off state at the timing when the output stop signal is given. Is provided with a switch that limits the application of.

  In Patent Document 3, the oscillation operation of an external oscillation circuit that is externally attached is controlled by an oscillation stop signal, a control means for outputting a signal from the external oscillation circuit as a first clock signal, and a second clock signal are generated There is described a semiconductor device having oscillation means for output and selection means for selecting a first clock signal or a second clock signal based on a switching signal and outputting the selected clock signal as an internal clock signal.

  Patent Document 4 discloses a crystal oscillation circuit that forms a clock signal by an oscillation operation using a crystal resonator, a built-in oscillator that forms a clock signal having a frequency at which an internal circuit can operate normally, and a crystal oscillation circuit. Based on the detection result of the abnormal high-speed oscillation detection circuit and the abnormal high-speed oscillation detection circuit that can detect that the frequency of the formed clock signal is higher than the normal operation frequency range of the internal circuit, the crystal oscillation circuit There is described a semiconductor integrated circuit device including a control circuit for supplying a clock signal formed by a built-in oscillator to an internal circuit instead of the formed clock signal.

  Patent Document 5 describes a CMOS oscillator circuit in which an amplification gain in an inverter is variable by providing a plurality of different gain paths on each of a high potential side and a low potential side of an inverter connected in parallel to a crystal resonator. ing.

JP-A-6-216644 JP 2009-290380 A JP 2008-72383 A JP 2013-102371 A Japanese Patent Laid-Open No. 6-224637

  The oscillation margin, which is one of the important characteristics of the crystal oscillation circuit, represents the margin (margin) from when the oscillation signal output from the crystal oscillation circuit oscillates until it stops oscillating. This is an index indicating how much signal amplification capability the circuit side excluding the crystal resonator has relative to the resistance value (attenuation capability of the signal) of the crystal resonator. Theoretically, oscillation is possible if the oscillation margin is greater than 1. However, if the oscillation margin is close to 1, oscillation does not occur or the oscillation start time becomes abnormally long, and the set does not operate normally. There is a case. These oscillation failures can be improved by increasing the oscillation margin, but increasing the oscillation margin increases the circuit current. That is, the oscillation margin and the circuit current are in a trade-off relationship.

  The conventional crystal oscillation circuit has a problem that the oscillation stops due to temporary external factors such as noise and condensation on the printed circuit board. A possible countermeasure is to use the output signal of the built-in CR oscillation circuit in place of the output signal of the crystal oscillation circuit when oscillation stops in the crystal oscillation circuit. However, the accuracy of the oscillation frequency in the CR oscillation circuit is remarkably lower than the accuracy of the oscillation frequency in the crystal oscillation circuit, and in the system requiring high frequency accuracy such as UART (Universal Asynchronous Receiver-Transmitter), It is considered undesirable to apply

  The present invention has been made in view of the above points, and when the oscillation signal generated by the crystal oscillation circuit enters an oscillation stop state, the oscillation stop state is eliminated while minimizing an increase in circuit current. An object of the present invention is to provide a semiconductor device and an oscillation circuit control method that can be used.

A semiconductor device according to a first aspect of the present invention includes a current source capable of adjusting an output current, and an inverter connected to a crystal resonator and supplied with the output current of the current source. A first oscillation circuit for generating a signal, a detection circuit for detecting an oscillation stop of the first oscillation signal, and a second oscillation signal when an oscillation stop of the first oscillation signal is detected Based on the overflow signal, a counter that outputs an overflow signal when a count value obtained by counting the number of pulses of the second oscillation signal exceeds a predetermined value corresponding to a predetermined period, and A current control circuit for increasing an output current of the current source .

A method for controlling an oscillation circuit according to a second aspect of the present invention includes: a current source capable of adjusting an output current; and an inverter connected to a crystal resonator and supplied with the output current of the current source. The oscillation stop of the first oscillation signal output from the oscillation circuit is detected, and when the oscillation stop of the first oscillation signal is detected, a second oscillation signal is generated, and the second oscillation signal is generated. An overflow signal is output when the count value obtained by counting the number of pulses exceeds a predetermined value corresponding to a predetermined period, and the output current of the current source is increased based on the overflow signal .

  According to the present invention, when an oscillation signal generated by a crystal oscillation circuit is in an oscillation stop state, the semiconductor device and the oscillation circuit capable of eliminating the oscillation stop state while minimizing an increase in circuit current are minimized. A control method is provided.

It is a figure which shows the structure of the semiconductor device which concerns on embodiment of this invention. 3 is a timing chart showing the operation of the semiconductor device according to the embodiment of the present invention. It is a figure which shows the structure of the semiconductor device which concerns on other embodiment of this invention. It is a figure which shows the relationship between an oscillation margin and an oscillation start time.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or equivalent components and parts are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate.

[First embodiment]
FIG. 1 is a diagram showing a configuration of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a crystal oscillation circuit 10 including a crystal resonator 13 and capacitors Cd and Cg connected to the outside of the semiconductor device 100. One end of the crystal resonator 13 and the capacitor Cg are connected to the external connection terminal 31 of the semiconductor device 100, and the other end of the crystal resonator 13 and the one end of the capacitor Cd are connected to the external connection terminal 32 of the semiconductor device 100. .

  The crystal oscillation circuit 10 includes an inverter 12, a resistance element Rf, and a current source 11 as parts accommodated in the semiconductor device 100. The inverter 12 and the resistance element Rf are connected in parallel to the crystal resonator 13 via the external connection terminals 31 and 32. The output current I1 output from the current source 11 is supplied to the inverter 12. The current source 11 outputs an output current I1 having a magnitude corresponding to a trimming code value S6 supplied from a current control circuit 24 described later. That is, the output current I1 is variable. The oscillation margin of the crystal oscillation circuit 10 increases as the output current I1 of the current source 11 increases. The crystal oscillation circuit 10 outputs the first oscillation signal S1 from the output terminal of the inverter 12. The first oscillation signal S1 is input to one input terminal of the oscillation stop detection circuit 21 and the selector 26.

  The oscillation stop detection circuit 21 outputs a high-level detection signal S2 when the first oscillation signal S1 supplied from the crystal oscillation circuit 10 is in an oscillation stop state, and the first oscillation signal S1 is in an oscillation state. If it is, a low level detection signal S2 is output. Here, the first oscillation signal S1 being in the oscillation stop state includes a state where the first oscillation signal S1 is not oscillating and a case where the amplitude of the first oscillation signal S1 is smaller than a predetermined value. The detection signal S <b> 2 is supplied to the CR oscillation circuit 22, one input terminal of the AND circuit 25, and the counter 23. The oscillation stop detection circuit 21 once ends the oscillation stop state detection operation of the first oscillation signal S1 in response to the reset signal S7 supplied from the current control circuit 24, and then restarts the detection operation.

  The CR oscillation circuit 22 is an oscillation circuit including a resistance element and a capacitor. The CR oscillation circuit 22 outputs the second oscillation signal S3 while the high-level detection signal S2 indicating that the first oscillation signal S1 is in the oscillation stop state is input. The frequency of the second oscillation signal S3 is adjusted so as to substantially match the frequency of the first oscillation signal S1, but the frequency accuracy of the first oscillation signal S1 is greater than that of the second oscillation signal S3. Higher than. The second oscillation signal S3 is input to the other input terminal of the selector 26 and the counter 23.

  The counter 23 counts up the number of pulses of the second oscillation signal S3 while the detection signal S2 exhibits a high level indicating that the first oscillation signal S1 is in the oscillation stop state. The counter 23 outputs an overflow signal S4 when the count value of the number of pulses of the second oscillation signal S3 reaches a predetermined value. That is, the overflow signal S4 is output when the oscillation stop state of the oscillation signal S1 continues for a predetermined period. The counter 23 resets the count value according to the reset signal S7 supplied from the current control circuit 24, and outputs the overflow signal S4 every time the count value of the number of pulses of the second oscillation signal S3 after the reset exceeds a predetermined value. Output. The overflow signal S4 is supplied to the current control circuit 24.

  The current control circuit 24 outputs a trimming code value S6 that specifies the magnitude of the output current I1 of the current source 11. The current control circuit 24 increments the trimming code value S6 by one step each time the overflow signal S4 is output from the counter 23. Thereby, the output current I1 of the current source 11 increases stepwise. After incrementing the trimming code value S6, the current control circuit 24 supplies the reset signal S7 to the oscillation stop detection circuit 21 and the counter 23 to reset them. The current control circuit 24 can generate a value obtained by further incrementing the trimming code value that maximizes the output current I1 of the current source 11 as the maximum trimming code value. The current control circuit 24 supplies a limit notification signal S8 that transitions to a high level when the trimming code value becomes maximum to the other input terminal of the AND circuit 25.

  The AND circuit 25 outputs a logical product of the limit notification signal S8 and the detection signal S2 as the selection signal S9, and supplies the selection signal S9 to the selector 26. That is, the AND circuit 25 outputs the high-level selection signal S9 when the oscillation stop state of the first oscillation signal S1 continues even when the output current I1 of the current source 11 is maximized. On the other hand, the AND circuit 25 outputs a selection signal S9 having a low level when the first oscillation signal S1 is in an oscillation state.

  The selector 26 selects the first oscillation signal S1 input to one input terminal when the low-level selection signal S9 is input (that is, when the first oscillation signal S1 is in an oscillation state). This is output from the output end. On the other hand, the selector 26 receives the high-level selection signal S9 (that is, when the oscillation stop state of the first oscillation signal S1 continues even when the output current I1 of the current source 11 is maximized). The second oscillation signal S3 input to the other input terminal is selected and output from the output terminal. The first oscillation signal S <b> 1 and the second oscillation signal S <b> 3 that are selectively output from the selector 26 can be supplied to another circuit in the semiconductor device 100 or a circuit outside the semiconductor device 100.

  Hereinafter, the operation of the semiconductor device 100 will be described. FIG. 2 is a timing chart showing an example of the operation of the semiconductor device 100. In FIG. 2, in order from the top, the first oscillation signal S1, the detection signal S2, the second oscillation signal S3, the count value of the counter 23, the overflow signal S4, the trimming code value S6, the reset signal S7, and the current source 11 The output current I1 is shown.

  At time t1, when the first oscillation signal S1 output from the crystal oscillation circuit 10 is in an oscillation stop state, the oscillation stop detection circuit 21 outputs a high level detection signal S2. When the detection signal S2 transits to a high level, the CR oscillation circuit 22 starts operation and generates a second oscillation signal S3.

  The counter 23 counts up the number of pulses of the second oscillation signal S3 output from the CR oscillation circuit 22 while the detection signal S2 exhibits a high level indicating that the first oscillation signal S1 is in the oscillation stop state. . When the count value of the number of pulses of the second oscillation signal S3 reaches a predetermined value at time t2, the counter 23 outputs an overflow signal S4 and supplies it to the current control circuit 24.

  When receiving the overflow signal S4, the current control circuit 24 increments the trimming code value by one step from the initial value [A] to [A + 1]. Thereby, at time t3, the output current I1 of the current source 11 increases by one step. The current control circuit 24 increments the trimming code value, and then supplies the reset signal S7 to the oscillation stop detection circuit 21 and the counter 23.

  When receiving the reset signal S7, the oscillation stop detection circuit 21 once resets the oscillation stop state detection operation in the first oscillation signal S1. As a result, the detection signal S2 once transits to a low level. As a result, the CR oscillation circuit 22 temporarily stops the output of the second oscillation signal S3. Thereafter, the oscillation stop detection circuit 21 restarts the detection operation. Upon receiving the reset signal S7, the counter 23 resets the count value of the number of pulses of the second oscillation signal S3.

  As shown in FIG. 2, when the oscillation stop state continues in the oscillation signal S1 even after the output current I1 of the current source 11 is increased to a magnitude corresponding to the trimming code value [A + 1], The detection signal S2 changes to the high level again. Thereby, the second oscillation signal S3 is output from the CR oscillation circuit 22, and the counter 23 again counts the number of pulses of the second oscillation signal S3. When the count value of the counter 23 reaches a predetermined value again at time t4, the counter 23 outputs the overflow signal S4 again and supplies it to the current control circuit 24.

  When receiving the overflow signal S4 again, the current control circuit 24 increments the trimming code value by one step from [A + 1] to [A + 2]. Thereby, at time t5, the output current I1 of the current source 11 further increases by one step. The current control circuit 24 increments the trimming code value, and then supplies the reset signal S7 to the oscillation stop detection circuit 21 and the counter 23.

  As shown in FIG. 2, after the output current I1 of the current source 11 is increased to a magnitude corresponding to the trimming code value [A + 2], at time t6 before the count value of the counter 23 reaches a predetermined value, When the oscillation stop state of the oscillation signal S1 of 1 is canceled and the oscillation state is entered, the detection signal S2 transits to a low level, and the CR oscillation circuit 22 and the counter 23 stop its operation. In the current control circuit 24, the trimming code value [A + 2] is held. As a result, supply of a current having a magnitude corresponding to the trimming code value [A + 2] is maintained in the inverter 12 constituting the crystal oscillation circuit 10. When the detection signal S2 becomes low level, the selection signal S9 that is an output signal of the AND circuit 25 becomes low level, and the selector 26 selects and outputs the first oscillation signal S1 generated by the crystal oscillation circuit 10. .

  On the other hand, if the oscillation stop state of the first oscillation signal S1 is not canceled even after the output current I1 of the current source 11 has been increased to the maximum value of the adjustment range, the current control circuit 24 starts from the counter 23. Based on the output overflow signal S4, a value obtained by further incrementing the trimming code value by one step is generated as the maximum value of the trimming code value. The current control circuit 24 generates a limit notification signal S8 exhibiting a high level when the trimming code value becomes maximum, and supplies this to the AND circuit 25. As a result, the selection signal S9, which is the output signal of the AND circuit 25, goes to a high level, and the selector 26 selects and outputs the second oscillation signal S3 generated by the CR oscillation circuit 22.

  As described above, the semiconductor device 100 according to the embodiment of the present invention increases the output current I1 of the current source 11 when the oscillation stop state of the first oscillation signal S1 continues for a predetermined period. Further, after the output current I1 of the current source 11 is increased, the process of further increasing the output current I1 of the current source 11 is repeatedly performed when the oscillation stop state of the first oscillation signal S1 continues for a predetermined period. That is, the semiconductor device 100 attempts to eliminate the oscillation stop state by increasing the output current I1 of the current source 11 stepwise while the oscillation stop state of the first oscillation signal S1 continues.

  According to the semiconductor device 100 according to the embodiment of the present invention, even when the first oscillation signal S1 generated by the crystal oscillation circuit 10 is in an oscillation stop state due to external factors such as noise and substrate dew condensation, Since the output current I1 of the current source 11 is increased and the oscillation margin is automatically adjusted in the direction of increasing, the oscillation stop state can be automatically canceled. Therefore, the semiconductor device 100 according to the present embodiment can be applied to a system that requires high reliability.

  In addition, according to the semiconductor device 100 according to the embodiment of the present invention, the output current I1 of the current source 11 increases in a stepwise manner, so that the increase amount of the output current I1 is necessary for eliminating the oscillation stop state. The minimum increase can be suppressed. That is, according to the semiconductor device 100 according to the present embodiment, it is possible to eliminate the oscillation stop state in the first oscillation signal S1 while minimizing an increase in circuit current.

  Here, the oscillation margin of the crystal oscillation circuit is greatly affected by the type of capacitor constituting the crystal oscillation circuit, the capacitance of the printed circuit board on which the crystal oscillation circuit is mounted, the wiring pattern, and the like. For this reason, the oscillation margin set on the manufacturer side may not be reproduced on the user side. Therefore, when importance is attached to the reliability of the oscillation circuit, a countermeasure method can be considered in which the manufacturer sets the oscillation margin higher. However, in this case, the circuit current may exceed the standard value. Further, the user has repeatedly selected the capacitor and adjusted the wiring pattern of the printed circuit board so that a desired oscillation margin can be obtained.

  According to the semiconductor device 100 according to the present embodiment, even when the type of capacitor, the capacitance of the printed circuit board, the wiring pattern, and the like change, the output of the current source 11 is maintained so that the first oscillation signal S1 maintains the oscillation state. Since the current I1 is automatically adjusted, it is not necessary to take a measure such as setting the oscillation margin high, and an increase in circuit current can be suppressed. Further, according to the semiconductor device 100 according to the present embodiment, the oscillation margin is adaptively adjusted with respect to external factors, so that the selection of the capacitor and the adjustment of the wiring pattern of the printed circuit board are repeated many times. Work becomes unnecessary.

  In addition, the semiconductor device 100 according to the embodiment of the present invention incorporates the CR oscillation circuit 22, and after the output current I1 of the current source 11 is increased to the maximum value, the oscillation stop state of the first oscillation signal S1 is predetermined. When the period continues, the second oscillation signal S3 generated by the CR oscillation circuit 22 is output. On the other hand, the semiconductor device 100 includes the first oscillation signal before the output current I1 of the current source 11 is increased to the maximum value or before a predetermined period elapses after the output current I1 of the current source 11 is increased to the maximum value. When S1 enters the oscillation state, the first oscillation signal S1 generated by the crystal oscillation circuit 10 is output.

  That is, according to the semiconductor device 100 according to the present embodiment, when the oscillation stop state is not eliminated as a result of the attempt to eliminate the oscillation stop state in the first oscillation signal S1, the second oscillation signal by the CR oscillation circuit 22 is obtained. S3 is output. As described above, the second oscillation signal S3 generated by the CR oscillation circuit 22 is used supplementarily, so that the system can be prevented from being stopped. Further, the second oscillation signal S3 generated by the CR oscillation circuit 22 is output only when the oscillation stop state is not eliminated in the first oscillation signal S1, and therefore the first oscillation signal S1 is Compared with the case where the second oscillation signal S3 is immediately output when the oscillation is stopped, the usage rate of the first oscillation signal S1 with higher frequency accuracy can be increased.

[Second Embodiment]
FIG. 3 is a diagram showing a configuration of the semiconductor device 101 according to the second embodiment of the present invention. Semiconductor device 101 further includes a compare register 27 in which a value corresponding to a count value at which counter 23 outputs overflow signal S4 can be written and rewritten. That is, in the semiconductor device 101, the counter 23 outputs the overflow signal S4 when the count value of the number of pulses of the second oscillation signal S3 reaches the value written in the compare register 27. The relationship between the counter 23 and the compare register 27 is substantially the same as that of a compare match timer mounted on a general MCU.

  In the semiconductor device 101 according to the present embodiment, the trimming code value output from the current control circuit 24 can be set from the outside of the semiconductor device 101. That is, the magnitude of the output current I1 of the current source 11 can be set from the outside of the semiconductor device 101.

  For example, writing of values to the compare register 27, rewriting, and setting of trimming code values can be performed based on a command from the CPU 200 provided outside the semiconductor device 101. The compare register 27 can be connected to the CPU 200 via the external connection terminal 33 and the data bus 210. Similarly, the current control circuit 24 can be connected to the CPU 200 via the external connection terminal 34 and the data bus 210. The overflow signal S4 output from the counter 23 can be supplied to the CPU 200 via the external connection terminal 35 and the data bus 210.

  According to the semiconductor device 101 according to the present embodiment, when 1000 is written in the compare register 27, the counter 23 outputs the overflow signal S4 when the number of pulses of the second oscillation signal S3 is counted 1000. . That is, according to the semiconductor device 101 according to the present embodiment, the time until the overflow signal S4 is output after the first oscillation signal S1 is in the oscillation stop state and the output current I1 of the current source 11 are increased. It is possible to set an arbitrary time from the outside of the semiconductor device 101 until the overflow signal S4 is output from this time (hereinafter referred to as an overflow time).

  According to the semiconductor device 101 according to the present embodiment, the value written to the compare register 27 is sequentially changed while the output current I1 of the current source 11 is kept constant, and the overflow signal S4 is output for each written value. By monitoring whether or not, the oscillation start time in the first oscillation signal S1 can be estimated. Here, the oscillation start time is a time from when the crystal oscillation circuit 10 is activated or reset to when the amplitude of the first oscillation signal S1 reaches a predetermined value, as shown in FIG. For example, the overflow signal S4 is output when 1000 is written to the compare register 27 while the output current I1 of the current source 11 is kept constant, and the overflow signal S4 is not output when 1100 is written to the compare register 27. In this case, it can be estimated that the oscillation start time at the output current I1 in the crystal oscillation circuit 10 is a time between 1000 counts and 1100 counts.

  Here, it is known that the oscillation start time and the oscillation margin in the crystal oscillation circuit 10 have a correlation. For example, as shown in FIG. 4, the oscillation start time T1 when the oscillation margin is relatively small is longer than the oscillation start time T2 when the oscillation margin is relatively large. That is, according to the semiconductor device 101 according to the present embodiment, the oscillation margin is estimated from the oscillation start time estimated as described above by acquiring the relationship between the oscillation start time and the oscillation margin in advance. be able to.

  Further, according to the semiconductor device 101 according to the present embodiment, the overflow time can be set to an arbitrary value, so that the upper limit of the oscillation start time can be set on the user side. In other words, the lower limit of the oscillation margin of the crystal oscillation circuit 10 can be set on the user side by the value written to the compare register 27, and the convenience for the user can be improved. In addition, according to the semiconductor device 101 according to the present embodiment, the oscillation margin can be determined in consideration of the influence of the capacitors Cd and Cg and the wiring pattern of the printed circuit board, so that a desired oscillation margin can be obtained. In addition, the operation of repeatedly selecting parts and changing the wiring pattern is not necessary.

  The crystal oscillation circuit 10 is an example of a first oscillation circuit in the present invention. The circuit group including the oscillation stop detection circuit 21, the CR oscillation circuit 22, the counter 23, the current control circuit 24, the AND circuit 25, and the selector 26 is an example of the control circuit in the present invention. The oscillation stop detection circuit 21 is an example of a detection circuit in the present invention. The CR oscillation circuit 22 is an example of a second oscillation circuit in the present invention. The counter 23 is an example of a counter in the present invention. The current control circuit 24 is an example of a current control circuit in the present invention. The selector 26 is an example of a selector in the present invention. The compare register 27 is an example of a register in the present invention.

DESCRIPTION OF SYMBOLS 10 Crystal oscillation circuit 11 Current source 12 Inverter 13 Crystal oscillator 21 Oscillation stop detection circuit 22 CR oscillation circuit 23 Counter 24 Current control circuit 26 Selector 27 Compare register 100, 101 Semiconductor device

Claims (10)

A first oscillation circuit for generating a first oscillation signal, comprising: a current source capable of adjusting an output current; and an inverter connected to a crystal resonator and supplied with the output current of the current source;
A detection circuit for detecting oscillation stop of the first oscillation signal;
A second oscillation circuit that generates a second oscillation signal when oscillation stop of the first oscillation signal is detected;
A counter that outputs an overflow signal when a count value obtained by counting the number of pulses of the second oscillation signal exceeds a predetermined value corresponding to a predetermined period;
A current control circuit for increasing the output current of the current source based on the overflow signal;
A semiconductor device including: The counter resets the count value when the output current of the current source is increased, and outputs the overflow signal every time the count value after reset exceeds the predetermined value,
The semiconductor device according to claim 1 , wherein the current control circuit increases an output current of the current source every time the overflow signal is output.   A selector that selectively outputs one of the first oscillation signal and the second oscillation signal
  The semiconductor device according to claim 1, further comprising:   The selector outputs the second oscillation signal when the oscillation stop state of the first oscillation signal continues for the predetermined period after the output current of the current source is increased to the maximum value, and the current When the first oscillation signal is in an oscillation state before the output current of the source is increased to the maximum value or before the predetermined period elapses after the output current of the current source is increased to the maximum value. Output the first oscillation signal
  The semiconductor device according to claim 3. The current control circuit controls the output current of the current source by a command value incremented each time the overflow signal is output,
The semiconductor device according to claim 3 , wherein the selector selects and outputs the second oscillation signal when the command value becomes maximum. The semiconductor device according to claim 1 , wherein the second oscillation circuit is a CR oscillation circuit. The counter further includes a register capable of writing and rewriting a value corresponding to a count value for outputting the overflow signal,
The counter, the number of pulses of the count value of the second oscillation signal, when it reaches the value written in the register, to any one of claims 1 to 6 for outputting the overflow signal The semiconductor device described. And output current adjustable current source, an inverter output current of the connected and the current source to the crystal oscillator is supplied, the oscillation stop of the first oscillation signal outputted from the first oscillation circuit comprising Detect
A second oscillation signal is generated when an oscillation stop of the first oscillation signal is detected;
When the count value obtained by counting the number of pulses of the second oscillation signal exceeds a predetermined value corresponding to a predetermined period, an overflow signal is output,
An oscillation circuit control method for increasing an output current of the current source based on the overflow signal . After the output current of the current source is increased to the maximum value, if the oscillation stop state of the first oscillation signal continues for the predetermined period, the second oscillation signal is output, and the output current of the current source When the first oscillation signal enters an oscillation state before the predetermined period elapses after the output current of the current source is increased to the maximum value. Output signal
  The control method according to claim 8. The control method according to claim 8 or 9, wherein the predetermined period is variable.

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