JP3880395B2 - Arbitrary waveform generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an arbitrary waveform generator for generating a waveform by storing each data constituting a waveform at each address of a waveform memory and sequentially reading each data stored at each address.
[0002]
[Prior art]
Rather than using an analog signal generator, the user-specified waveform is generated by storing the user-specified waveform at each address in the waveform memory and sequentially reading each data. The method of obtaining the waveform can more accurately and easily realize the waveform specified by the user.
[0003]
An arbitrary waveform generator employing such a method is configured as shown in FIG. 7, for example.
[0004]
As shown in FIG. 8, each data of the target waveform 2 is stored in each address in the waveform memory 1. The address storage unit 3 stores the start address A of the waveform 2 in the waveform memory 1. _S And end address A _E Is stored. When the arbitrary waveform generator is activated, the start address A is read from the address storage unit 3. _S Is loaded into the address counter 4 and the end address A _E Is applied to the end address detector 5.
[0005]
The address counter 4 receives a start address A every time a clock c is input from the outside. _S Is increased or decreased by a predetermined number, and each address A increased or decreased by a predetermined number is sequentially applied to the waveform memory 1. Further, the address A output from the address counter 4 is also input to the end address detector 5.
[0006]
The waveform memory 1 sends the data stored at the address A sequentially input in synchronization with the clock c to the next D / A converter 6. The D / A converter 6 converts each input data into analog and outputs it as an analog waveform 2.
[0007]
The address A output from the address counter 4 is the end address A _E , A load command is applied from the end address detector 5 to the address counter 4. As a result, the start address A stored in the address storage unit 2 is sent to the address counter 4. _S Is newly loaded. Therefore, the same waveform 2 is repeatedly output from the D / A converter 6.
[0008]
Although the arbitrary waveform generator of FIG. 7 is configured to output only one type of waveform 2, as shown in FIGS. 9 and 10, an arbitrary waveform generator capable of outputting a plurality of types of waveforms has also been proposed. (Japanese Patent No. 2544210).
[0009]
A plurality of types of waveforms are stored in the waveform memory 1a of the arbitrary waveform generator as shown in FIG. Further, as shown in FIG. 10A, the start address A of each waveform stored in the waveform memory 1a. _S And end address A _E And a waveform switching unit 8 are provided.
[0010]
In the arbitrary waveform generator having such a configuration, when an operator (user) designates a waveform to be output to the sequence storage unit 7, the start address A of the corresponding waveform from the sequence storage unit 7. _S And end address A _E Are sent to the address storage unit 2. As a result, the address A of the designated waveform is output from the address counter 4 to the waveform memory 1a, and the designated waveform 2 is output from the D / A conversion unit 6.
[0011]
When a trigger b for switching the output to another waveform is applied to the waveform switching unit 8 during the output of one waveform 2, a waveform switching command is sent to the address storage unit 2. As a result, the address storage unit 2 stores the start address A of the switching destination (next) waveform stored in the sequence storage unit 7. _S And end address A _E And take in.
[0012]
When the currently output waveform 2 is completed after the trigger b is applied to the waveform switching unit 8, a load command is sent from the end address detecting unit 5 to the address counter 4. From this point, the trigger b is used. The output of the switched new waveform 2 is started.
[0013]
[Problems to be solved by the invention]
However, the arbitrary waveform generator shown in FIG. 9 still has the following problems to be solved.
[0014]
That is, consider a case where this arbitrary waveform generator is used by being incorporated in a test apparatus that tests the operation of a terminal that performs various communications with a base station such as a mobile phone. In this case, a trigger (frame trigger signal) is received from the terminal under test at a substantially constant cycle, and in synchronization with this trigger (frame trigger signal), the test apparatus is generated from the waveform generated by the arbitrary waveform generator. The test signal needs to be transmitted to the corresponding terminal under test.
[0015]
The output timing of the almost constant cycle trigger (frame trigger signal) generated by the terminal under test is large before and after the change when the transmission / reception setting value (parameter) of the terminal under test is changed for the test. The case of changing occurs.
[0016]
As an arbitrary waveform generator incorporated in the test apparatus, when a trigger (frame trigger signal) b is inputted, the output of the waveform 2 is synchronized with the trigger (frame trigger signal) b and the leading edge (start address A _S However, as shown in FIGS. 11A and 11B, the input timing of the trigger (frame trigger signal) b changes, so that the trigger (frame trigger signal) b is input. To the time T until the next waveform 2 is actually output. _A There is a problem that is not constant.
[0017]
Further, since the clock cycle of the terminal under test does not completely match the clock cycle of the test apparatus, the timing of the trigger (frame trigger signal) b output from the terminal under test matches the clock of the test apparatus. Not necessarily.
[0018]
Further, there is a case where one waveform having a relatively long period, such as a pseudo random code string waveform, is divided into fixed-length blocks divided by a trigger (frame trigger signal) b and output. For example, this corresponds to a case where a pseudo-random code string waveform is transmitted by being divided into bursts of a burst signal.
[0019]
In such a case, the start address and end address of the waveform (partial waveform) output in each block of one waveform having a relatively long cycle are written in the sequence storage unit 7.
[0020]
However, since it is rare that the value obtained by dividing the length (number of addresses) of one waveform having a relatively long period by the fixed length (number of addresses) of the block becomes an integer, the end address of the block has a relatively long period. Thus, it is necessary to write a plurality of waveforms having a relatively long period continuously in the waveform memory 1a so as to coincide with the end of one waveform.
[0021]
As a result, the storage capacity required by the waveform memory 1a is required by at least the least common multiple of the fixed length of the block and the length of one waveform (number of addresses), which increases the manufacturing cost. In addition, the necessary storage capacity of the sequence storage unit 7 also increases.
[0022]
The present invention has been made in view of such circumstances, and after a certain adjustment time has elapsed for an externally input trigger, the waveform starts to be output from the beginning, and switching of the output waveform is performed by a trigger transmission source device. It is an object of the present invention to provide an arbitrary waveform generator that can accurately synchronize with the setting change of the apparatus and can expand the application of the apparatus.
[0023]
It is another object of the present invention to provide an arbitrary waveform generator that can reduce the required storage capacity of the waveform memory.
[0024]
[Means for Solving the Problems]
In the present invention, each data for forming one or more types of waveforms is stored in each address of the waveform memory, and each data stored in each address corresponding to the designated waveform is synchronized with the clock. It is applied to an arbitrary waveform generator that generates at least one specified waveform by sequentially reading.
[0025]
In order to solve the above problems, in the arbitrary waveform generator of the present invention, address information output means for outputting the start address of the designated waveform in the waveform memory and the end address specifying information for specifying the end address From the address information output means, an address counter that loads the start address output from the address information output means and applies an address that increases or decreases sequentially from the start address to the waveform memory in synchronization with the clock. Address counter stopping means for stopping the address counter by detecting that the address output from the address counter has reached the end address of the waveform using the output end address specifying information, and the timing of the trigger input from the outside After adjusting the time, start this trigger to the address information output means. Is applied as the output instruction-less and end address specifying information, and and a timing adjusting means for applying a load instruction start address to the address counter.
[0026]
In the arbitrary waveform generator configured as described above, for example, when a trigger (frame trigger signal) output from a device to which a waveform output from the arbitrary waveform generator is input is input to the arbitrary waveform generator. This trigger is adjusted in timing time, applied to the address information output means as an instruction to output the start address and end address specifying information, and applied to the address counter as an instruction to load the start address.
[0027]
Therefore, when a trigger is input to the address counter, for example, timing adjustment of less than one clock is performed, and then output of the next waveform is started from the next clock.
[0028]
Therefore, even if this trigger is input during the output of one waveform, the output of the next waveform is started almost in synchronization with this trigger input without waiting for the end of the output of this waveform. The signal input / output can be synchronized with the device to which the waveform output from the generator is input.
[0029]
In another aspect of the invention, the address information output means in the arbitrary waveform generator of the invention described above is a next start address storage means means for outputting a start address stored by itself in response to an output instruction from the timing adjustment means. In response to the output instruction from the timing adjustment means, the start address to be output is calculated in response to the output instruction next to this output instruction, and the calculated start address is stored in the next start address storage means means. Start address calculating means for updating the start address.
[0030]
In the arbitrary waveform generator configured in this way, every time a trigger (frame trigger signal) is input from the outside, the start address stored in the next start address storage means is output, and the next output The start address to be output is automatically calculated according to the instruction.
[0031]
In this way, each time a trigger is input from the outside, each time the start address of the waveform to be output next is calculated, one waveform having a relatively long period as described above is triggered in a fixed-length block (frame trigger). Even in the case of outputting by dividing by (signal), it is only necessary to prepare a waveform memory that stores only one waveform having a relatively long period.
[0032]
Furthermore, in another invention, the end address specifying information in the arbitrary waveform generator of the invention described above is configured by the number of addresses indicating the length of the corresponding waveform. Further, the address counter stopping means is constituted by an address number counter that subtracts the input address number in synchronization with the clock and stops the address counter when the address number reaches zero.
[0033]
Further, in another invention, the end address specifying information in the arbitrary waveform generator of the above-described invention is configured by the end address of the corresponding waveform. Further, the address counter stopping means is constituted by an end address detecting section for stopping the address counter when the address output from the address counter matches the input end address.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of an arbitrary waveform generator according to the first embodiment of the present invention. The arbitrary waveform generator of this embodiment is incorporated in a test apparatus that tests the operation of a terminal that performs various communications with a base station such as a mobile phone. The arbitrary waveform generator receives a frame trigger signal output from the terminal under test at a substantially constant period, and generates a waveform in synchronization with the frame trigger signal. The test apparatus has a function of creating a test signal using the output waveform and transmitting it to the terminal under test.
[0035]
In FIG. 1, each data of the target waveform is stored in each address in the waveform memory 11. In the arbitrary waveform generator of the first embodiment, the waveform memory 11 has (2 ^N A waveform of a relatively long pseudo-random code sequence having a period of 1) is stored for only one waveform. (N = 9, 15, 23, etc.) And this (2 ^N -A waveform of a pseudo-random code sequence having a period of 1), for example, a fixed length N such as 120 addresses. _B Are divided into triggers (frame trigger signals) and output.
[0036]
In the address information output unit 12, a next start address storage unit 13, a next start address calculation unit 14, and a next address number storage unit 15 are provided. When the output instruction d from the timing adjustment unit 16 is input, the next start address storage unit 13 stores the start address A stored by itself. _S Is applied to the address counter 17. When the output instruction d is input from the timing adjustment unit 16, the next address number storage unit 15 receives the number of addresses N indicating the length of the waveform stored by itself. _A Is applied to the address number counter 18.
[0037]
When the output instruction d is input from the timing adjustment unit 16, the next start address arithmetic unit 14 starts output address A to be output according to the output instruction d next to the output instruction d. _S And the calculated start address A _S The start address A stored in the next start address storage unit 13 _S Update. Specifically, the start address A output in response to the current output instruction d stored in the next start address storage unit 13. _S Fixed length of block N _B (= 120) is added to the next start address A _S And Further, the next start address calculation unit 14 calculates the fixed length N of the block. _B The number of addresses N stored in the next address number storage unit 15 _A Update.
[0038]
The timing adjustment unit 16 adjusts the timing of the trigger (frame trigger signal) e input from the external terminal under test to the clock timing, and then sends the trigger e to the address information output unit 12 as the start address A. _S And the number of waveform addresses N as end address specifying information _A Output instruction d, and the start address A to the address counter 17 _S Is applied as a load instruction g.
[0039]
When the load instruction g is applied from the timing adjustment unit 16, the address counter 17 starts the start address A output from the address information output unit 12. _S Take in. Then, the address counter 17 synchronizes with the clock generated within itself and starts address A. _S Are increased or decreased by a predetermined number, and each address A increased or decreased by a predetermined number is sequentially applied to the waveform memory 11.
[0040]
The waveform memory 11 sends the data stored at the address A sequentially input in synchronization with the clock to the next D / A converter 19. The D / A converter 19 converts each input data into analog and outputs it as an analog waveform j.
[0041]
The address number counter 18 receives the address number N from the address information output unit 12. _A Is applied, the number of addresses N is synchronized with the clock generated within itself that is synchronized with the clock of the address counter 17. _A Is decremented by 1 and the number of subtracted addresses is N _A When 0 becomes 0, a stop command h is applied to the address counter 17.
[0042]
As a result, the address counter 17 stops operating and waits for the input of the load command g by the next trigger (frame trigger signal) e input.
[0043]
FIG. 2 shows the timing of the trigger (frame trigger signal) e input from the terminal under test to the arbitrary waveform generator due to, for example, changing the setting contents of the terminal under test. It is a figure which shows the time chart which shows the state of each part at the time of generating in the output period of the waveform with respect to (signal) e.
[0044]
Trigger (frame trigger signal) e is time t ₁ Input at time t ₂ ~ T _Three Clock period T of the next clock i ₁ The start address A output from the address information output unit 12 at this time to the address counter 17 _S (= M) is loaded. At the same time, the number N of addresses output from the address information output unit 12 at this time _A (= Y) is loaded into the address number counter 18.
[0045]
Furthermore, the clock cycle T ₁ And start address A _S Is applied to the next start address calculator 14, and the next start address calculator 14 starts calculating the next start address. When the calculation of the next start address ends, time t _Three The calculated next start address A in the clock cycle of _S (= N) is output from the address information output unit 12.
And the clock cycle T ₁ Next clock i (time t _Three ) Starts to output the next waveform.
[0046]
As can be understood from the time chart of FIG. 2, even if the trigger (frame trigger signal) e is input during the output period of the waveform, two clock cycles elapse from the input time of the trigger (frame trigger signal) e. At this point, the output of a new waveform is surely started from the beginning.
[0047]
Further, in the arbitrary waveform generator of the first embodiment configured as described above, every time a trigger (frame trigger signal) e is input from the terminal under test, the start address A of the waveform to be output next time each time. _S Is calculated by the next start address calculation unit 14. Therefore, in the waveform memory 11, (2 ^N -Even if only one waveform of a relatively long pseudo-random code sequence having a period of 1) is stored, when each block is output in a fixed-length block separated by a trigger (frame trigger signal) e, The block waveform is output. Therefore, the storage capacity of the waveform memory 11 can be saved.
[0048]
Furthermore, it is not necessary to use the sequence storage unit 7 used in the conventional arbitrary waveform generator of FIG.
[0049]
In addition, by configuring the timing adjustment unit 16 with a delay counter, the time from the input of the trigger (frame trigger signal) e to the start of output of a new waveform can be set (adjusted) to an arbitrary clock cycle length. . By adopting the delay counter in this way, it is possible to absorb the time difference between the transmission timing of the trigger (frame trigger signal) e from the terminal under test and the reception timing of the trigger (frame trigger signal) e of the arbitrary waveform generator.
[0050]
Furthermore, since a waveform is started to be output in synchronization with the internal clock after a predetermined adjustment time has elapsed from a clock (frame trigger signal) e input from the terminal under test at a substantially constant cycle, even if the waveform is received. Even if there is a difference between the clock cycle of the terminal under test and the internal clock cycle of the arbitrary waveform generator of the embodiment, it is resolved before the transmission timing and reception timing of the waveform due to this difference are significantly different. .
[0051]
Therefore, since it is not necessary to guide the clock of the terminal under test to the arbitrary waveform generator, the configuration of the arbitrary waveform generator can be simplified.
[0052]
(Second Embodiment)
FIG. 3 is a block diagram showing a schematic configuration of an arbitrary waveform generator according to the second embodiment of the present invention. The same parts as those of the arbitrary waveform generator of the first embodiment shown in FIG.
[0053]
In the arbitrary waveform generator of the second embodiment, a next end address storage unit 21 is provided in the address information output unit 12a in addition to the next start address storage unit 13 and the next start address calculation unit 14 described above. Yes. The next end address storage unit 21 stores the end address A of the waveform output in response to the next output instruction d calculated by the next start address calculation unit 14. _E Is memorized. Naturally, the next start address calculation unit 14 sets a new end address A. _E Is calculated, the end address A stored in the next end address storage unit 21 is calculated. _E Also this new end address A _E Updated to
[0054]
Each time an output instruction d is input to the address information output unit 12a, the start address A stored in the next start address storage unit 13 is stored. _S The end address A stored in the next end address storage unit 21 _E Is output.
[0055]
The end address detection unit 20 monitors the address A output from the address counter 17, and the address A output from the address counter 17 is the end address A output from the address information output unit 12a. _E If the two coincide with each other, a stop command h is applied to the address counter 17.
[0056]
As a result, the address counter 17 stops operating and waits for the input of the load command g by the next trigger (sequence trigger signal) e input.
[0057]
Also in the arbitrary waveform generator of the second embodiment configured as described above, it is possible to obtain substantially the same operational effects as those of the arbitrary waveform generator of the first embodiment described above.
[0058]
(Third embodiment)
FIG. 4 is a block diagram showing a schematic configuration of an arbitrary waveform generator according to the third embodiment of the present invention. The same parts as those of the arbitrary waveform generator of the second embodiment shown in FIG.
[0059]
In the arbitrary waveform generator of the third embodiment, each of the next start address storage unit 13 and the next end address storage unit 21 constituting the address information output unit 12a is independently dedicated from the timing adjustment unit 16. Output command d ₁ , D ₂ Is applied.
[0060]
In the arbitrary waveform generator of the third embodiment configured as described above, for example, in response to a trigger (frame trigger signal) e input from the terminal under test and each trigger (frame trigger signal) e input. The length of the output waveform can be set independently of each other. For example, when the waveform length is longer than the trigger period, the waveform is forcibly cut off halfway. When the waveform length is shorter than the trigger period, there is a period in which no waveform exists near the end of the trigger period.
[0061]
(Fourth embodiment)
FIG. 5 is a block diagram showing a schematic configuration of an arbitrary waveform generator according to the fourth embodiment of the present invention. The same parts as those of the arbitrary waveform generator of the third embodiment shown in FIG.
[0062]
In the arbitrary waveform generator of the fourth embodiment, a waveform start address A that is output in synchronization with each trigger (frame trigger signal) e. _S End address A of the waveform output in synchronization with the previous trigger (frame trigger signal) e _E Are set equal to.
[0063]
That is, the output instruction d from the timing adjustment unit 16 ₁ , D ₂ Is input from the next start address storage unit 13. _S Is output from the next end address storage unit 21 to the end address A _E Is output. Next, the end address A stored in the next end address storage unit 21 _E The start address A stored in the next start address storage unit 13 _S Is updated. Next, the next end address calculation unit 22 is activated, and the end address A stored in the next end address storage unit 21. _E And then the output instruction d ₂ End address A of the waveform that is output when is input _E And the calculated end address A _E Then, the end address AE of the next end address storage unit 21 is updated.
[0064]
Also in the arbitrary waveform generator of the fourth embodiment configured as described above, it is possible to achieve substantially the same operational effects as the arbitrary waveform generator of the third embodiment shown in FIG.
[0065]
(Fifth embodiment)
FIG. 6 is a block diagram showing a schematic configuration of an arbitrary waveform generator according to the fifth embodiment of the present invention. The same parts as those of the arbitrary waveform generator of the first embodiment shown in FIG.
[0066]
In the arbitrary waveform generator of the first embodiment, the same length (the same number of addresses N) is always synchronized with a trigger (frame trigger signal) e inputted at a constant period from the terminal under test. _A ) Waveform is output.
[0067]
Therefore, in the address information output unit 12b, the next start address storage unit 13 and the next start address calculation unit 14 are provided, but the next address number storage unit 15 is not provided. The address number counter 18 receives a reset instruction d output from the timing adjustment unit 16 in synchronization with the trigger (frame trigger signal) e. _Three Depending on the number of fixed addresses N determined in advance as an initial value. _A Is set, and this fixed number of addresses N _A Are subtracted in synchronization with the internal clock. Number of subtracted addresses N _A When 0 becomes 0, a stop command h is applied to the address counter 17. As a result, the address counter 17 stops operating and waits for the input of the load command g by the next trigger (frame trigger signal) e input.
[0068]
Also in the arbitrary waveform generator of the fifth embodiment configured as described above, it is possible to achieve substantially the same operational effects as the arbitrary waveform generator of the first embodiment shown in FIG.
[0069]
Note that the present invention is not limited to the first to fifth embodiments described above.
In the arbitrary waveform generator of each embodiment, the next start address calculation unit 14 or the next end address calculation unit 22 is incorporated in the address information output units 12, 12a, and 12b, and the next output from the arbitrary waveform generator is performed. Start address A of the waveform memory 11 _S Or end address A _E Was calculated each time.
[0070]
However, when the output waveforms are independent according to each trigger (frame trigger signal) e input, the start address A of each waveform _S And end address A _E Are stored in advance in the address information output unit 12, and each time each trigger (frame trigger signal) e is input, the stored start address A is stored. _S And end address A _E It is also possible to output the set of and in order.
[0071]
【The invention's effect】
As described above, in the arbitrary waveform generator of the present invention, the address counter is activated by loading the waveform start address output from the address information output unit to the address counter in response to an externally input trigger. I am letting. Therefore, after a certain adjustment time has elapsed from the trigger input time, the waveform starts to be output from the beginning, the switching of the output waveform can be accurately synchronized with the setting change of the trigger transmission source device, and the use of the arbitrary waveform generator can be expanded.
[0072]
Furthermore, each time a trigger is input, the start address in the waveform memory of the waveform to be generated next is calculated. Therefore, even when one waveform with a relatively long period is divided into fixed-length blocks by a trigger (frame trigger signal) and output, a wavelength memory for storing only one waveform with a relatively long period should be prepared. Therefore, the required storage capacity of the waveform memory can be saved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of an arbitrary waveform generator according to a first embodiment of the present invention.
FIG. 2 is a time chart showing the operation of the arbitrary waveform generator of the first embodiment.
FIG. 3 is a block diagram showing a schematic configuration of an arbitrary waveform generator according to a second embodiment of the present invention.
FIG. 4 is a block diagram showing a schematic configuration of an arbitrary waveform generator according to a third embodiment of the present invention.
FIG. 5 is a block diagram showing a schematic configuration of an arbitrary waveform generator according to a fourth embodiment of the present invention.
FIG. 6 is a block diagram showing a schematic configuration of an arbitrary waveform generator according to a fifth embodiment of the present invention.
FIG. 7 is a block diagram showing a schematic configuration of a conventional arbitrary waveform generator.
FIG. 8 is a diagram showing a relationship between each address of a waveform read from the waveform memory of the arbitrary waveform generator and a clock;
FIG. 9 is a block diagram showing a schematic configuration of still another conventional arbitrary waveform generator.
FIG. 10 is a view showing stored contents of a sequence storage unit and a waveform memory in the arbitrary waveform generator
FIG. 11 is a diagram for explaining problems of the arbitrary waveform generator
[Explanation of symbols]
11 ... Waveform memory
12, 12a, 12b ... Address information output unit
13: Next start address storage unit
14: Next start address calculation unit
15: Next address number storage unit
16. Timing adjustment unit
17 ... Address counter
18 ... Address counter
19 ... D / A converter
20: End address detection unit
21: End address storage unit
22: Next end address calculation unit

Claims (4)

Each data for forming one or more types of waveforms is stored in each address of the waveform memory (11), and each data stored in each address corresponding to the designated waveform is sequentially synchronized with the clock. In an arbitrary waveform generator that generates at least one specified waveform by reading,
Address information output means (12, 12a, 12b) for outputting the start address of the designated waveform in the waveform memory and the end address specifying information for specifying the end address;
An address counter (17) that is loaded with a start address output from the address information output means, and that sequentially applies addresses to the waveform memory from the start address in synchronization with the clock;
Address counter stop means (18) for detecting that the address output from the address counter has reached the end address of the waveform using the end address specifying information output from the address information output means and stopping the address counter. 20)
After adjusting the timing of an externally input trigger, this trigger is applied to the address information output means as an instruction to output start address and end address specifying information, and is applied to the address counter as an instruction to load the start address. Arbitrary waveform generator comprising timing adjustment means (16). The address information output means includes
In response to an output instruction from the timing adjustment means, a next start address storage means means (13) for outputting a start address stored by itself,
In response to an output instruction from the timing adjustment means, a start address to be output is calculated in response to an output instruction next to the output instruction, and the calculated start address is stored in the next start address storage means means. 2. The arbitrary waveform generator according to claim 1, further comprising start address calculation means (14) for updating the start address. The end address specifying information is the number of addresses indicating the length of the corresponding waveform,
The address counter stopping means is an address number counter (18) that subtracts the input address number in synchronization with the clock and stops the address counter when the address number reaches zero. The arbitrary waveform generator according to claim 1 or 2. The end address specifying information is an end address of a corresponding waveform,
3. The end address detector (20), wherein the address counter stop means stops the address counter when the address output from the address counter matches the input end address. Arbitrary waveform generator.

Images