JPH02304660A - Controller - Google Patents

Abstract

PURPOSE:To know the degree of a load of the controller by transferring the contents of a first time counting circuit and a second time counting circuit to a host device by a data transfer means. CONSTITUTION:When a controller 21 is not executing an instruction to a device 31 to be controlled or 32 from a host device 11, an instruction execution control circuit 204 in the device 21 effectuates a signal line 317, and supports to execute a time counting operation to a second time counting circuit 203. When the device 11 starts to execute an instruction to the device 31 or 32, the device 11 transfers an instruction code and an address of the device to be controlled to the device 21 through a signal line 301. The circuit 204 receives the instruction code and the address of the device to be controlled on the signal line 301 through a data transfer circuit 201 and a signal line 313, selects the device to be controlled which is supported through a signal line 321, executes a processing designated by the instruction code, and also effectuates the signal line 317 and allows a second time counting circuit 203 to stop its time counting operation, and simultaneously, effectuates a signal line 315 and allows a first time counting circuit 202 to start its time counting operation.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to the control of external storage devices or input/output devices in computer systems such as magnetic disk devices, optical disk devices, magnetic tape devices, card readers, and printers. The present invention relates to a control device that performs operations.

[Conventional technology]

Conventionally, in electronic computer systems, when the processing capacity reaches its limit due to an increase in the amount of processing, it has been difficult to identify the external storage subsystem or input/output subsystem that is the cause.

[Problem to be solved by the invention]

Therefore, in the past, it has been difficult to determine which control device should be added to an electronic computer system to improve its processing capacity.

The purpose of the present invention is to eliminate the cause of processing capacity limitations in computer systems by notifying a host device of the time when a control device such as an external storage device or an input/output device is used and the time when it is not used. An object of the present invention is to provide a control device that makes it possible to specify a control device that is currently being used.

[Means to solve the problem]

The present invention includes: a first timer that performs a timekeeping operation when processing is being performed on a controlled device; a second timer that performs a timekeeping operation when no processing is being performed on the controlled device;
data transfer means for transmitting the contents of the first timekeeping means and the second timekeeping means to the host device according to a command from the host device;
The present invention is characterized by comprising initial setting means for setting the first time measuring means and the second time measuring means to initial values in response to a command from a host device.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, the control device 21 of the present invention includes a data transfer circuit 201, a first clock circuit 202, a second clock circuit 203,
and an instruction execution control circuit 204. Further, the control device 21 of the present invention is connected to the host device 11 through a signal line 301 and to the controlled devices 31 and 32 through a signal line 321. As described above, in the embodiment of the present invention, one host device and two controlled devices are connected to the control device 21, but the number of connected devices may be arbitrary.

Next, the operation of the embodiment of the present invention will be explained in detail.

When the control device 21 is not executing a command from the host device 11 to the controlled device 31 or 32, the control device 21
The instruction execution control circuit 204 in the second clock circuit 204 enables the signal line 317 and supports the second clock circuit 20B to perform a clock operation.

When the host device 11 starts executing an instruction to the controlled device 31 or 32, the host device 11 sends the instruction code and the controlled device address to the control device 21 through the signal line 301.
Transfer to. The instruction execution control circuit 204 receives the instruction code and controlled device address on the signal line 301 through the data transfer circuit 201 and the signal line 313, and receives the instruction code and the controlled device address on the signal line 321.
selects the controlled device supported through the instruction code, executes the process specified by the instruction code, enables the signal line 317, causes the second clock circuit 203 to stop timing, and at the same time enables the signal line 315 to 1. The clock circuit 202 is caused to start clocking operation. When the instruction execution control circuit 204 completes a series of processing for the controlled device specified by the instruction code, the instruction execution control circuit 204 connects the signal line 3143 to the data transfer circuit 201,
The host device 11 is notified through the signal line 301 that the execution of the command has ended. If there is an instruction to be executed following the immediately previous executed instruction, the host device 11 similarly transfers the instruction code and controlled device address to the control device 21 through the signal line 301, and the immediately preceding instruction is executed. If it is the last command in a chain of commands, the controller 21 is notified through the signal line 301 that all commands to be executed have been transferred.

When the instruction execution control circuit 204 is notified through the signal line 301, the data transfer circuit 201, and the signal line 313 that the execution of a series of instructions has been completed, the instruction execution control circuit 204 disables the signal line 315 and causes the first clock circuit 202 to perform a timing operation. At the same time, the signal line 317 is enabled to cause the second clock circuit 203 to restart the clock operation.

In addition, while the controlled device is performing an operation that can be separated from the control device and execute processing independently, such as a seek operation in a magnetic disk device or a rewind operation in a magneto-electric device, the instruction execution control circuit 204 disables the signal line 315 to cause the first timekeeping circuit 202 to temporarily stop the timekeeping operation, and enables the signal line 317 to instruct the second timekeeping circuit 203 to perform the timekeeping operation.

As can be seen from the above explanation, the control device 21 is the controlled device 3
1 or 32, the first clock circuit 202 performs a time measurement operation, and when no processing is performed, the second clock circuit 202 performs a time measurement operation.
A clock circuit 203 performs a clock operation.

The instruction execution control circuit 204 is connected to the signal line 3 from the host device 11.
01, when the data transfer circuit 201 receives a command to transfer the contents of the timer circuit through the signal line 313, the data transfer circuit 201 transfers the contents of the timer circuit 2 to the data transfer circuit 201 through the signal line 314.
02 and the contents of the second clock circuit 203 are instructed to be transferred to the host device 11. The data transfer circuit 201 transfers the contents of the first clock circuit 202 and the second clock circuit 203 to the host device 11 through the signal line 301 through the signal line 312 and 311, respectively. The instruction execution control circuit 204 resets the contents of the first clock circuit 202 and the second bulletin board circuit 203 through the signal line 316 after the contents of the first clock circuit 202 and the second clock circuit 203 are transferred to the host device 11. instruct.

In the embodiment of the present invention, the instruction to transfer the contents of the first timer circuit and the second timer circuit to the host device and the instruction to reset the contents are executed by the same instruction, but they may be executed by separate instructions. good.

〔Effect of the invention〕

As explained above, the present invention has the effect of making it possible to know the degree of load on the control device by transferring the contents of the first timekeeping circuit and the second timekeeping circuit to the host device.

Brief description of the drawing FIG. 1 is a block diagram showing one embodiment of the present invention.

11... Host device, 21... Pa control device, 31.32
...Controlled device, 201...Data transfer circuit, 20
2...First timekeeping circuit, 203...Second timekeeping circuit, 2
04...Instruction execution control circuit.

Claims (1)

[Claims] a first timer that performs a timekeeping operation when a process for the controlled device is being executed; a second timer that performs a timekeeping operation when the process for the controlled device is not in progress; The apparatus includes data transfer means for transferring the contents of the timekeeping means and the second timekeeping means to a host device, and initial setting means for setting the first timekeeping means and the second timekeeping means to initial values based on a command from the host device. Characteristic control device.