JPS5769336A - Key input display controller - Google Patents

Key input display controller

Info

Publication number
JPS5769336A
JPS5769336A JP55141751A JP14175180A JPS5769336A JP S5769336 A JPS5769336 A JP S5769336A JP 55141751 A JP55141751 A JP 55141751A JP 14175180 A JP14175180 A JP 14175180A JP S5769336 A JPS5769336 A JP S5769336A
Authority
JP
Japan
Prior art keywords
key input
delivered
key
screen
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55141751A
Other languages
Japanese (ja)
Inventor
Yoshihiro Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP55141751A priority Critical patent/JPS5769336A/en
Publication of JPS5769336A publication Critical patent/JPS5769336A/en
Pending legal-status Critical Current

Links

Landscapes

  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: Not only to reduce the load of software but to shorten the transfer timer, by using a key input buffer and a screen memory in common under the control of a direct memory access controller.
CONSTITUTION: The 1-frame parameter of a CRT screen is analyzed by a parameter analyzing circuit 18, and the strobe signal delivered while a key input device 11 is operated is detected by an R-S type FF13. Then a request signal for direct memory access DMA transfer is delivered. The information supplied with key by the request signal of the FF13 is supplied to a screen/key input buffer memory 15 from a DMA controller 16 based on the information obtained by the circuit 18. Then the input data is transferred to the memory 15, and the same time a CRT controller 19 is controlled to reset an R-S type FF17 when the DMA transfer of data has been completed. Then an error signal to the operation of key carried out after the end of the DMA transfer of data is delivered to a CPU.
COPYRIGHT: (C)1982,JPO&Japio
JP55141751A 1980-10-09 1980-10-09 Key input display controller Pending JPS5769336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55141751A JPS5769336A (en) 1980-10-09 1980-10-09 Key input display controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55141751A JPS5769336A (en) 1980-10-09 1980-10-09 Key input display controller

Publications (1)

Publication Number Publication Date
JPS5769336A true JPS5769336A (en) 1982-04-28

Family

ID=15299342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55141751A Pending JPS5769336A (en) 1980-10-09 1980-10-09 Key input display controller

Country Status (1)

Country Link
JP (1) JPS5769336A (en)

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