JPH02303071A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve characteristics of a polycrystalline Si MIS type FET and prevent the deterioration of characteristics of a substratum device, by arranging a silicon nitride film in an island form, so as to cover a channel region. CONSTITUTION:By thermally oxidizing a P-type Si substrate 101, an SiO2 film 102 is formed; thereon a polycrystalline Si film 103 and an SiO2 film 104 are deposited; ion is implanted into the film 103, and the film 104 is eliminated; a gate electrode 103' is formed by processing the film 103; an SiO2 film 105 is deposited and heat-treated, thereby forming a gate oxide film; thereon an Si film 106 is deposited and processed in a specified form: an SiO2 film 107 is deposited; ion is implanted; impurity is activated, thereby forming a P-type high concentration impurity region of source.drain; an SiO2 film 108 is formed; an Si nitride film 109 is deposited and processed in a specified form; a contact hole is formed; an Al-Si film 110 is deposited; a wiring pattern is formed; finally a PSG film 111 is deposited, thereby forming a protecting film.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a semiconductor device and its manufacturing method that improves the characteristics of a polycrystalline SiM I S field effect transistor and suppresses deterioration of the characteristics of the underlying device. Regarding.

[Conventional technology]

IEE, Electron Device Letter EDL-5 (1984) pp. 468-470 (11: OHHFectron Devi
Cellett, BiDL-5, p. 468 (1984
)) Conventionally, polycrystalline Si
For hydrogenation of MOS field effect transistors, plasma CVD is used as the final protective film. Using the silicon nitride film formed in A, a method is used in which hydrogen atoms are diffused by heat treatment at 450°C.

[What does invention try to solve? [111I Problem] The above-mentioned conventional technology does not take into consideration the influence that diffused hydrogen atoms have on the single-layer device.

Therefore, if the device is fabricated in a single-crystal Si substrate,
In the case of a stacked device such as an OS transistor, M
There are problems in that the initial characteristics of the OS transistor fluctuate and the reliability is lowered due to hot carriers.

The present invention aims to suppress the deterioration of the characteristics of the underlying device as much as possible without impairing the characteristics of the Po1yS i -MOS transistor, and further aims to provide the structure and manufacturing method necessary therefor.

[Means for solving the problem J In order to achieve the above object, water AJ in the present invention]
A silicon nitride film serving as a K/− diffusion source was provided only above the channel region of the polycrystalline SiM I S field effect transistor.

Further, in order to effectively perform hydrogenation, the silicon nitride film was provided below the metal wiring film.

In addition, in order to improve the interface characteristics between the polycrystalline Si film including the channel region of the polycrystalline SiM I S type field effect transistor and the interlayer insulating film, 5iOz was added between the polycrystalline Si film and the silicon nitride film. A membrane was provided.

In addition, we have improved the characteristics of polycrystalline SiM I S type field effect transistors in SRAM, and
The above silicon nitride film was used to prevent the characteristics of the MO8) transistor in the substrate from deteriorating.

Further, in order to avoid increasing the number of photo-etching steps for etching the silicon nitride film and increasing manufacturing costs, etching was performed simultaneously with polycrystalline Si etching using the same mask.

(Function) Providing a silicon nitride film only on the upper side of the channel portion of the polycrystalline S i M I S type field effect transistor improves the characteristics of the polycrystalline S i M I S type field effect transistor, and also improves the performance of the underlying device. This acts to suppress the diffusion of excess hydrogen atoms as much as possible.Therefore, deterioration of the characteristics of the ground device can be prevented.

〔Example〕

The present invention will now be described in detail with reference to the drawings.

Example 1 A p-type Si-based film 101 is prepared and thermally oxidized to form a 5-ins film 10.
form 2. On top of that, a low pressure chemical vapor deposition method (hereinafter referred to as 1'L) is applied.
)'CVI) method and w8xt), polycrystalline Si
Deposit wAI Q 3 on top of the container L P CV D
A SiOx film 104 is deposited by a method, and BFa◆ ions are implanted into the polycrystalline Si film 103 (first Iy
4A).

Next, after activating the impurities, wet etching is performed in an HF-based aqueous solution to remove the SiOx film 1046.
Next, the polycrystalline Si film 103 is processed by a dry etching method using the photoresist pattern as a mask, and a 5ift film 105 is deposited to a thickness of 25 nm by a primary LPCV L) method to form a gate electrode 103', and then etched in a N2 gas atmosphere. A heat treatment is performed at 900° C. for 10 minutes to form a gate oxide film. On top of that, 5iHa gas was used as the reaction gas, and the temperature was 520°C.
'C to LPCVD method: YO) J S i IJ 10
6 is deposited to a thickness of 40 nm. It is processed into a predetermined shape by dry etching using a photoresist pattern as a mask.

Next, S i Ox fla was obtained by the L 13 CV D method.
tO7 is deposited, and BF'z÷ is ion-implanted using the photoresist pattern as a mask to activate the impurity and form p-type high concentration impurity regions of the source and drain.

Next): The SiOx film 108 is deposited by the CV L) method.
100n, and on top of that, 5iHa and N are added to the reaction gas.
A silicon nitride film 109 of 20 nu+ is deposited by the plasma CVLJ method using Ha at a substrate temperature of 30° C. Subsequently, the silicon nitride film 109 is processed into a predetermined shape by dry etching using the photoresist pattern as a mask (FIGS. 1B and C).

Next, contact holes were formed by dry etching using the photoresist pattern as a mask, and AQ-8i11Q 110
A wiring pattern is formed by dry etching using a photoresist pattern as a mask. Finally, p s G11! was obtained using the normal pressure Cvv method at a reaction temperature of 400°C. J (
A 5iOz film containing phosphorus) 111 was deposited to a thickness of 1μ to form the final protective film (Fig. 1D).

Polycrystalline 5i-p channel MO8 manufactured according to this example
In a type field effect transistor, the source electrode is grounded, voltage is applied to the drain and gate electrodes, and the drain electric field is 11g was determined. As a result, in this example, the off-state current is 1/1 compared to the structure without the silicon nitride film.
On the contrary, the on-current increased by 10 times. From this, it was found that hydrogenation was sufficiently performed with the structure of this example.

Embodiment 2 In Embodiment 1, an extra number of photo cycles is required for etching the silicon nitride film. On the other hand, in the present example shown in FIG. 2, the same effect as in Example 1 was obtained without increasing the number of photo-etching operations.

A p-type Si substrate 201 is prepared, and thermally oxidized 11 false 202. by the same method as in Example 1. Polycrystalline Si electrode 20: ('
, gate oxide film 205. Form a Si film 206 (second
(to figure).

Next, a 5-ift film 207 is deposited by the L P CV l) method, and 8×20 ions are implanted using the photoresist pattern as a mask. Then, the impurities are activated to form the p-type low concentration impurity regions of the source and drain. Forming 0 then H? 'The SiOx film 208 was removed by the
n. A silicon nitride film 209 of 200 nm is deposited by plasma CVIJ method (FIG. 2B).

Next, silicon nitride IHzo++ was removed using a dry etching method using the photoresist pattern as a mask.

5iOa films 208 and 207. The S
iOz 111210 is deposited, a contact hole is formed by dry etching using the photoresist pattern as a mask, an AQ-S i film 211 is deposited, and a wiring pattern is formed by dry etching using the photoresist pattern as a mask. 0 reaction temperature 40 (always 7 hC at J℃)
A pSG II film 212 is deposited by the vlJ method to form the final protective film (FIG. 2C).

In this example, transistor characteristics equivalent to those in Example 1 were obtained.

Embodiment 3 An embodiment in which the present invention is applied to a memory cell of a complete CMO3 type SRAM will be described with reference to FIG.

First, an n-type Si substrate 301 is prepared, and after forming a p-well 302, a strand isolation region 30:3 is formed by a selective oxidation method (LOCO8 method). Gate oxide film 304 is formed by thermal oxidation.
After forming, BFz+ is ion-implanted to adjust the threshold voltage of the n-channel MOS transistor.

After forming a connection hole for direct connection between the driving MOS transistor metal electrode and the diffusion layer of the transfer MOS transistor, depositing polycrystalline 5i 305 by the LPCVIJ method and performing phosphorus diffusion, a 5iOz film 306 is deposited by the LPCVLI method.
is deposited and a gate electrode is formed by dry etching. Next, a 5iOz film is deposited by the 0-order L P CV I) method in which p+ ions are implanted for the n-type low concentration impurity region of the structural phase, and the gate electrode is formed by anisotropic dry etching. A sidewall 307 is formed on the side wall of the semiconductor device 305, and As◆ is ion-implanted to form n◆ type high concentration impurity regions that will become the source and drain.

Next, after activating the impurities, [,P (m V
An interlayer SiOz film 308 is deposited by IJ method.

Subsequently, after forming a connection hole for connecting the gate electrode of the polycrystalline 5i-p channel MOS transistor and the gate electrode of the Mpml n MOS transistor, L
P CV IJ method to deposit polycrystalline Si film 0-order L IJ CV IJ method to deposit 5102 film) lFz+ ion implantation to activate impurities, then remove 5ift film by wet etching do.

Next, using the photoresist pattern as a mask, the polycrystalline Si film is processed into a predetermined shape by dry etching, and the gate electrode 309 of the polycrystalline 5i-p channel MOS transistor is formed using SiH+ gas and Nz as the zero-order reaction gas.
V I to L P using O gas at n, temperature 800°C
) method, deposited 1p525 nm of SiOx, and deposited N
Heat treatment was performed at 900°C for 10 minutes in a Z gas atmosphere,
Polycrystalline 5i-
a drain region diffusion layer of a p-channel MOS transistor;
After forming a connection hole to connect the gate electrode of the opposing inverter, silane gas (SiHg or 5izH
n or 5i3Ha) as the reaction gas and S i l! at a temperature of 520°C by the L)' CV l) method. 'J 31
1 is deposited to a thickness of 40 nm. It is processed into a predetermined shape by a dry etching method, a 5 iOz layer is deposited by an LPCVD method, and BFt+ is ion-implanted using a photoresist pattern as a mask to form source/drain regions.

A silicon nitride film 313 of 200 nm is deposited thereon by a plasma CvL method, and processed by a tri-etching method into a shape that covers the channel region of the polycrystalline Sj-ρMOS transistor.

Next, after forming a connection hole for connecting the gate electrode of the transfer n-channel MOS transistor and the first layer wiring, '1' iN and W are vapor deposited (314) and processed into a predetermined shape by dry etching. . Subsequently, a 5iOz film 315 containing phosphorus is deposited as a layer between the two layers, and after forming a connection hole with the second layer wiring, '1'iN and AQ are deposited.
16) Process into a predetermined shape using a dry etching method.

Finally, after performing a heat treatment at 400° C. for 30 minutes in a Nz gas atmosphere, an IJSG film 317 is deposited by the normal pressure CVO method at a reaction temperature of 400° C. to form a final IsI layer.

The standby current consumption of the memory cell manufactured in this example was reduced to 1710 compared to the conventional technology. Additionally, the soft error rate during operation was significantly reduced. Furthermore, this is due to the provision of a silicon nitride film. No deterioration in reliability due to hot carriers was observed.

Example 4 Example: Polycrystalline 5i-p channel M in memory cell
A silicon nitride film was provided only on the upper part of the ≠Jannel part of the OS transistor. In contrast, in this example, a silicon nitride film was provided over the entire memory cell mat portion (
Figure 4).

The memory is composed of a memory cell section and a circuit section on the same side.

Mutual fundductance due to hot carriers, threshold voltage fluctuation, etc. are particularly problematic in MOS peripheral circuits.
It is a transistor. Therefore, the structure shown in FIG. 4 is also effective for the purpose of the present invention, which is to improve the characteristics of a polycrystalline Si-ρ MOS transistor and to prevent low reliability of a grounded MOS transistor.

The manufacturing process is the same as in Example 3.

When etching the silicon nitride film, it is etched so as to cover the entire memory cell mat portion.

Results equivalent to those of 3 were obtained.

〔Effect of the invention〕

According to the present invention, the characteristics of a polycrystalline Si-M I S transistor can be improved by diffusion of hydrogen atoms from a silicon nitride film. The off-state current is reduced by a factor of 10, and the on-state current is increased by a factor of 10.

In SRAM using multi-coupled MSiMIS transistors as load elements, standby current consumption is reduced to 1/1 of that of conventional products.
The soft error rate during operation was also reduced. At the same time, the underlying MOS transistor achieved the same reliability as before.

[Brief explanation of drawings]

1 is a sectional view and a plan view of the manufacturing process of a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a sectional view and a plan view of a manufacturing process of a semiconductor device according to a second embodiment of the present invention. 3 is a cross-sectional view of a semiconductor device according to Example 3 of the present invention, and FIG. 4 is a plan view of a semiconductor device according to Example 4 of the present invention. 101... p-type Si substrate, 102...・Thermal oxide film, 1
03... SiOz film, 105... Gate oxide film, 106... Polycrystalline Si film (channel, source/drain region) 108... 5ift film, 109... Silicon nitride film, 110 ...AQ-8i film, 11
1...PSG film, 201...p-type 81 substrate, 202
...Thermal oxide film, 203'...Gate electrode, 205.
...Gate oxide film. 206... Polycrystalline Si film (channel, source/drain region), 208... 5iOz film, 209... Silicon nitride film, 210... 5iOz film, 211
-AQ-8i film, 212/PSG film, 301- n-type S
i-substrate, 302--p well, 303--socket isolation region, 304--gate oxide film, 105--polycrystalline Si film, 306-8iOz, 307-side wall, 308-- 5iOz, 309...gate electrode. 310... Gate oxide film, 311... Polycrystalline Si model (channel/source/drain region), 312...5
iOz, 313...Silicon nitride film, 314
...1st layer distribution IQ (W/ 'I' i N),
315-8iOa, 316-2nd layer wiring (A 14
/'l' i N). , R17°°"PSG membrane・v l 国／I+---P、S斤臘藁2 2θ3' 3 fig. VJ l fig.

Claims (1)

[Claims] 1. A polycrystalline Si film in which source and drain regions are formed in a polycrystalline Si film and a channel region is formed in the polycrystalline Si film.
1. A semiconductor device in which a silicon nitride film is provided in an island shape to cover a channel region in a MIS field effect transistor. 2. The semiconductor device according to claim 1, wherein the silicon nitride film is formed by plasma enhanced chemical vapor deposition. 3. The semiconductor device according to claim 1, wherein the silicon nitride film is provided below a metal wiring layer. 4. The semiconductor device according to claim 1, wherein a silicon doped film is provided between the polycrystalline Si film including the channel region and the silicon nitride film. 5. A semiconductor device in a static random access memory (SRAM) using a polycrystalline Si MIS field effect transistor, characterized in that a silicon nitride film is provided in an island shape so as to cover a channel region. 6. The method is characterized by comprising the steps of depositing a polycrystalline Si film in the channel portion, depositing the silicon nitride film, and etching the silicon nitride film and the polycrystalline Si film using the same mask. A method for manufacturing a semiconductor device according to claim 1.