JPH0230164A - Master slice type semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a device which is provided with a wiring pattern to by-pass a wiring-failure pattern, and can be easily manufactured in a short term, by forming a first layer wiring in a basic cell region as a fixed wiring, and forming a second layer wiring as a variable wiring capable of alternation according to the input-output circuit system applied to said basic cell region. CONSTITUTION:The title master slice type LSI is provided with the following; a master chip containing a basic cell region in which a plurality of basic cell rows 106 are arranged in a specified direction, and an input-output cell region, a first layer wiring and a second layer wiring. The first layer wiring 8 in the basic cell region is a fixed wiring formed on the master chip side. The second layer wiring in the basic cell region is a variable wiring capable of alternation according to the input-output circuit system applied to said basic cell region. A plurality of basic cells 104, 105 are arranged in the longitudinal direction of a master chip in the basic cell region, at specified intervals. A by-pass wiring region 40 having a previously set fixed-pattern is formed on a first layer between the basic cells 104, 105.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a master slice type semiconductor integrated circuit device (LSI
), especially for the I10 cell of master slice type LSI and its manufacturing method, the mask one-layer customization method is applied to the basic cell region, and the basic cell region 1
An object of the invention is to provide a master slice type LSI that can be manufactured easily and in a short period of time with a wiring pattern that bypasses a wiring failure pattern by using an unused area of the area, and a method for manufacturing the same. , a master chip including a basic cell region formed by a plurality of basic cell rows arranged in a fixed direction and an input/output cell region formed by a plurality of input/output cells arranged along an outer peripheral edge; In a master slice type semiconductor integrated circuit device in which first layer wiring and second layer wiring are arranged in a cell region and an input/output cell region, the first layer wiring in the basic cell region is formed on the master chip side. The second layer wiring that goes into the basic cell area is a variable wiring that can be changed according to the input/output circuit format applied to the basic cell area, and the basic cell area is arranged in the vertical direction of the master chip. A plurality of basic cells are arranged at constant +etl intervals, and a bypass wiring region having a preset fixed pattern is formed in the first layer within the interval between basic cells.

The invention according to claim 6 provides a method for manufacturing a master slice type semiconductor integrated circuit device in which an arbitrary wiring pattern is formed on a master chip to form a semiconductor integrated circuit, in which one to transistors are diffused on the master chip. region, a first layer wiring having a fixed pattern on the upper layer, a contact hole connecting the first layer wiring and the transistor diffusion region, and a second layer wiring.
A step of forming in advance a through hole between the wiring layers to be connected to the layer wiring, and a step of forming a second layer wiring that connects each ball of the wiring layer 1u'' with an arbitrary variable wiring pattern. and configure it.

[Industrial application field]

The present invention relates to a master slice type LSI, and more particularly to an I10 cell of a master slice type LSI and a method for manufacturing the same.

Master slice type LSI can be used for various games! - Suitable for manufacturing arrays. For a master slice type LSI, a master chip is created by forming a common pattern on the diffusion layer of the LSI.
This is an LSI for high-mix, low-volume production that is manufactured by individually designing only the wiring layers according to specifications requested by users.

According to this master slice type LSI, the delivery time of the LSI can be shortened by using a common pattern for expanded IT/iH.

Recently, there has been a demand to further shorten the delivery time of LSIs, and it has become necessary to adopt a single-layer mask customization method for wiring patterning.

The one-layer mask customization method means that one layer is placed on the master chip.
This is a method of forming a wiring pattern using a custom mask for each layer (wiring pattern mask specified by the user). According to this method, it is also possible to standardize the wiring pattern, so that it is possible to promote LSI manufacturing and shorten the delivery period.

[Technology from 1Jt] Figure 8 shows the master slice type L of CMOS game 1 hair array.
An overview of SI is shown.

The master slice type LSI 100 includes a basic cell region 101 and an I10 cell region 10 on one semiconductor substrate.
A master chip 103 is prepared by forming 2 in advance, and a wiring pattern is formed on the basic cell area 101 and the I10 cell area 102 according to the user's order to complete the process.

The basic cells 131101 are a pair of two basic cells 104 and 105 using CMOS transistors, and are arranged in the Y direction to form one basic cell column 106.
A plurality of basic cell rows 106 are arranged at predetermined intervals in the X direction. This is what is called a tuple column structure.

The I10 cell region 102 is made up of a plurality of I10 cells 107 arranged along the outer peripheral edge of the master chip 103.

The wiring patterning can be roughly divided into two types: processing for the basic cell 9ri region 101 and processing for the I10 cell region 102. The wiring patterning for the basic cell region 101 includes a total of 4 wiring patterns, including a first layer wiring, a second layer wiring, a contact hole between the transistor diffusion region and the first layer wiring, and an interlayer through hole between the first layer wiring and the second layer wiring. The layers were done using custom masks. A custom mask is a mask for wiring patterning desired by the user. Further, the wiring patterning for the I10 cell region 102 includes input terminals, output terminals, bidirectional terminals,
This was done using separate custom masks for power supply terminals, GND terminals, etc.

In the conventional master slice type LSI 100 described above,
The basic cell region 101 requires four layers of custom mask patterns, and the I10 cell region 102 requires at least five types of custom mask patterns, 177 custom mask patterns.

Preparing a plurality of types of custom mask patterns in this way complicates wiring pattern design and manufacturing, and increases the number of steps. This means that the demand for shorter LSI delivery times cannot be fully met.

Next, FIG. 9 shows details of the basic cells 104 and 105. As shown in FIG. 10, the basic cells 104 and 105 include a semiconductor substrate 5ub (FIG. 10(A)), a gate G (shaded area in FIG. 10(B)), and a source/drain region 1dS/D (Fig. 10(B)). (the shaded part in (C) in Figure 10). The cross-sectional structure of such a basic cell 10=1.105 is shown in FIG.

In FIG. 11, a diffusion layer 1 of a MOS transistor formed in a semiconductor substrate S14b is connected to a first layer wiring 8 via a contact pole 3 formed in an insulating layer 2, and a first layer wiring 8 is connected to a first layer wiring 8. 8 is isolated by an insulating layer 5, and a through hole 6 between wiring layers is formed at a predetermined position. Because of this, the inter-wiring layer through-pole 6 formed on the outside in FIG.
a) Gate G, source/drain fij region S/
It cannot be connected to the first layer wiring 8 which is connected to D, and even if a wiring is formed on such an interlayer through hole 6, no short circuit will occur in the circuit. Therefore, the inter-wiring layer through-hole 6 formed inside and the above-described inter-wiring layer through-hole 6a constitute a wiring failure pattern when connection is not required.

Furthermore, as is clear from the cross section 'fM' of FIG. 9 shown in FIG. Since there are the insulating layer 2 and the insulating layer 5, no short circuit occurs in the circuit.

From what has been described above, when forming one-layer wiring using the mask one-layer customization method, it is necessary to create a wiring pattern that bypasses wiring failure patterns.

Conventionally, in forming one-layer wiring in a basic cell area using a one-layer mask customization method, wiring has been performed using other areas such as a bypass-only fin area in order to bypass the wiring failure pattern. This is because in the conventional design apparatus, it is difficult in terms of processing efficiency and speed to design a wiring pattern that detours around a wiring failure pattern using an unused area on the basic cell area.

[Problem to be solved by the invention]

However, when wiring is performed using a dedicated bypass area as described above, it is necessary to secure a dedicated bypass area between the basic cells 104105, and for this reason, a cell row in which basic cells 104 and 105 are closely arranged is used. Difficult to form.

1. In order to realize a basic cell array with a double column structure, one layer of wiring (
Since it is necessary to form wiring (corresponding to the third layer wiring), a problem arises in that the one-layer mask customization method cannot be adopted. In addition, since the bypass-only area is used, when connecting the left and right sides of the basic cell area, etc.
There is also the problem that the wiring length becomes unnecessarily large and the resistance of this slanted wiring increases.

Therefore, the present invention applies a single-layer mask customization method to the basic cell area, and creates a master slice that can be manufactured easily and in a short period of time by using an unused area of the basic cell area and having a wiring pattern that bypasses the wiring failure pattern. The purpose of the present invention is to provide an LSI type LSI and a method for manufacturing the same.

[Means to solve the problem]

In order to solve the above problem, the invention according to claim 1 provides a basic cell region (101) formed by arranging a plurality of basic cell rows (106) in a certain direction and a plurality of inputs along the outer peripheral edge. A master chip (103) including an input/output cell area (102) formed by arranging output cells (107), and a first layer wired to the basic cell area (101) and the input/output cell area (102). A master slice type semi-3I equipped with wiring and second layer wiring.
In the P-tree integrated circuit device (100), the first layer wiring (8) in the basic cell area (101) is a fixed wiring formed on the master chip (103) side;
The second layer wiring (7) in the basic cell area (101) is a variable wiring that can be changed according to the input/output circuit format applied to the basic cell area (101),
The basic cell area 61 (101) is the master chip (10
3) A plurality of basic cells (104, 105) are arranged at regular intervals in the contraction direction, and a bypass wiring region (4) having a preset fixed pattern is formed in the first layer within the mutual interval. Configure it like this.

The invention according to claim 6 provides a method for manufacturing a master slice type semiconductor integrated circuit device (Zoo) in which a semiconductor integrated wt circuit is manufactured by forming an arbitrary wiring pattern on a master chip (103). ) is connected to a transistor diffusion region (1), a first layer wiring (8) with a fixed pattern above it, a contact ball (3) connecting this first layer wiring and the transistor diffusion region, and a second no wiring. a step of forming in advance an inter-wiring layer through-ball (6), and then a step of forming a second-layer wiring (7) for connecting the inter-wiring layer through-holes (6) with an arbitrary variable wiring pattern. and configure it.

[Effect]

According to the present invention, a transistor diffusion region, a first layer wiring with a fixed pattern, a second layer wiring with a variable pattern, a contact hole, and a through hole between the wiring layers are formed in advance on the master dig side, and the wiring patterning is performed by forming the through balls between the necessary wiring layers. The desired LS can be created by preparing 7+7 mask patterns for only one layer for the second layer with the bypass wiring area.
I can complete I. In this way, since only one layer of mask pattern is required, it is easy to design and manufacture.
The delivery time can be shortened, and the bypass wiring area can improve wiring efficiency.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

Hereinafter, the configuration, application circuit example, design device, and manufacturing method of the master slice type LSI according to the present invention will be explained.

Master Slice Type LSI First, the overall configuration of the master slice type LSI according to the present invention will be explained.

Figure 1 shows the master slice type L of a CMOS gate array.
A diagram showing an outline of SI and details of each part thereof is shown. In FIG. 1, parts corresponding to those in FIG. 8 are given the same reference numerals and will be described below.

On the master dig 103 is a page/y xel area 101.
, a wiring channel 108, and an I10 cell region 102 are formed.

In the basic cell region 101, a pair of basic cells 104 and 105 are arranged in parallel in the Y direction (vertical direction) to form one basic cell row 106, and the basic cell row 106 is A plurality of them are arranged at predetermined intervals in the direction (direction). As before, they are arranged in a tuple column structure. The basic cells 104 and 105 each include two CMOS transistors 20a.

20b. Between the basic cells 104 and 105, an inter-cell wiring region 30 having a fixed pattern set in advance is provided in the first layer. 1 (J
A bypass wiring region 40 having a fixed pattern set in advance in the first layer is formed between the CMO3I-ranging metals 20a and 20b which perform fH. Therefore, C
The MO3+- transistors 20a, 20b and the bypass wiring region 40 are arranged in the Y direction in an alternately repeated pattern. 50 is each CMO3+- transistor 20a.

This is the end wiring area of 20b. intercell wiring layer region 30,
The bypass wiring region 40 and the end wiring region 50 are set to have a predetermined wiring length, and are not connected to each other.

The inter-cell wiring region 30 consists of a short line region 30a and a long line pfj1 or 30b. The short line area 30a is the master chip 10
3 between adjacent basic cell regions in the X direction
It consists of a group of electric wires that are divided into a plurality of wires in the Y direction and arranged at predetermined intervals in the Y direction. The long line region 30b is a bypass wiring f adjacent to the master chip 103 in the X direction.
Basics are formed in the same number as the bypass wirings in the bypass wiring area 40 between the i-areas 40 with their ends not butting each other, and whose ends are adjacent to each other in the X direction. It consists of a group of long lines arranged so as to extend inward from the ends of the cell area.

As shown in FIG. 1, the wiring channel 108 has an interconnection region 108a in which wires are wired in units of a predetermined wiring length, and is formed in an area wider (approximately twice or more) than the intercell wiring layer region 30. . The length between each contact hole in the mutual wiring region 108a is such that one second layer wiring 7 (in the Y direction) can pass therethrough. The basic cell rows 106 are arranged in an alternating repeating pattern in the X direction (horizontal direction) with the wiring channels 108 in between.

The 110 cell head area 102 is composed of a plurality of I10 cells,
It is similar to FIG.

In FIG. 2, M of each basic cell 104105
The diffusion layer 1 of the OS+- transistor is connected to the first layer wiring 8 via the contact ball 3, and is connected to the first layer wiring 8 and the second layer formed by the mask one layer customization method described later. An inter-wiring interlayer through hole 6 is formed for connection to the wiring 7.

FIG. 3 shows a connection example of the bypass wiring area 40.

The wiring cells 10 shown in FIG. 4 are a plurality of types of wiring cells 10a to 10h corresponding to the patterns of basic cells 104 to 105 shown in FIG. 9. Here, as explained with reference to FIGS. 9 to 11 above, the wiring interlayer through-holes 1; The interlayer through-hole 6a constitutes a wiring failure pattern when no connection is required. Therefore, the wiring cells 10a to 10h having the patterns shown in FIGS. 4(A) to 4(H), respectively, are formed so as to bypass the wiring fault pattern described above.

In FIG. 71, the wiring cell 10a is for connection between the left and right wiring interlayer through-poles 6b of the basic cells 104, 105 (FIG. 4(A)), and the wiring cell 10b is for the connection between the left and right wiring layers of the basic cells 104, 105. The wiring cell 10c is for connection between the wiring interlayer through hole 6b and the upper part of the basic cells 104, 105 and the connection between the upper and lower parts of the basic cells 104, 105 (FIG. 4(B)). (Fig. 4(C)), and the wiring cell 10d is for connection between the upper and lower sides of the basic cell 104.1.
05 wiring interlayer through hole 6b and basic cell 10
4, 105 for connection above and below, and for connection between the top and bottom of basic cells 104, 105 (
Figure 4(D)).

Further, the wiring cells 10e to 10h are the wiring cells 10a to 10
These are the elemental wiring cell patterns of d, which are subjected to effects such as point symmetry, By doing so, the number of patterns to be prepared in advance can be reduced.

In FIG. 5, the second layer wiring 7 corresponds to one layer of wiring formed by a one-layer mask customization method, and the second layer wiring 7 is formed into a pattern by appropriately combining wiring cells 10a to 1011. The pattern between 9 points A and A' is a combination of two wiring cells 10a, and the pattern between point B and 8' is a pattern that is X-axis symmetrical to wiring cell 10f, wiring cell 10g, This pattern is a combination of a wiring cell 10f, a cell symmetrical to the X axis, and a wiring cell 10a.

Note that automatic wiring is performed between the wiring cells arranged on the base cell area 101 and between the wiring cells and the router area as in the conventional design apparatus.

The above-mentioned embodiment is an example in which the second layer wiring 7 corresponds to a one-layer wiring by a mask one-layer customization method, but the present invention is an example in which the first-layer wiring corresponds to a one-layer wiring by a mask one-layer customization method. , it is also applicable to all mask single layer customization methods.

Design Apparatus Next, the design apparatus for the master slice type LSI 100 will be described.

FIG. 1 is a conceptual diagram of the design apparatus of the present invention.

In FIG. 1, the design apparatus 2'00 of the present invention consists of a basic configuration mask pattern storage means 201, a wiring cell mask pattern storage means 202, and a pattern synthesis stage 203. The basic configuration mask pattern information stored in the basic configuration mask pattern information stored in the wiring cell mask pattern storage means 202 and the wiring cell mask pattern information stored in the wiring cell mask pattern storage means 202 are read and combined by the pattern synthesis means 203 to perform pattern synthesis. The mask pattern 204 of the wiring is designed.

The basic configuration mask pattern/information described above is mask pattern information regarding the basic configuration of the basic cell area 101 mounted on the LSI substrate, as shown in FIG. 3, for example.

The above wiring cell mask pattern information is also shown in Figure 4 (A
) to (H) relate to patterns of multiple types of wiring cells.

Next, wiring of the basic cell area 101 is performed by the design apparatus 200 according to the present invention, which stores the above-mentioned basic configuration mask pattern information and wiring cell mask pattern information in the basic configuration mask pattern storage means 201 and the wiring cell mask pattern storage means 202, respectively. We will explain the design of

A design device 20 that stores basic configuration mask pattern information regarding the basic cell area 101 shown in FIG.
0, when an instruction is input to connect between points A-A' and B-I3' in FIG. From among the wiring cell mask pattern information regarding the wiring cells 10a to 10h shown in FIG. 4 stored in , the wiring cell mask pattern information that provides the shortest wiring length to bypass the wiring failure pattern is read out. Then, by combining and pattern-synthesizing the read wiring cell mask pattern information and the basic configuration mask pattern information, a wiring mask pattern 20 of the basic cell area 101 as shown in FIG. 6 is created.
4 designs are carried out.

As described above, according to the present design device, the basic configuration mask pattern information stored in the basic configuration mask pattern storage means and the wiring failure pattern stored in the wiring cell mask pattern storage means The basic cell area wiring of the LSI is designed by reading and combining the wiring cell mask pattern information for bypassing by pattern synthesis, reading and combining by pattern synthesis means, and pattern synthesis, making the design easy. As a result, the time required for design is significantly shortened, and the wiring in the basic cell area can be configured using a one-layer mask customization method, and the time required for manufacturing LSIs is also significantly shortened.

Furthermore, since the length of the wiring to be formed can be suppressed to the minimum necessary length, it is also possible to reduce the wiring resistance.

Next, a method for manufacturing the master slice type LSI 100 will be explained.

The method for manufacturing the master slice type LSI 100 is roughly divided into a process for manufacturing the basic cell region 101 and a process for forming a wiring pattern on the upper surface of the basic cell region 101 using a custom mask.

When manufacturing the basic cell region 101, as shown in FIG. 22(a), an insulating film (S
I 02 ) 1 through 301. ! First layer wiring 8 is formed by vapor deposition or the like. Furthermore, an insulating film (Si
o□) 302 is formed, and its insulating film (SiO2) 302 is
A through hole 12 between wiring layers is formed to contact the insulating film (S i02 ) 301. Then, a conductive film 303 is formed on the entire upper surface.

Next, the design device 200 (21st
A mask pattern 204 is created using a photoresist (FIG.), and the conductive film 3 is etched using this mask pattern 204.
No desired wiring patterning was performed on 03.

Through the above steps, as shown in FIG. 22(c), an interlayer through-pole 12 is formed, and a master slice type LSI 100 according to user specifications is manufactured.

〔Effect of the invention〕

As described above, according to the present invention, 1-transistor diffusion region, first layer wiring of fixed pattern, second layer wiring of variable pattern,
Layer wiring, contact holes, and inter-layer through-holes are formed in advance on the master chip side, and the wiring patterning is performed by connecting the necessary inter-layer through-holes using an arbitrary variable wiring pattern. A desired LSI can be completed by preparing a mask pattern for only one layer. In this way, since only one layer of mask pattern is required, design and manufacture are easy, delivery times can be shortened, and wiring efficiency can be improved by using the bypass wiring area.

[Brief explanation of the drawing]

Fig. 1 is an overall configuration diagram of the master slice type LSI of the present invention, Fig. 2 is a pattern diagram of a basic cell array, Fig. 3 is a pattern connection diagram showing an example of the use of a bypass region, and Fig. 4 is a diagram of various wiring cells. Pattern diagram, Figure 5 is a basic cell wiring pattern diagram, Figure 6 is a conceptual diagram of the design device, Figure 7 is a sectional view showing the manufacturing process of master slice type LSI, Figure 8 is a conventional master slice type LSI. 9 is a pattern diagram of a conventional basic cell, FIG. 10 is an explanatory diagram of a conventional basic cell, and FIG. 11 is a partial sectional view of a conventional basic cell. 100...Master slice type LS1 101...Basic cell region 102...I10 cell area 103...Master chip 104.105...Basic cell 106...Basic cell row 107...I10 cell 108...Wiring channels 20a, 20b=-CMO3 transistor 30.
...Intercell wiring region 40...Bypass wiring region 50...End wiring region 1...MOS transistor diffusion layer 2...Insulating layer 3...Contact hole 5...Insulating layer 6... ...Wiring interlayer through hole 7...Second layer wiring 8...First layer wiring 10a to 1011...Wiring cell Wiring cell N pattern times Off-regular cell O pattern times name 4 times Honrocho O nailing device 0 imitation 1 time 8 each 1 arm earned (a) CC) 6 Yutaka I! 7th cross-section showing the LSI manufacturing slope
*LSI basic O transistor arrangement pattern - ￥ushiヱina Ushigosho 0 Contact hole 3 0・Gekibu 1 interval through hole 6 1: 躬fRWJ44 ■ - Sick - Beggar O pattern diagram

Claims (1)

[Claims] 1. A basic cell region (101) formed by a plurality of basic cell rows (106) arranged in a fixed direction and a plurality of input/output cells (107) arranged along the outer peripheral edge. a master chip (103) including an input/output cell area (102) formed by the basic cell area (102);
1) and the first wired to the input/output cell area (102).
In a master slice type semiconductor integrated circuit device (100) comprising a layer wiring and a second layer wiring, the first layer wiring (8) in the basic cell region (101) is formed on the master chip (103) side. The second layer wiring (7) in the basic cell area (101) is a variable wiring that can be changed according to the input/output circuit type applied to the basic cell area (101). The area (101) is the master chip (103
A plurality of basic cells (104, 105) are arranged at regular intervals in the vertical direction, and a bypass wiring region (104, 105) having a fixed pattern set in advance is provided in the first layer within the mutual interval between the basic cells (104, 105).
40) A master slice type semiconductor integrated circuit device comprising: 40). 2. In the device according to claim 1, the basic cell regions (101) are arranged in pairs at regular intervals in the lateral direction (X) of the master chip (103) to form basic cell rows (106). , the first one within the fixed interval in the lateral direction
A master slice type semiconductor integrated circuit device characterized in that an inter-cell fixed wiring region (30) having a fixed pattern set in advance is formed in the layer. 3. In the device according to claim 2, the intercell fixed wiring area (30) includes a short line area (30a) and a long line area (30b).
The short line area (30a) is the master chip (1
03) horizontally adjacent basic cells (104, 1
05) The long wire region (30b) is adjacent to the master chip (103) in the horizontal direction. The same number of bypass wiring regions (40) are formed between each bypass wiring region (40), corresponding to each bypass wiring of the bypass wiring region (40), with their ends abutting each other, and the end portions are A master slice type semiconductor integrated circuit device comprising a group of long lines arranged to extend inward from the ends of the horizontally adjacent basic cells (104, 105). 4. In the device according to claim 2 or 3, each basic cell column (106) is spaced apart from each other in the lateral direction of the master chip (103) by a width wider than the lateral width of the inter-cell wiring region (30). A master slice type semiconductor integrated circuit, characterized in that a plurality of wiring channels (108) are arranged in a plurality of basic cell rows (106), and a wiring channel (108) having a preset fixed pattern is formed in a first layer within an interval between each basic cell row (106). circuit device. 5. The device according to claim 4, wherein the wiring channel (10
8) is a master slice type semiconductor integrated circuit, characterized in that the master chip (103) is divided into a plurality of parts in a predetermined length unit in the lateral direction, and is composed of wiring groups arranged in an unconnected state. circuit device. 6. In a method for manufacturing a master slice type semiconductor integrated circuit device (100) in which a semiconductor integrated circuit is manufactured by forming an arbitrary wiring pattern on a master chip (103), a transistor diffusion region ( 1), the first layer wiring (8) with a fixed pattern on the upper layer,
A step of previously forming a contact hole (3) connecting the first layer wiring and the transistor diffusion region and an interlayer through hole (6) to be connected to the second layer wiring; (6) A method for manufacturing a master slice type semiconductor integrated circuit device, comprising: forming a second layer wiring (7) that connects each other with an arbitrary variable wiring pattern; 7. In the manufacturing method according to claim 6, the second layer wiring (7) is formed by forming a conductive film (303) on the entire surface of the second layer in advance in the step of forming the master chip (103),
A method for manufacturing a master slice type semiconductor integrated circuit device, characterized in that a second layer wiring (7) is formed by performing an arbitrary wiring patterning process in the formation process.