JPH0229526U - - Google Patents

Info

Publication number
JPH0229526U
JPH0229526U JP10851888U JP10851888U JPH0229526U JP H0229526 U JPH0229526 U JP H0229526U JP 10851888 U JP10851888 U JP 10851888U JP 10851888 U JP10851888 U JP 10851888U JP H0229526 U JPH0229526 U JP H0229526U
Authority
JP
Japan
Prior art keywords
bonding jig
bonding
island
semiconductor chip
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10851888U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10851888U priority Critical patent/JPH0229526U/ja
Publication of JPH0229526U publication Critical patent/JPH0229526U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図a,bは本考案の一実施例を説明するた
めのボンデイング治具の平面図及びA―A′線断
面図、第2図a,bは従来のボンデイング治具を
示す平面図及びB―B′線断面図である。 1…ヒータブロツク、2…気体吹出孔、3…ア
イランド、4…半導体チツプ、5…リード、6…
ボンデイング線、7…不活性ガス。
Figures 1a and b are a plan view and a sectional view taken along the line A-A' of a bonding jig for explaining an embodiment of the present invention, and Figures 2a and b are a plan view and a cross-sectional view showing a conventional bonding jig. It is a sectional view taken along the line B-B'. DESCRIPTION OF SYMBOLS 1...Heater block, 2...Gas blow-off hole, 3...Island, 4...Semiconductor chip, 5...Lead, 6...
Bonding wire, 7...Inert gas.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] アイランドに半導体チツプを搭載したリードフ
レームを載せて加熱し前記リードフレームのリー
ドと前記半導体チツプの電極との間をワイヤボン
デイングするためのボンデイング用治具において
、前記ボンデイング治具が前記アイランドと前記
リードとの間に設けた気体吹出孔を有することを
特徴とするボンデイング用治具。
In a bonding jig for wire bonding between the leads of the lead frame and the electrodes of the semiconductor chip by placing a lead frame on which a semiconductor chip is mounted on an island and heating it, the bonding jig connects the island and the leads. A bonding jig characterized by having a gas blowing hole provided between the bonding jig and the bonding jig.
JP10851888U 1988-08-17 1988-08-17 Pending JPH0229526U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10851888U JPH0229526U (en) 1988-08-17 1988-08-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10851888U JPH0229526U (en) 1988-08-17 1988-08-17

Publications (1)

Publication Number Publication Date
JPH0229526U true JPH0229526U (en) 1990-02-26

Family

ID=31343929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10851888U Pending JPH0229526U (en) 1988-08-17 1988-08-17

Country Status (1)

Country Link
JP (1) JPH0229526U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569135A (en) * 2012-02-07 2012-07-11 三星半导体(中国)研究开发有限公司 Heating block for wire bonding

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569135A (en) * 2012-02-07 2012-07-11 三星半导体(中国)研究开发有限公司 Heating block for wire bonding

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