JPH02288358A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve rapidity and yield by forming a sidewall to a gate electrode and by forming a layer pattern of a sidewall formation material corresponding to a mask pattern. CONSTITUTION:A base diffusion region is formed to a part of a collector region of a wafer bipolar transistor area in the first process. A gate electrode is formed on a wafer MOS transistor area in the second process. An impurity region of low concentration is formed to an MOS transistor area through ion implantation which uses a gate electrode as a mask in the third process. In the fourth process, a layer pattern 128 of a sidewall formation material is formed on a base diffusion region using RIE etching for forming of widewalls 134, 136. In the fifth process, after a protective layer is provided to an MOS transistor area, a contact hole 140 is provided to the layer pattern to form an emitter electrode 144. In the sixth process, an impurity region of high concentration for an MOS transistor is formed through ion implantation. Thereby, rapid operation can be realized and yield can be improved.

Description

Detailed Description of the Invention (Industrial Application Field) This invention relates to a method for manufacturing a semiconductor device in which a bipolar transistor and a MOS device are fabricated on the same wafer;
In particular, LDDs (L
i9htly DopedDrain) structure MO3
The present invention relates to a manufacturing method focusing on a bipolar transistor of a BiCMO3 semiconductor device 1 including a field effect transistor as a component of a CMOS device.

(Prior art) This type of BiCMO5 semiconductor device was developed and put into practical use as a realistic and effective technology that combines the high integration and low power consumption of CMOS devices with the high driving force and high speed of bipolar transistors. (For example, Document I: ``Ultra-high-speed MOS device, Ultra-high-speed digital device, SH1 nose'' Baifukan), and ultra-high-speed gate array LSIs using B1CMOS devices have also been proposed (Reference II: r Electronic Information Journal of the Communication Society CVol.

J71-CNo.9. pp, 1248-1256.19
September 1988).

Among these known BiCMO3 semiconductor devices, especially C
The MO8FETtLDD structure constituting the MOS device is attracting attention because it improves the degree of integration.
E.E. Transaction on Electron
Device (IEEE T day ANSACTI○N O
N ELECTRON DEVICE), Vol.
ED-32, No, 2. Feb, 1985J and literature ■:
“IEE Journal on Solid State Circuits (IEEE J.

unalof 5olid-state circ
units) Vol, 5C-21, No, 2. April
, 1986J).

First, prior to explaining this invention, this conventional typical
We will briefly explain the manufacturing process for fabricating a bipolar transistor and a CMOS device comprising an LDD structure NMOS transistor with a gate electrode with sidewalls formed on the same wafer, and then explain the problems with this conventional method. .

FIGS. 2(A) to 2) are manufacturing process diagrams for explaining a conventionally known method for manufacturing an 8iCMO5 semiconductor device, which is capable of manufacturing BiCMO8Wr with a small number of steps and at a low cost. Each figure schematically shows a cross-section of the structure obtained at the manufacturing stage. Typically, a large number of BiCMO3! Although a large number of such wafers are manufactured at the same time, the manufacturing of one BiCMO5 of a certain number of wafers will be described as a representative example.

First, as is conventionally known, an N◆ type buried layer 12 is buried in a P type silicon substrate 10 to form a P resin taxial layer 14, and an N type collector is formed above the buried layer 12 in this process and the taxial layer 14. A field oxide film (SiO2 film in this case) is formed using the LOCO3 method.
18 and bipolar transistors 1120 and N
An evaporator 26 (also referred to as an underlayer or structure) defining areas 22 and 24 for MO8 and PMOS transistors, respectively, is prepared (FIG. 2(A)).

Next, after forming a P-type diffusion region as the base diffusion region 28 of the bipolar NPN transistor on this wafer 26 with a diffusion depth of 0.4 um, the gate of the M○S transistor is disconnected. A gate oxide film that becomes an Il film (in this case, a Si
An O2 film) 30 is formed. At this time, an oxide film (SiO2 film in this case) 32 having the same thickness as the gate oxide film 30 is also formed in the bipolar transistor area 2°. This state is shown in FIG. 2 (8).

Next, a polysilicon film is grown on the entire surface of the wafer 26 by low-pressure CVD, and then the gates 134 and 36 of the NMO3 and PMOS transistors are formed using well-known photolithography and etching techniques. Using the well-known self-line technique using the gate electrodes 34 and 36 as masks, the NMO3t-transistor area 22 is filled with a lightly doped region (in this case N-
38 (which will become the type source/drain region) (the second
Figure (C)).

Next, apply C to the entire upper surface of the structure shown in FIG.
P20 as a CVD film (insulating film) using the VD method! 4 PSG films with a weight concentration of 15% by weight were made to have a length of 0 (
Figure 2 (D)).

Next, anisotropic etching is performed on the PSG film 4 using RIE (reactive ion etching) technology to form well-known sidewalls (sidewall oxide films) 4 and 2 on the sidewalls of the gate electrodes 34 and 36. and 44.

At this time, the bipolar transistor area 20. The wafer surface of the area planes 22 and 24 for NMO3 and PMOS transistors is exposed (see FIG.
E)).

Next, the structure shown in FIG. 2E is heat-treated in a dry oxygen atmosphere to form oxide films 46, 48 and 50 on the exposed wafer surface and the polysilicon surface of the gate electrode. In this case, area 2 for bipolar transistors
The 0 oxide film 46 serves as a processing/nching stopper during processing/etching in the later process, and the oxide films 48 and 50 in both MOS transistor sections Vt22 and 24 serve as high-concentration impurity impurities in the source/drain layer phase in the later process. These films act as protective films during ion implantation to form regions. Therefore, the film thickness is set to about 2,008 cm so that ion implantation is not impaired. The appearance of the structure thus obtained is shown in FIG. 2(F).

Next, the oxide film 46 in the bipolar transistor area 2o is
Then, using well-known photolithography and etching techniques, a window 52 for forming an emitter diffusion region is opened to expose the wafer surface, and then a polysilicon film 54 is formed over the entire upper surface of this structure by low-pressure CVD. Then, As (arsenic) ions are implanted into this polysilicon 11154 to form a diffusion source for forming an emitter diffusion region, thereby obtaining the structure shown in FIG. 2(G).

Furthermore, using well-known photolithography and etching techniques,
A diffusion source 56 for forming an emitter electrode/emitter diffusion region for a bipolar transistor is patterned, and a second
A structure as shown in Figure (H) is obtained. In this case, since the gate electrodes 34 and 36 are covered with oxide films 48 and 5o, they are not etched.

Next, using an ion implantation method, As ions are implanted into the NMOS transistor area 22 to partially transform the previously provided low concentration impurity region 38 into an N type high concentration impurity region 58. The remaining low concentration impurity region is indicated by 38a. Subsequently, using an ion implantation method, B F 2◆ is implanted into the PMOS transistor area 24 to form a high concentration (P+ type) impurity region 60, and a bipolar A P1 type base contact region 62 is formed in the base diffusion region 28 of the transistor area 20 and an N+ type collector contact region 64 is formed in the collector region 16 to obtain a structure as shown in FIG. 2(I).

Next, a PSG film, for example, is provided as a layer barrier film 66 on the upper side of this structure by the CVD method, and then heat treatment is performed at 900° C. for about 30 minutes in a wet oxygen atmosphere. flows and the surface becomes flat. At the same time, each region containing impurities also diffuses and expands.

Due to this expansion, the base diffusion region 28 is reduced from the original 0°4um.
It diffuses deeply from 0.6 um to become the base layer 68,
The base contact region 62 becomes the base contact layer 70, the collector contact region 64 becomes the collector contact layer 72, and As impurities are diffused from the diffusion source 56 into the base diffusion region 28 and hence into the base layer 68 to form an emitter layer 74. The collector region 16 or collector layer 8o is formed by forming each of these layers.

Further, by this heat treatment, the low concentration and high concentration impurity regions 38a and 58 are converted into the source or drain (here,
Expressed as source/drain. ) layer 76, and similarly, the high concentration impurity region 60 becomes a lath/drain layer 78. The appearance of the structure thus obtained is shown in FIG. 2(J).

Next, although not shown in the drawings, as is well known, contact holes are formed for interconnection between each transistor, and electrodes are formed using a gold layer such as aluminum or other suitable material to form a BiCM.
Complete O8 semiconductor device a.

(Problems to be Solved by the Invention) However, the 8iCMO3 semiconductor device having the structure manufactured by such a conventional method has two problems as described below.

- Due to manufacturing constraints of the BiCMO5 semiconductor device, it is not possible to achieve sufficient high-speed performance of bipolar transistors compared to when bipolar transistors are manufactured alone.

(2) The current amplification factor of the formed bipolar NPN transistor varies widely, making it impossible to improve the yield of LSI.

These points will be briefly explained below with reference to the completed model of the bipolar transistor shown in FIGS. 3 and 4. FIG. 3 is a model diagram schematically showing an enlarged portion of the base layer 68, emitter layer 74, base oxide J132, and emitter electrode 56 made of polysilicon above the collector layer 80 of the bipolar transistor. FIG. 4 is a model diagram schematically showing the position and size relationship of the base layer 68 and emitter layer 74 on the surface of the wafer 26. Indicated by

First, problem (2) will be explained.

It is generally known that the operating speed of a bipolar transistor increases as the current gain band amplification or cutoff frequency (hereinafter referred to as FT) increases. This FT is 1/2ytF□=τs”Tb +τ8+...(1)
The first term T is the charge/discharge time constant of the emitter-base junction, the second term Tb is the base time constant, and the third term τ
8 is the collector/depletion layer carrier transit time and the fourth term τ. is the base-emitter junction charging/discharging time.

Particularly in the low current region, the first term T is dominant. This τ is proportional to the base-emitter group capacitance C ε of the bipolar transistor, and in the structure shown in Fig. 3,
This base-emitter capacitance CTE is the emitter layer 74
It is known that Equation (2) is given by the PN junction capacitance J between and the base layer 68 and the capacitance COX of the base oxide fi 132 between the emitter electrode 56 and the base layer 6B.

Cya=C,, + +cOX + ”
・(2) Here, the relative dielectric constant of silicon is ε, and the dielectric constant of air is ε. , the amount of electric charge is q, and the Fermi potential between the emitter and the base is Vllll (Ell), then C1=(area of the bottom surface of the junction) x (area of the surface of the junction surface). On the other hand, for COX, the thickness of the oxide film 32 is d, and 5i0
If the relative dielectric constant of 2 is ε, then Cox=(εε./d) X
(Opposing area between emitter electrode and base layer)...(4
) is given by.

Therefore, in the model of FIG. 4, this capacitance CTε is calculated. Emitter area surrounded by boundary 82 (W
l xw,) is 2um x 5um, and the misalignment margin W3 in the mask alignment process when forming the emitter layer 74 in the base diffusion region 28 (corresponding to the base layer 68) is
Assuming that it is 1 um as usual, the area surrounded by the boundary 84 (
(W.

+ 2 Ws) x (W2 + 2 Ws))
is 4 um x 7 um. First, regarding C8, the carrier concentration N of the base layer 68 of the base-emitter junction is usually about 3xlO1 ion/Cm3,
The diffusion depth of the emitter layer 74 is usually about 0.3 um, and if V b+ +ts, 0, 7 V, and ε: 12, then C, = 8.6 fF; on the other hand, Coxl(tS As mentioned above, the thickness of the IO2 film 32 is 20OA, and its relative dielectric constant ε is 3.5, so Cax=27.9 fF. Therefore, the value of C0X is the same as that of a bipolar transistor. The value is about 10 times larger than the value when manufactured separately.And CTE=CJ +C0X
= 36.5fF, which is larger than the CTE of a bipolar transistor alone, so T in equation (1)
, becomes large, and therefore there is a problem that the high speed performance of the bipolar transistor in the low current region is impaired.

As a first countermeasure, it is possible to increase the thickness dt of the oxide film 32, but in the conventional method, as explained in FIG. 2(B), the oxide film for forming the gate oxide film is used as is. Therefore, if this oxide film is made thicker, the result shown in Figure 2 (
There is a drawback that As (arsenic) and B (boron) ions are not implanted in the ion implantation for forming the low concentration impurity region 38 of the source/drain layer phase described in step F).

In addition, as a second countermeasure, there is a method of reducing the area of the emitter electrode facing the base layer, but with this method, there is no choice but to reduce or eliminate the misalignment margin W3 during mask alignment. , if we break down this W3, we get
There is a drawback that the emitter layer cannot be formed due to misalignment.

Furthermore, the base time constant T of the second term of equation (1) above,
also has a large effect on the high-speed operation of bipolar transistors. This τゎ is defined as D, where W8 is the base width of the base layer, n is a constant depending on the minority carrier distribution in the base layer,
It is known that if is the diffusion constant of minority carriers in the base layer, it is given by τe+=Ws2/nDs'' (5).Generally, W6 is the depth of the base layer when the current amplification factor is constant. Since it becomes narrow depending on (
From equation 5), it can be understood that if W8 becomes narrower, FT becomes larger due to the squared ratio, and high-speed operation becomes possible. However, according to the conventional manufacturing method of the 8i CMO3 semiconductor device described above, as explained in FIG. 2(B), the MOS gate electrode 34 (formed in the process of FIG. Since the base diffusion region 28 is provided in the process, the original base diffusion layer 2 can be replaced by the subsequent heat treatment process.
Since the impurity diffuses from the diffusion depth 0.4 um of No. 8 and the region expands, the depth of the base layer 68 is finally 0.4 um.
It will be about 6um.

The experimental results of the FT IE characteristics (cutoff frequency-emitter current characteristics) of the B i 0 MO3 bipolar transistor obtained by the conventional method are plotted with the emitter electrode IE (in mA unit) on the horizontal axis and the cutoff frequency on the vertical axis. FT(GH
2 units) is plotted in Figure 5, which is shown by the curve ■.As can be understood from this figure, even by increasing the depth of this diffusion, the bipolar transistor with a continuous frequency F of about 4.5 GHz can be There was a problem that I could only get it.

In addition, as disclosed in the above-mentioned document II, 8
B1CMOS gate arrays etc. using devices with iCMO3 structure are often composed of circuit forming elements such as two-power NAND7a with a composite circuit of bipolar transistors and MOS transistors, and as shown in Figure 6, there are three types: day type, N type, and No matter which D-type 8iCMO8 logic gate is used, it is the MOS transistor that drives the base current of the final stage bipolar transistor.

Since the MOS transistor has a small driving ability, it cannot supply a small amount of current at the start of switching of the bipolar transistor. Therefore, the higher the cutoff frequency FT of the bipolar transistor in the low current range, the faster the switching becomes. From this point of view, the cutoff frequency F is higher in the low emitter current vA region. It is hoped that this will be the case.

Next, problem (2) will be explained.

As already explained, a sidewall is provided on the gate electrode in order to make the MOS device have an LDD structure. In the conventional method described above, as explained in FIGS. 2(C) to 2(E), after forming the gate electrode 34, a CVD film such as PS
After the G film 4o is once provided on the entire surface of the wafer, the PSG film 4o is anisotropically etched by IE etching. However, the thickness is uniform over the entire surface of the wafer (usually about 1.t 4000 A) T: i::,
(7) Although P SGM 401 is provided, the thickness varies by 3 to 5% between the center side and the edge side of the same wafer.

In addition, the same degree of variation in thickness occurs between each wafer. On the other hand, the RIE etching rate also varies by about 3 to 10% not only within the same wafer but also between different wafers. Figure 7 shows the variation in the amount of etching when multiple silicon wafers are simultaneously etched for an appropriate period of time using RIE etching. In the figure, the horizontal axis represents the frequency and the vertical axis represents the etching amount. This is an indication. From this experimental result, it can be seen that the etching amount of the wafer ranges from several amps to a maximum of 200 amps.

By the way, for example, a CVD film (such as the PSG film 40 which is an insulating film shown in FIG. 2(D)) with a film thickness of 4000 A is deposited on both the MOS transistor areas 22 and 24 of the wafer except for the sidewalls 42 and 44. If the doped oxide films 48 and 50 (FIG. 2(F)) remain in the ion implantation process in the subsequent process, variations will occur.As a result, the depths of the high concentration impurity regions 58 and 60 will vary. In order to avoid this situation, it is normal to set R
Controls IE etching time. However, assuming that there is a variation in film formation of ±5%, in order to etch the film so that it does not remain on the wafer except for the sidewalls, the maximum film thickness of the PSG film 40 is 420 OA, and the standard etching time is 0M0S that 10%~30% overetch jig time needs to be added
Assuming that the maximum film thickness of the PSG film 40 in the transistor areas 22 and 24 is 420 OA, and the minimum film thickness of the PSG film 40 in the bipolar transistor area 20 is 380 OA, the process of FIG. 2(E) , the surface of the base diffusion region 2 days may be etched away by 40 OA, resulting in a depth of 0.56 um for the final base layer 68 in FIG. 2(J). The PSG film 4° in this section t420 has a maximum film thickness of 4200 mm between different wafers that are processed simultaneously.
In the case of A, the diffusion depth is 0.6 um, whereas the minimum film thickness is 380 OA (7) 1. tt'Reyo'
) also becomes deeper by 0.04 um (400A), and the variation reaches 7%.

By the way, as is well known, the current amplification factor of emitter grounding strongly depends on the base width W8 and the total number of balls in the base layer, and this base width w0 is determined by the width of the emitter electrode 56 in contact with the emitter layer 74. Since it corresponds to the distance perpendicular to the wafer surface between the junction boundary between the emitter layer 74 and the base layer 68 directly below and the junction boundary between the base layer 68 and the collector layer 8o, W8=(base depth) −(emitter depth). As already mentioned, the depth of the emitter layer is usually set to 0.
Since it is 3 μm, at the maximum thickness of the PSG film 40 mentioned above, the base width w81 is 0.3 μm, while at the minimum thickness, the base width W +12 is 0.24 μm, so W s 2 / W a + =0.8 therefore 20
% will also vary. Within the pace layer 68,
Since hole carriers are unevenly distributed on the emitter layer 74 side, even if the base width Wll changes slightly, the current amplification factor of the grounded emitter will also vary greatly.

FIG. 8 is a diagram showing variations in the current amplification factor, and the vertical axis indicates the current amplification factor.

Because of this variation in current amplification factor, 8iCM
The yield of O3 LSI decreases.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to prevent the base diffusion region of the bipolar transistor area from being etched by RIE etching for forming a sidewall on the gate electrode of the MoS transistor, and to prevent the base diffusion region of the bipolar transistor area from being etched. A semiconductor device, preferably, in which ion implantation for formation can be performed reliably, and in which the facing distance between an emitter electrode and a base layer is formed to be larger than before, and which can operate at high speed and has an excellent yield. An object of the present invention is to provide a method for manufacturing a BiCMO3 semiconductor device.

(Means for Solving the Problems) In order to achieve this object, the present invention provides a semiconductor device M comprising a bipolar transistor and an LDD structure MOS transistor having a gate electrode with a side wall on a silicon wafer. There are three methods for manufacturing:

The first method includes a first step of forming a base diffusion region in the collector region of the bipolar transistor area of the wafer, a second step of forming a gate electrode on the MOS transistor area of the wafer, and the MOS transistor. In the third step, ions are implanted into the target area using the gate electrode made in the second step as a mask to form a low concentration impurity region vt. After providing the wall forming material layer, a mask pattern is provided on the side wall forming material layer corresponding to at least a portion of the base diffusion region formed in the deep step, and then RI is applied.
A fourth step of forming sidewalls on both gate electrodes using E-etching technology and forming a layer pattern of sidewall forming material corresponding to the mask pattern, and forming a protective film on at least the surface of the MOS transistor area. After forming a contact hole in this layer pattern without etching the underlying base diffusion layer,
A fifth step is to form an emitter electrode that also serves as an emitter diffusion source and contacts the base diffusion region through the contact hole on this layer pattern, and ion implantation is performed in the MOS transistor area using the gate electrode with sidewalls as a mask. The structure obtained in the sixth step is heat-treated, and the above-mentioned base is formed by diffusion of impurities from the emitter diffusion source formed in the fifth step. The present invention is characterized in that it includes a seventh step of forming an emitter layer in the diffusion region, a collector layer in the collector region, and a source/drain layer of an LDD structure in the low-concentration and high-concentration impurity regions.

In the second method, the thickness remaining from the subsequent RIE etching for sidewall formation on at least the bipolar transistor area of the wafer is greater than the thickness of the gate oxide layer formed in another subsequent step. a first step of forming a base diffusion region in the collector region of the region after providing an insulating layer with increasing film thickness; a second step of patterning to form a layer pattern; a third step of respectively forming gate electrodes via gate oxidation S on the MOS transistor area of the wafer; A fourth step of performing ion implantation using the created gate electrode as a mask to form a low concentration impurity region, a fifth step of forming sidewalls on both gate electrodes using RIE etching technology, and at least a MOS After the protective film is provided on the surface of the transistor area, the layer pattern is partially etched by the RIE etching in this fifth step, and the remaining layer pattern is removed, so that the underlying base diffusion region is not etched. A sixth step is to form a contact hole on this layer pattern, and then form an emitter/sitter electrode that also serves as an emitter diffusion source and contacts the base diffusion region through the contact hole, and a sidewall is formed in the MOS transistor area. The seventh step is to perform ion implantation using the attached gate electrode as a mask to form a high concentration impurity region, and the fifth step is to perform heat treatment on the structure obtained in this seventh step. an eighth step of forming an emitter layer in the base diffusion region, a collector layer in the collector region, and a source/drain layer of an LDD structure in the low concentration and high concentration impurity regions by ion diffusion from the emitter diffusion source; It is characterized by including.

Furthermore, in the third method, a sidewall is formed in a separate post-process on at least a portion of a region where a base diffusion region is to be formed in a post-process in a collector region of a bipolar transistor area of the wafer. A first step of forming an insulating layer pattern with a thickness that remains after the RIE etching for the wafer is thicker than the thickness of the gate oxide film formed in another subsequent step; and a second step of forming a gate electrode on the PMOS transistor area via a gate oxide film, and performing ion implantation using the gate electrode formed in the second step of the NMOS transistor area as a mask,
The third step is to form a low concentration impurity region, the fourth step is to form sidewalls on both gate electrodes using FIIE etching technology, and the layer pattern described above is partially removed by IE etching in this fourth step. having an etched remaining layer pattern;
A fifth step of forming a base diffusion region in the collector region of the bipolar transistor region, and after providing a protective film in at least the NMO5 and PMOSMOS transistor regions, a gate electrode with a sidewall is used as a mask in the NMO8)-randisk region. The sixth step is to form a highly concentrated impurity region by performing ion implantation using the etching method.A contact hole is formed in this layer pattern without etching the underlying base diffusion region, and then,
A seventh step is to form an emitter electrode that also serves as an emitter diffusion source and contacts the base diffusion region through the contact hole on this layer pattern, and ion implantation is performed in the PMOS transistor area using the gate electrode with sidewalls as a mask. The structure obtained in the eighth step is heat-treated, and the above-mentioned structure is formed by ion diffusion from the emitter diffusion source formed in the sixth step. The present invention is characterized in that it includes a ninth step of forming an emitter layer in the base diffusion region, a collector layer in the collector region, and a source/drain layer of the LDD structure in the aforementioned low concentration and high concentration impurity regions.

(Operation) According to the first method of the present invention, in the fourth step, a layer pattern of the sidewall forming material is formed on the base diffusion region using RIE etching for forming the sidewall. Then, in a fifth step, a protective film is provided in the area for the MoS transistor, and then a concrete hole is provided in this layer pattern to form an emitter electrode. In the subsequent sixth step, a high concentration impurity region for a MOS transistor is formed by ion implantation.

According to this first method 1, during RIE etching for sidewall formation, the sidewall forming material layer partially remains as a layer pattern in at least the region where the emitter layer is to be formed in the base diffusion region. ,
The region where the emitter layer is to be formed is not etched.

Moreover, since this layer pattern is thicker than at least the gate oxide film, the gap between the emitter electrode and the base layer becomes smaller. Furthermore, since a thin protective film having a thickness different from that of this layer pattern is formed in a subsequent step, ion implantation in the MO3 element area will not be hindered.

Further, according to the second method, in the first step, even if RIE processing/etching is performed for sidewall formation at least in the bipolar transistor area, an insulating film that remains with a thickness thicker than the gate oxide film is formed. After providing layer 8 having
A base diffusion region is formed through this layer. Then, in a second step, this layer is etched to form a layer pattern. Thereafter, in a third step, a gate oxide film is provided and then a gate electrode is formed, and in a subsequent fifth step, sidewalls are formed. Then, in the sixth step, after providing a protective layer in the MOS transistor area, a contact hole is provided in this layer pattern to form an emitter electrode. In the subsequent seventh step, a high concentration impurity region for the MO3t transistor is formed by ion implantation.

According to this second method, during the RIE etching jig for sidewall formation, an insulating layer pattern with a thickness thicker than the gate oxide film is formed in at least the region where the emitter layer is to be formed in the base diffusion region. is formed, so that the region where the emitter layer is to be formed will not be etched.Furthermore, after forming the sidewall electrode, a thin protective film different from the layer pattern and capable of forming a MoS transistor is formed. Therefore, it does not interfere with ion implantation for forming M○S transistors.
Furthermore, since the layer pattern is thicker than at least the gate oxide film, the capacitance between the emitter electrode and the base layer is reduced.

Furthermore, according to the third method, in the first step, at least the bipolar transistor area has an insulating property that remains thicker than the gate oxide film even if RIE etching is performed for forming sidewalls. A layer is provided and then etched to form a layer pattern. Therefore, in the second step, a gate oxide film is provided and then a gate electrode is formed. After that, in the fourth step, a sidewall is formed, and in the sixth step, a protective layer is provided in the area for the MOS transistor, and then a high concentration impurity region is formed by ion implantation, and further, in the seventh step, this layer is formed. A contact hole is provided in the pattern to form an emitter electrode.

According to this third method, during the IE etching for sidewall formation, an insulating layer having a thickness thicker than the gate oxide film is formed in at least the region where the emitter layer is to be formed in the base diffusion region. Since the pattern is formed, the area where the emitter layer is to be formed will not be etched.Furthermore, after the sidewall is formed, a thin protective film different from the layer pattern and capable of forming a MoS transistor is formed. Therefore, it does not interfere with ion implantation for MO3h run transistors, and
Since the layer thickness is at least larger than the gate oxide film, the capacitance of the circle between the emitter electrode and the base layer becomes smaller. Furthermore, since the base diffusion region for the bipolar element is formed after the above-mentioned protective film is formed, the base width can be reduced.

(Embodiments) Hereinafter, preferred embodiments of the method for manufacturing an 8iCMO8 semiconductor device of the present invention will be described with reference to the drawings. Note that the figures merely schematically show the shapes, dimensions, and arrangement of each component to the extent that the present invention can be understood, and the present invention is not limited to the illustrated examples. Further, the various conditions listed in the examples described below are merely preferred examples.

Therefore, the present invention is not limited only to these conditions, and will be described with attention to a set of transistors constituting BiCMO3.

1 First of all, Figure 1 (A) to (N) of the sum' method! Reference is made to the first part of this invention.
A preferred embodiment of the manufacturing method will be described. In the drawings, hatchings and the like representing cross sections are partially omitted.

First, a wafer 100 is prepared. In this embodiment, the wafer 100 may be, for example, a P-type silicon substrate 102 with a resistivity of 1 oΩ·cm, but in this embodiment,
As shown in FIG. 1(A), this P-type silicon substrate 10
A bipolar transistor area 106 in the semiconductor body formed by providing an epitaxial layer 104 on the (100) plane of 2;
The wafer 100 has areas 108 and 110 defined for NM○S and PMO3I-rundisks.

In this example, as is well known, in the regions of the substrate 102 corresponding to areas 106 and 110, antimony sb is diffused from the surface to a depth of 5 um to provide an N0 buried layer 112 with a sheet resistance of 20 Ω/hole, and then this (10
0) On the surface, the specific resistance is 1.0Ωcm and the film thickness is 2.0u.
m, P-type boron (B) doped engineered taxial layer 10
4 and further includes a bipolar transistor area 10
6 and PMOS transistor area 110, respectively, continuously above the buried layer 1.12 such that the surface impurity concentration is 2×10” ions/cm3 at a diffusion depth of 2 um from the surface of the epitaxial layer 104. An N region 114 for forming a transistor is provided,
Thereafter, a field oxide film (here, a Si film) 116 having a thickness of about 7000 Å is formed by the LOCO3 method to obtain the wafer 100. This N region 114 is a collector region that will ultimately constitute the collector layer of the bipolar transistor. Note that in the following description, a transistor may be simply referred to as an element.

In the first step of this example, as in the conventional case,
Area 10 for bipolar transistors of this wafer 100
The base diffusion region 11 is located in a part of the collector region 114 of 6.
form 8. The base diffusion region 118 is formed by implanting P-type impurity ions, for example, B◆, into a part of the collector region at an acceleration voltage of 100 ev using any suitable conventional method, and then performing heat treatment to diffuse the region. Change to P type and form. The diffusion depth is set to 0.4 um and the surface impurity concentration is set to 5 x 10'' ions/cm3. This state is shown in FIG. 1(B).

Next, in the second step, as in the conventional method, the NM of 1°O of the wafer
Areas 108 and 110 for O3 and PMOS transistors
A gate electrode is formed thereon. For this purpose, first, the exposed surface of the wafer 100 is thermally oxidized or a gate insulating film (in this case, an oxide film of SiO2) 12o of about 20 OA is formed using a suitable technique (see FIG. C
)).

Subsequently, a polysilicon film (not shown) is formed over the entire wafer surface above the gate insulating film 120 by low pressure CVD.
was grown to a film thickness of 400 OA, and then N and PMOS were grown using the well-known photorin etching technology.
Gate electrodes 122 and 124 of the transistors are formed, respectively. The structure thus obtained is shown in Figure 1 (D
).

In the next third step, in the same way as before, NMO3)
- Form low concentration impurity regions 126 for forming transistor source/drain layers using self-line technology. Therefore, in this NMOS transistor area 108, using the gate electrode 122 made in the second step as a mask,
S ions are implanted to form N- impurity regions (source/drain regions).

The diffusion depth of this region 126 from the wafer surface is set to 0.2u.
m, and its surface impurity concentration is 4×1Q18 ions/cm3. The state of the structure in which the low concentration impurity region] 26 is formed in this manner is shown in FIG. 1(E).

Next, in the fourth step, the upper electrodes 122 of both gates are etched using RIE (reactive ion etching) technology.
and 124 as well as the base diffusion region 118 of the bipolar transistor area 106.
A layer pattern 128 (shown in FIG. 1H, which will be described later) of a sidewall forming material is formed thereon.

Therefore, as in the past, first, as a sidewall forming material layer 130, a PSG film containing, for example, 15% by weight of P2O5 is coated on the entire upper surface of the structure obtained in FIG. 1(D) using the CVD method. It is grown to a thickness of 4000A (FIG. 1(F)).

Subsequently, in the embodiment of the present invention, a portion of the sidewall forming material layer 130 is formed on at least a portion of the base diffusion region 118 formed in the first step and above the emitter diffusion layer to be formed in a subsequent step. In order to remain as a layer pattern, a mask pattern 132 made of a resist of an appropriate material is provided at corresponding locations on this material layer 130 (FIG. 1(G)). At this time, also in this invention, the base of the bipolar transistor In consideration of misalignment during formation of layers and emitter electrodes, and thus alignment accuracy, it is preferable to form this resist pattern 132 to be slightly larger than the area of the emitter layer on the wafer surface.

Thereafter, the sidewall material layer 130 is subjected to RIE.
On the other hand, anisotropic processing and ν titration are performed to form both gate electrodes 122.
and 124, and a layer pattern 128 of the sidewall forming material corresponding to the mask pattern 132, that is, PSG in this example (FIG. 1(H)'). The etching also etches the lower gate insulating film 120, and the wafer 100! Used as an etching stopper.

In this way, a layer cavity 128 is formed in the bipolar device area 106, with a portion of the insulating film 120 remaining unetched underneath. Further, due to this processing/etching, in the bipolar element area, the wafer surface corresponding to both the lead-out regions of the spacer contact and the collector contact, and the source/drain forming regions of both the MO5 elements is exposed. The appearance of the structure thus obtained is shown in FIG. 1(H).

In the next fifth step, an emitter electrode that also serves as an emitter diffusion source for the bipolar element is formed.

Therefore, first, the bipolar element area 106 acts as an etching resist film, and the MO3 element area tl
In ils 08 and 110, an oxide film 138, which acts as a protective film (BuOtect S) during ion implantation for forming source/drain regions, is mainly provided on the exposed surface of the wafer 100 in which the required regions are formed. . This oxide film 1
38, the structure shown in FIG. 1(H) was heated with dry oxygen (0
2) A heat treatment is performed in an atmosphere at a temperature of 950° C. for 30 minutes, and the film is grown to a normal film thickness of about 20 OA. Note that this oxide film covers not only the exposed surface of the wafer but also the gate electrode 1.
It also grows on the surface of 22. The state of the structure after the formation of this oxide film 138 is shown in FIG. 1(I).

After forming this oxide film 138, this layer pattern 128 has
Using well-known photolithography technology, base diffusion region 1
A contact hole 40 is formed, being careful not to etch the surface of 18 (FIG. 1(J)).

Thereafter, an electrode formation preliminary layer 142 is formed on the entire upper surface of the wafer 100 using a suitable electrode material. In this case, it is preferable that this preliminary layer 142 be a polysilicon film. This polysilicon film 142 is formed by normal low pressure CVD.
The film is grown to a film thickness of 200 OA. In that case, this polysilicon film 142 is grown so that it also contacts the base diffusion region 118 in the contact hole 140 provided in the layer pattern 125. After that, this polysilicon film 14
In contrast to 2, in the ion implantation method, ions, such as As ions, are used as a diffusion source for forming an emitter diffusion region, which will be described later. 4
2.0X10” ions/cm at 0KeV accelerating voltage
Implant at a dose of 2. The resulting structure is shown in FIG. 1(K).

Subsequently, this polysilicon film 142 is patterned to form an emitter electrode 44 of a bipolar element, which also serves as an emitter diffusion source, using well-known photolithography and etching techniques (see FIG. 1).

In the next sixth step, ion implantation is performed into the NMO5 and PMOS transistor regions 108 and 110, respectively, using the sidewalled gate electrodes 122 and 124 as masks, and mainly the high concentration impurity region 14 is implanted.
6.148 and 150.1527: Form. In this case, the ion implantation is performed separately in the areas for the NMO5 and PMO3 elements. First, in this embodiment, using an appropriate method, appropriate ions, for example, As ions, are applied at 40° C. to the regions where the collector contacts are to be taken out in the NMO3 element section tl 108 and the bipolar element section t'i 106.
Accelerating voltage of KeV and 1.2X1016 ions/cm2
Ion implantation is performed at a dose of 1 to form high concentration impurity regions 146 and 148 for source/drain regions and high concentration impurity region 154 for a collector contact extraction region.

Subsequently, suitable ions are applied to the base contact extraction area of the PMO5 element area 1]○ and the bipolar element area 106 at an accelerating voltage of 8F2''?70 KeV and a dose of 1.2 x 1015 ions/Cm2. Implantation is performed to form high concentration impurity regions 150 and 52 for source/drain regions and high concentration impurity regions 156 for base contact extraction regions. The appearance of the structure is shown in FIG. 1(M).

Next, in the seventh step, the required layer structures of the bipolar element and both MO3 elements are completed. Therefore, as usual, an interlayer insulating film is formed on the entire upper surface of the structure obtained in the sixth step.
58 is provided. This interlayer insulating film 158 is formed by, for example, CVD.
Film thickness 6000A containing 20% by weight of p2o by method
It is preferable to provide it as a PSG film. Next, this entire structure! At a temperature of 900'C, wet oxygen (
02) Perform heat treatment for 30 minutes in an atmosphere,
This PSG film 158 is flowed to planarize its surface, and at the same time, by this heat treatment, As is deposited from the diffusion source 44, which is the emitter electrode, into the base diffusion region 118.
The impurity is diffused and a part of this region turns into an N-type emitter us failure layer 160 with a depth of about 0.3 um from the surface of the wafer 100, and this base diffusion region t'5+11
8 is the collector region] 14 and expands from the initial diffusion depth of 0.4 um to 0.6 um to form the base layer 162.
In addition, the collector region 1]4 is also the collector layer 164
Further, the high concentration impurity regions 154 and 156 become a collector contact extraction region 166 and a base contact extraction region 168, respectively. Furthermore, by this heat treatment, the NMOS transistor 1i10
8 low concentration and high concentration impurity regions] 20, 146 and 1
48 are slightly enlarged by diffusion, so that the source and drain layers 170 and 1 of the LDD structure are formed in these regions.
It becomes 72. Also, the area 110 for PMOS transistor
Similarly, the high concentration impurity regions 150 and 152 are slightly expanded by diffusion, and the source and drain layers 174 and 1
It becomes 76. The appearance of the structure thus obtained is shown in FIG. 1 (N).

Next, although not shown in the drawings, a BiCMO3 semiconductor substrate is formed by forming openings for interconnection of each element, forming necessary electrodes, etc. using well-known techniques. Further explanation will be omitted.

According to this first method, the sidewalls 134 and 13
6, the sidewall forming material layer 130 partially remains as a layer pattern 128 in at least the region where the emitter layer 160 is to be formed in the base diffusion region 118. The region to be formed is not etched, and since the layer pattern 128 is thicker than at least the gate oxide film 120, the capacitance between the emitter electrode 144 and the base layer 162 is small. Become. In addition, since a thin protective film 138 having a different thickness from that of the layer pattern 128 is formed in a later process, ion implantation in the MO5 element area 108 and 110 can be easily performed. ! I won't come.

In addition, in the embodiment described above, the emitter and base PN1
Since the design is such that the 4 combined capacitance c capacitance, junction depth, carrier concentration, and other conditions are unchanged from the conventional one, the capacitance @C,=8.6 fF is the same as the conventional one. However, unlike the conventional 20OA, the distance d between the emitter electrode 144 and the base layer 162 is as thick as at least 4000A in the case of the present invention. The capacitance Cox due to the wA cotton layer is Cox” 1, 40 f F, and as a result, the capacitance between the base and the top and bottom is CyEl (tCyE= 1
0. It becomes OffF. This capacity is the conventional capacity C,,=3
This is about 27% lower than 6.5fF. From this fact, it can be understood that the cutoff frequency-emitter current (FT IE) characteristics are greatly improved in the low current range. F□ of BiCM○S semiconductor device obtained by the manufacturing method of this example
- The measurement results of the mechanical properties are shown in FIG. 5 by curve A.

Next, with reference to FIGS. 9(A) to (○), a preferred embodiment (difficulties) of the second manufacturing method of the present invention will be explained. The illustrations are shown with some hatching etc. omitted. In addition, in the explanation of each manufacturing process stage, explanations of technical matters that overlap with those explained with reference to Fig. 1 may be omitted unless specifically mentioned. Components that are substantially the same as those shown in FIG. 1 will be described with the same reference numerals, and detailed description thereof will be omitted unless specifically mentioned.

In this case, a wafer 100 similar to that described in FIG. 1(A) is prepared (FIG. 9(A)).

In the first step of this embodiment of the invention, the wafer 1
Area 106 for at least bipolar transistors of 00
An insulating layer 200 of a suitable material is provided thereon. This layer 200 can also be, for example, a silicon oxide film. This oxide film 200 is herein referred to as a base oxide film.

This base oxide film 200 is once grown on the entire upper surface of the evaporator 100 using an appropriate technique. The film thickness of the base oxide film 2o○ at this time is such that it remains sufficiently thick when RIE processing and nitching are performed for sidewall formation in the later process, and the remaining film thickness is further increased in the subsequent process. It is provided with a film thickness of 2000 Å, for example, which is thicker than the thickness of a gate oxide film formed in a separate process. Note that as the layer 200 having insulating properties instead of the base oxide film, for example,
It can also be a polysilicon layer with a silicon oxide film formed on its surface. A structure provided with such an insulating layer 200 is shown in FIG. 9 CB).

Next, through this layer 200, ion implantation and thermal diffusion are performed under the same conditions as in the case of FIG.
A base diffusion region 118 is formed with a diffusion depth of . This state is shown in FIG. 9(C).

Next, in a second step, an insulating layer pattern is formed on at least a portion of this hemispherical diffusion region 118. In the case of this embodiment, the base oxide film 200 is patterned to form a layer pattern 202 using an ordinary photorin etching technique, as shown in FIG. 9(D).
You will get a structure as shown in . At this time, in the embodiment of the present invention as well, the layer pattern 202 is set slightly larger than the area of the emitter layer on the wafer surface, taking into account misalignment and alignment accuracy when forming the base layer and emitter electrode of the bipolar transistor. It is preferable to form it in a larger size.

Next, in this example, a film with a thickness of 20 mm was applied to the entire upper surface of the wafer 100 using the same method and conditions as explained in FIG. 1(C).
Forming the gate oxide film 120 of OA (FIG. 9(E))
.

Subsequently, in a third step, a gate oxide film 120 is formed on the NMO3 and PMOS transistor areas 108 and 110 of the wafer 100. Through the gate electrodes 122 and 12
4 respectively.

The method and conditions for forming the gate electrodes 122 and 124 can be the same as those described with reference to FIG. 1(D). FIG. 9(F) shows the structure in which these gate electrodes 122 and 124 are formed.

Next, as shown in FIG. 9(G), in a fourth step, ions are implanted into this NMOS transistor area 108 using the gate electrode 122 made in the third step as a mask, and a low concentration An impurity region 126 is formed.

The ion implantation conditions in this case can be the same as those described with reference to FIG. 1(D).

Next, in a fifth step, sidewalls are formed on both gate electrodes using RIE etching technology. Therefore, in this example, for example, 15% of P2O5 was first applied to the entire upper surface of the structure obtained in FIG. 9(G) using the CVD method.
A PSG film containing % by weight is grown to a thickness of 4000 Å as a sidewall forming material layer 130 (FIG. 9(H)).

Subsequently, RI is applied to the sidewall forming material layer 130.
Both gate electrodes 122 are etched by anisotropic etching using the E method.
and 124, sidewalls 134 and 136 are formed. This etching also etches 120% of the lower gate insulating film and uses the wafer 100 as an etching stopper. At this time, the already formed layer pattern 2
Of course, the upper sidewall forming material layer 130 and this layer pattern 202 are also etched, but since this layer 202 is sufficiently thick, at least this layer 202 is thicker than the gate oxide film 120. The remaining layer thickness remains and becomes a layer pattern corresponding to the layer pattern 128 already described in FIG. 1(H). Also, by this etching, in the bipolar element area 106, both the base contact and collector contact extraction areas,
In both MO8 device areas 108 and 110, the wafer surfaces corresponding to source/drain formation regions are exposed, respectively.

The appearance of the structure thus obtained is shown in FIG. 9(I).

Next, in the sixth step, Fig. 1 (I) to Fig. 1 (L)
An emitter electrode that also serves as an emitter diffusion source for a bipolar element is formed through a process similar to that described above (therefore using similar techniques, conditions, etc.).

Therefore, first, the bipolar element area 106 acts as an etching stopper film, and the MO3 element area 106 acts as an etching stopper film.
8 and 110, a wafer 100 is formed in which an oxide film 138 which acts as a protective film during ion implantation for forming source/drain regions is formed in a required region with a normal film thickness of about 200A. (FIG. 9(J)).

Next, the formation edge of this oxide film 138, this layer pattern 1
28, a contact hole 204 is formed using the well-known photorin technique, taking care not to etch the surface of the underlying base diffusion region 118 (FIG. 9(K)).
.

Thereafter, a preliminary electrode formation layer 1428 is formed using a suitable electrode material such as polysilicon on the entire upper surface of the wafer 100 so that the contact hole 204 is also in contact with the base expansion region 118. Ions, such as As ions, which will become a diffusion source for forming an emitter diffusion region to be described later, are implanted into the polysilicon film 142 by an ion implantation method. The resulting structure is shown in FIG. 9(L).

Subsequently, this polysilicon film 142 is subjected to vacuuming to form an emitter electrode 144 of a bipolar element which also serves as an emitter diffusion source (FIG. 9(M)).

In the next seventh step, ions are implanted into the NMO3 and PMOS transistor regions 108 and 110 using the sidewalled gate electrodes] 22 and 124 as masks, and the high concentration impurity regions 14 are mainly implanted.
6.148 and 150.152. in this case,
The method, order, and other conditions for this ion implantation can be carried out in the same manner as in the case explained with reference to FIG. 1(M).

FIG. 9(N) shows the appearance of a structure obtained by forming such a high concentration impurity region.

Next, in the eighth step, the required layer structures of the bipolar element and both MO3 elements are completed. For this reason, Figure 1 (N)
With similar techniques, order, and other conditions as described in Section 9.
A structure as shown in the figure (○) is obtained. That is, the glabellar constriction membrane 158 is provided on the entire upper surface of the structure obtained in the seventh step in the usual manner, and then the entire structure is heat-treated to cause the PSG film 158 to flow to the surface. At the same time, through this heat treatment, As impurities are diffused into the base diffusion region 118 from the diffusion source 144, which is the emitter electrode, and a part of this region becomes
The base diffusion region 118 is changed into an N-type emitter diffusion layer 160 with a depth of about 0.3 um from the surface of the wafer 100, and the base diffusion region 118 is diffused into the collector region 114, and the initial diffusion depth is changed from 0.4 um to 0.3 um. The base layer 162 expands to 6 um, and the collector region 114 also becomes the collector layer 164, and furthermore, the high concentration impurity regions 154 and 1
56 are collector contact extraction regions 166, respectively.
and a base contact extraction region 168. Furthermore, due to this heat treatment, the low-concentration and high-concentration impurity regions 120, 146, and 148 in the NMOS transistor area 108 are similarly expanded to some extent by diffusion.
In these regions, the source and drain layers 170 of the LDD structure
and 172. In addition, the high concentration impurity regions 150 and 152 in the PMO8h transistor area 1]0 are similarly expanded to some extent by diffusion, and the source and drain layers 174
and 176. The state of the structure thus obtained is shown in FIG. 9 (◯).

Next, in the case of this embodiment as well, using well-known techniques (not shown), an 8iCMO3 semiconductor device is formed through the formation of openings for interconnection of each element, the formation of necessary electrodes, etc. A structure is formed, but detailed description thereof will be omitted.

According to this second method, the sidewall] 34 and 1
During the IE etching for forming the gate oxide film 36, an insulating layer pattern 202 having a thickness thicker than the gate oxide film 120 is formed in the base diffusion region 118 at least in the region where the emitter layer 160 is to be formed. Therefore, the region where the emitter layer 160 is to be formed will not be etched, and the sidewall 134 will not be etched.
After the formation of
Since a thin protective film 138 capable of forming an S transistor is formed, it does not interfere with ion implantation for forming a MOS transistor.

Further, the layer pattern 202 includes at least the gate oxide film 1
Since the film thickness is larger than 20, the capacitance between the emitter electrode 144 and the base layer 162 becomes smaller.

In addition, in the embodiment of the second method described above, the PN junction capacitance J between the emitter and the base is designed so that the junction depth, carrier concentration, and other conditions remain the same as before. Similar capacity is 41G, =8.6 fF. However, the distance d between the emitter electrode 144 and the base layer 162 is thick, at least about 200 OA, unlike the conventional 20 OA, as in the case of the second method. The capacitance C0X due to the dark insulating layer of 162 becomes C3x=2.79fF, and as a result, the base-emitter capacitance CyE1. tC
yi:=11, 4 fF. Therefore, in this case as well, this capacitance is the same as the conventional capacitance C, E = 36.5 fF.
This is a reduction of approximately 31% compared to the previous year.

From this fact, cutoff frequency - emitter current (FT-IE)
It can be seen that the characteristics are greatly improved in the low current range. Curve 8 in FIG. 5 shows the measurement results of the FT Iε characteristics of the 8iCMO8 semiconductor device obtained by the manufacturing method of this example.

3 Glue 1 Next, a preferred embodiment of the third manufacturing method of the present invention will be described with reference to FIGS. 10(A) to 10(P). In the drawings, hatchings and the like representing cross sections are partially omitted. Furthermore, in the description of each manufacturing process step, explanations of technical matters that overlap with those explained in FIGS. 1 and 9 may be omitted unless specifically mentioned. Also, the first
Components that are substantially the same as those shown in the figures and FIG. 9 will be described with the same reference numerals, and detailed description thereof will be omitted unless specifically mentioned.

In this case as well, a wafer 100 similar to that described in FIG. 1(A) is prepared (FIG. 10(A)).

In the first step of this embodiment of the invention, the wafer 1
On at least a part of the region where the base diffusion region is to be formed in the collector region 114 of the pibora transistor 11106 of No. 00 in a later step, it has an insulating property and is formed in another later step. A layer pattern 202 with a thickness thicker than the gate oxide film is formed (see FIG. 10(B)).
)).

Therefore, as explained in FIG. 9(8), in the case of this embodiment as well, the wafer 10 is
A layer (referred to as a base oxide film) 20C1 of an appropriate material having an insulating property is provided on at least the bipolar transistor area 106 of 0 (FIG. 10(B)), also in the case of the second embodiment. Similarly, the film thickness of the gate oxide film 200 at this time is such that it remains sufficiently thick when RIE processing and nitching are performed for forming sidewalls in a later process, and the remaining film thickness is Further, the film thickness is set to, for example, 200 OA, which is thicker than the thickness of a gate oxide film formed in a subsequent separate process.

Next, an insulating layer pattern is formed on at least a portion of the region where the base diffusion region is to be formed. In this embodiment, the base oxide film 200 is patterned to form a layer pattern 202 using conventional photolithography and etching techniques to obtain a structure as shown in FIG. 10(C). At this time, also in the embodiment of the present invention, the layer pattern 202 is set to be slightly larger than the area of the emitter layer on the wafer surface, taking into account misalignment and alignment accuracy when forming the base layer and emitter electrode of the bipolar transistor. It is preferable to form it in a larger size.

Subsequently, in a second step, gate electrodes 122 and 124 are formed on the NMO 8 and PMOS transistor areas 108 and 110 of the wafer 100 via a gate oxide film 120.
form each.

Therefore, first of all, in this embodiment as well, as shown in FIG.
and in the same manner and under the same conditions as explained in FIG. 9(E),
A gate oxide film 120 having a thickness of 20 OA is formed on the entire upper surface of the wafer 100 (FIG. 10(D)).

Next, the gate electrodes 122 and 124 are formed, and the formation method and conditions can be the same as those described in FIG. 1(D) and FIG. 9(F). FIG. 10(E) shows the state of the structure in which these gate electrodes 122 and 124 are formed.

Next, in a third step, ions are implanted into this NMOS transistor area 108 using the gate electrode 122 made in the second step as a mask to form a low concentration impurity region 126 (see FIG. )), the ion implantation conditions in this case can be the same as those described with reference to FIG. 1(E).

Next, in the fourth step, sidewalls are formed on both gate electrodes using the etching technique of the Japanese IE method in the same manner as in FIGS. 9(H) and (I) (FIG. 10(I)). H)) In this case as well, the part of the sidewall forming material layer 130 above the already formed layer pattern 202 and this layer pattern 202 are naturally etched, but if the thickness of this layer 202 is sufficient. Therefore, at least this layer pattern 202 remains thicker than the gate oxide film 120, and has a layer pattern (12) corresponding to the layer pattern already explained in FIG.
8 and 2o2).

Also, by this etching, as in the case of FIG.
In the eight element areas 108 and 110, the wafer surface corresponding to the source/drain formation region is exposed, respectively. The appearance of the structure thus obtained is shown in FIG. 10(H).

Next, in this embodiment, in the fifth step, the base diffusion region 118 is formed in the collector region 114 of the bipolar element section t12106 (FIG. 0 (J)). 9(J) and FIG. 9(I), the bipolar element area 106 acts as an etching stopper film, and the MO3 element areas 108 and 1
10, an oxide film 13 that acts as a protective film during ion implantation to form source/drain regions.
8 is mainly provided on the exposed surface of the wafer 100 where the required area is formed, with a normal film thickness of about 20 OA (
Figure 10 (I)), followed by Figure 1 (8) and Figure 9 (
A base diffusion region 118 is formed in the collector region 114 of the bipolar element area 106 by performing ion implantation and thermal diffusion under the same conditions as in case C) (FIG. 10(J)).
, the diffusion depth of this base diffusion region 118 is 0.4 μm.
It is preferable that

Next, in the sixth step, ion implantation is performed in the NMOS transistor area 108 using the gate electrode with sidewalls as a mask to form high concentration impurity regions 146 and 148 for forming source/drain layers.
@Formation and bipolar transistor discussion v41
Also in the collector region 114 of No. 06, a high concentration impurity region 154 for a collector contact extraction region is formed. In this case, ion implantation is performed by accelerating As ions at an acceleration voltage of 40Ke.
It is preferable to use V and a dose of 1.2xlO"/cm'. The structure obtained by forming such a high concentration impurity region is shown in FIG. 10(K).

Next, in the seventh step, an emitter electrode that also serves as an emitter diffusion source for the bipolar element is formed (Fig. 10 (N)).
).

Therefore, by using a well-known photolithography technique on the layer base 202 that has already been formed, the underlying base diffusion region 11 is
A contact hole 204 is provided while being careful not to etch the surface 8 (FIG. 10(L)).

Thereafter, a preliminary electrode formation layer 142 is formed using a suitable electrode material such as polysilicon on the entire upper surface of the wafer 100 so as to contact the contact hole 204 and the base diffusion region 118. 9(L), ions such as As ions, which will become a diffusion source for forming an emitter diffusion region to be described later, are implanted into this polysilicon film 142 by the ion implantation method. The resulting structure is shown in FIG. 10 (CM).

Subsequently, this polysilicon film 142 is patterned to form an emitter electrode 144 of a bipolar element, which also serves as an emitter diffusion source, using well-known photolithography, etching, and etching techniques (FIG. 10(N)).

Next, in an eighth step, ion implantation is performed in the PMOS transistor area 110 using the sidewalled gate electrode 124 as a mask to form high concentration impurity regions 150 and 152 for forming source/drain layers. , a high concentration impurity region 156 for a base contact extraction region is also formed in the base diffusion region 118 of the bipolar transistor area 106. In this case, the ion implantation is preferably performed at an acceleration voltage of BFz'' of 70 KeV and a dose of t1.2x 10''7 cm2. FIG. 10(0) shows the appearance of a structure obtained by forming such a high concentration impurity region.

Next, in the ninth step, the bipolar element and both MO3
Complete the required layer structure of the device. For this reason, Figure 1 (N
) A structure as shown in FIG. 10(P) is obtained using the same technique, order, and other conditions as described in . That is, an interlayer insulating film 158 is provided on the entire upper surface of the structure obtained in the eighth step in the usual manner, and then the entire structure is subjected to heat treatment to flow the PSG film 158 to the surface. Perform flattening. At the same time, this heat treatment causes As impurities to diffuse into the base diffusion region 118 from the diffusion source 144, which is the emitter electrode, and a portion of this region becomes an N-type emitter at a depth of about 0.3 um from the surface of the wafer 100. The diffusion layer 160 becomes the base layer 160, and the base diffusion region 118 (the base diffusion region 118) diffuses into the collector region 114 and expands from the initial diffusion depth of 0.4 um to 0.5 um to become the base layer 162, and the collector region 114. The collector layer 164 also becomes the high concentration impurity region 154.
and 156 are a collector contact extraction region 166 and a base contact extraction region 168, respectively. Furthermore, by this heat treatment, the low concentration and high concentration impurity regions 126, 146, and 148 of the NMOS transistor area 1 area 08 are similarly expanded to some extent by diffusion.
Therefore, these regions form the source and drain layers 170 and ]72 of the LDD structure. Also, the high concentration impurity regions 150 and 1 of the PMOS transistor section t110
52 is similarly expanded to some extent by diffusion to become source and drain layers 174 and 176. The appearance of the structure thus obtained is shown in FIG. 10(P).

Next, although not shown, the structure of the BiCMO8 semiconductor device is formed by forming openings for interconnection of each element, forming required electrodes, etc. using well-known techniques. Further explanation will be omitted.

According to this third method, the sidewalls 134 and 1
During the RIE process and nitching to form the gate oxide film 36, an insulating layer pattern 202 having a thickness thicker than the gate oxide film 120 is formed in the base diffusion region 118 at least in the region where the emitter layer 160 is to be formed. Since the emitter layer 160 is formed, the region where the emitter layer 160 is to be formed is not etched. Also, side wall 1
After forming the layers 34 and 136, a thin protective film 138 different from the layer pattern 202 and capable of forming a MOS transistor is formed, which supports ion implantation for forming an MO3i-transistor. The old pattern that came with 11 is also layered pattern 20
2 is thicker than at least the gate oxide film 120, so the capacitance between the emitter electrode 144 and the base layer 162 is reduced. Furthermore, after forming the above-mentioned protective film 138, the base diffusion region 1 for the pibora transistor is
18, the base width can be made smaller than in the case of manufacturing by the first and second methods.

In addition, in the embodiment of the third method described above, the depth of the capacitive junction of the emitter and the base, the carrier concentration, and other conditions are the same as before. The capacitance value C, which is similar to that, is 8.6 fF.

However, the distance d between the emitter electrode 144 and the base layer 162 is thicker, at least about 200 OA in the case of the present invention, unlike the conventional 20 OA.
The capacitance C0X due to the insulating layer between the emitter electrode 144 and the base layer 162 is C0,=2.79fF, and as a result, the base-emitter capacitance JI CT E is CtE=
It becomes 11.4fF. This capacity is the conventional capacity CTE=3
This is about a 31% reduction compared to 6.5 fF.

Furthermore, in this third method, the depth of the base layer is 0.5
um and shallower, so the base width wb is the conventional o, 35μ
m to 0.3 um, which is approximately 7 um from the conventional value.
Reduce to about 3%.

From this fact, continuous frequency - emitter current (F, -
It can be seen that the characteristics (IE) are greatly improved not only in the large current range but also in the low current range. Curve C in FIG. 5 shows the measurement results of the FT-IE characteristics of the BiCMO3 semiconductor device obtained by the manufacturing method of this example.

Furthermore, when we experimentally investigated the current amplification factor of the common emitter of the BiCMO5 semiconductor multi-semiconductor transistor manufactured by this third method, we found that as shown in FIG.
It was found that while the conventional current amplification factor was 80 to 400, according to the present invention, the variation was reduced to 90 to 110, which was extremely good. As a result, according to the present invention, the yield of BiCMO8 LSI can be improved.

The present invention is not limited to the embodiments described above, but is suitable for application when bipolar transistors and MOS transistors are fabricated on the same wafer.

(Effects of the Invention) As is clear from the above explanation, in any of the methods for manufacturing BiCMO3 semiconductor devices of the present invention, there is the following problem: ■ Capacitance due to the insulating layer between the emitter electrode and the base layer. Since the base layer can be made small and the base layer can be made shallow, a high-speed bipolar transistor can be formed.

■Furthermore, when forming the sidewall, the base oxide film is
However, since the underlying wafer surface in the area where the emitter electrode is formed is not etched, the depth of the base layer cannot be determined by heat treatment, and therefore the depth of the base layer cannot be made uniform. I can do it. As a result, the base width defined by (depth of base layer) - (depth of emitter layer) becomes uniform, so that the current amplification factor of the common emitter of the bipolar transistor becomes uniform.

[Brief explanation of drawings]

1A to 1N are manufacturing process diagrams showing a first preferred embodiment of the method for manufacturing a BiCMO8 semiconductor device of the present invention, and FIGS. FIG. 3 is a perspective view schematically showing the structure near the emitter electrode; FIG. 4 is a planar schematic showing the relationship between the emitter layer and the base layer. Figure 5 shows BiC manufactured by the present invention and the conventional method.
MO3 Semiconductor Lightning Semiconductor Device - LA Transistor FT-I
E characteristic curve diagram, FIG. 6 is a diagram showing a BiCMO8 logic gate, FIG. 7 is an explanatory diagram of the amount of etching of a silicon substrate in the conventional manufacturing method, and FIG. TaBiC
A distribution diagram of the current amplification factor of MO5 semiconductor snow lamination semiconductor snow lamination transistor, FIG. FIG. 10 is a manufacturing process diagram showing a third preferred embodiment of the BiCMO3 semiconductor device-rich semiconductor device method of the present invention. 100...Wafer, 102...Silicon substrate 104...Epitaxial layer 106-...Bipolar transistor story 1 or 108-
・・NMO3)-Landister area 110・-PMOS
Transistor area 112...buried layer, 11
4--Collector region 116--Field oxide film 118--Base diffusion region 120--Gate insulating film 122,124--Gate electrode 126--Low concentration impurity region 128,202--layer Pattern 130... Side wall forming material layer 132... Resist pattern 134, 136... Side wall 138... Oxide film 140, 204... Contact hole 142... Electrode forming preliminary layer 144...・Emitter electrode 146.148.150.152.154.156...
・High concentration impurity region 158--Interlayer insulating film, 60--Emitter diffusion layer] 62--Base layer, 164--Collector layer 166--Collector contact extraction region 16
8... Paster contact extraction area 170.1
74--Source layer 172.176--Drain layer. 200...layer having insulation properties

Claims (3)

[Claims] (1) LDD structure MOS with bipolar transistor and gate electrode with sidewalls on a silicon wafer
In manufacturing a semiconductor device comprising a transistor, a first step is to form a base diffusion region in a part of the collector region of the bipolar transistor region of the wafer, and to form a gate electrode on the MOS transistor region of the wafer. a second step; a third step of forming a low concentration impurity region in the MOS transistor area by ion implantation using the gate electrode as a mask; After providing the wall forming material layer, a mask pattern is provided on the sidewall forming material layer corresponding to at least a portion of the base diffusion region, and then a sidewall is formed on the gate electrode using an RIE etching technique. At the same time, a fourth step of forming a layer pattern of the sidewall forming material corresponding to the mask pattern, providing a contact hole in the layer pattern, and contacting the base diffusion region through the contact hole on the layer pattern. a fifth step of forming an emitter electrode that also serves as an emitter diffusion source; a sixth step of forming a high concentration impurity region in the MOS transistor area by ion implantation using a gate electrode with sidewalls as a mask; Heat treatment is performed on the structure obtained in the six steps,
Forming an emitter layer in the base diffusion region by ion diffusion from the emitter diffusion source, forming a collector layer in the collector region, and forming a source/drain layer of an LDD structure in the lightly doped and heavily doped regions. A method for manufacturing a semiconductor device, the method comprising: a seventh step. (2) LDD structure MOS with bipolar transistor and gate electrode with sidewalls on silicon wafer
In manufacturing a semiconductor device including a transistor, the remaining thickness of the RIE etching for forming sidewalls performed in a later process on at least the area for a bipolar transistor of the wafer is removed from the gate formed in another later process. a first step of forming a base diffusion region in a part of the collector region in the region after providing an insulating layer having a thickness greater than the thickness of the oxide film; a second step of forming a layer pattern by patterning the insulating layer; a third step of forming a gate electrode via a gate oxide film on the MOS transistor area of the wafer; and a third step of forming a gate electrode on the MOS transistor area of the wafer. a fourth step of forming a low concentration impurity region by ion implantation using the gate electrode as a mask, a fifth step of forming a sidewall on the gate electrode using RIE etching technology, and at least a MOS transistor. After providing a protective film on the surface of the area, a contact hole is provided in the layer pattern, and an emitter electrode that also serves as an emitter diffusion source is formed on the remaining layer pattern to contact the base diffusion region through the contact hole. a sixth step; a seventh step of forming a high concentration impurity region in the MOS transistor area by ion implantation using a gate electrode with sidewalls as a mask; and a structure obtained in the seventh step. heat treatment,
An emitter layer is formed in the base diffusion region by impurity diffusion from the emitter diffusion source, a collector layer is formed in the collector region, and a source/drain layer of an LDD structure is formed in the low concentration and high concentration impurity regions. A method of manufacturing a semiconductor device, comprising: an eighth step. (3) LDD structure MOS with bipolar transistor and gate electrode with sidewalls on silicon wafer
In manufacturing a semiconductor device comprising a transistor, a step is performed in a separate post-process on at least a portion of a region where a base diffusion region to be formed in a post-process is to be formed in the collector region of the bipolar transistor area of the wafer. a first step of forming an insulating layer pattern having a thickness that is thicker than the thickness of a gate oxide film to be formed in another subsequent step; A second step of forming a gate electrode via a gate oxide film on the N and PMOS transistor areas of the wafer, and forming a low concentration impurity region in the NMOS transistor area by ion implantation using the gate electrode as a mask. a fourth step of forming a sidewall on the gate electrode using RIE etching technology; and a bipolar transistor of the wafer, which remains after the fourth step and has an insulating layer pattern. After the fifth step of forming a base diffusion region in a part of the collector region of the NMOS transistor region and providing a protective film on at least the surface of the NMOS transistor region, a gate with sidewalls is formed in the NMOS transistor region. a sixth step of forming a high concentration impurity region by ion implantation using an electrode as a mask; a contact hole is provided in the layer pattern; and an emitter diffusion is formed on the layer pattern to contact the base diffusion region through the contact hole. a seventh step of forming an emitter electrode that also serves as a source; an eighth step of performing ion implantation into the PMOS transistor region using the gate electrode with sidewalls as a mask to form a high concentration impurity region; Heat treatment is performed on the structure obtained in the process,
An emitter layer is formed in the base diffusion region by impurity diffusion from the emitter diffusion source, a collector layer is formed in the collector region, and a source/drain layer of an LDD structure is formed in the low concentration and high concentration impurity regions. A method for manufacturing a semiconductor device, comprising a ninth step.