JP2820456B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION (FIELD OF THE INVENTION) The present invention, DOPOS (Do ped Po lysilicon Si licon) and bipolar transistor emitter structure, LDD having sidewalls with a gate electrode (Lightly Doped Drain)
The present invention relates to a method for manufacturing a semiconductor device including a MOS transistor having a structure.

(Prior Art) A BiCMOS semiconductor device is known as a device having both advantages such as high driving power and high speed of a bipolar transistor and advantages such as high integration and low power consumption of a CMOS device. For example, Document I: “Ultra High Speed MOS Device Ultra High Speed Digital Device Series” Baifukan).

Among such BiCMOS semiconductor devices, those having an LDD structure as a MOSFET constituting a CMOS device have been attracting attention because the integration degree is improved.・ EEE Transaction on Electron Device (IEEE T
RANSACTION ON ELECTRON DEVICE) Vol.ED-32, No.2, (1
985.2) ”and Reference III:“ IEJ Journal of Solid State Circuits (IEEE J
ounal of Solid-State circuits) Vol.SC-21, No.2,
(1986.34) ").

First, prior to the description of the present invention, a brief description will be given of a conventional manufacturing process of manufacturing a conventional bipolar transistor and a CMOS device having P and NMOS transistors having an LDD structure having a gate electrode with a side wall on the same wafer. Then, the problems of the conventional method will be described.

2 (A) to 2 (J) are manufacturing process diagrams for explaining a method of manufacturing a BiCMOS semiconductor device which is conventionally known and can be manufactured at low cost with a small number of processes. Each figure schematically shows a cross section of the structure obtained in the manufacturing stage. Normally, many BiCMOSs are built on one wafer, and the manufacturing process is performed on many such wafers at the same time.
The manufacture of BiCMOS will be described as a representative.

First, conventional as is well known, the P-type epitaxial layer 14 formed on the substrate 10 further embeds an N ⁺ -type buried layer 12 in P-type silicon substrate 10, then the epitaxial layer 14, the buried layer 12 An N-type collector region 16 is provided continuously on the upper side,
Next, a field oxide film (in this case, S
iO ₂ film) 18 to provide bipolar transistor area 20 and N
Wafer 26 (or base or structure) defining areas 22 and 24 for MOS and PMOS transistors, respectively.
Is prepared (FIG. 2 (A)).

Next, a P-type diffusion region as a base layer 28 of the bipolar NPN transistor is formed on the wafer 26 with a diffusion depth of 0.4 μm.
Then, a gate oxide film (SiO ₂ film in this case) 30 to be a gate insulating film of the MOS transistor is formed.
At this time, the oxide film of the same thickness as the gate oxide film 30 in the bipolar transistor region 20 (in this case SiO ₂ film) 32 is formed. This state is shown in FIG. 2 (B).

Next, after a polysilicon film is grown on the entire surface of the wafer 26 by a low pressure CVD method, the gate electrodes 34 and 36 of the NMOS and PMOS transistors are formed using a well-known photolithographic etching technique. Gate electrode
A low-concentration impurity region (in this case, N ^- type source / drain region) 38 is formed in the NMOS transistor area 22 by using a well-known self-alignment technique using the masks 34 and 36 as masks (FIG. 2). (C)).

Next, over the entire upper surface of the structure shown in FIG.
The P ₂ O ₅ weight concentration was set to 15 as a CVD film (insulating film) by the CVD method.
A PSG film 40 in which the weight% is obtained is grown (FIG. 2 (D)).

Next, the PSG film 40 is subjected to anisotropic etching by RIE (reactive ion etching) technology to form well-known side walls (sidewall oxide films) 42 and 44 on the side walls of the gate electrodes 34 and 36. I do. At this time, the portion of the gate electrode with the sidewall and the field oxide film
Area 20, NM for bipolar transistors, other than 18
The wafer surfaces of the OS and PMOS transistor areas 22 and 24 are exposed (FIG. 2E).

Next, heat treatment is performed on the structure shown in FIG. 2 (E) in a dry oxygen atmosphere to form oxide films 46, 48 and 50 on the exposed wafer surface and the polysilicon surface of the gate electrode. In this case, the base oxide film 46 in the bipolar transistor section 20 serves as an etching stopper at the time of etching in a later step, and both the MOS transistor sections 22 and 2
The oxide films 48 and 50 of 4 are films which respectively act as protective films (protection films) at the time of ion implantation for forming high concentration impurity regions for source / drain layers in a later step. Therefore, the thickness is set to about 200 ° so that the ion implantation is not impaired. The appearance of the structure obtained in this way is shown in FIG. 2 (F).

Next, the oxide film 46 of the bipolar transistor area 20 is formed.
Then, a window 52 for forming an emitter diffusion region is opened by using a well-known photolithographic etching technique to expose the wafer surface. Thereafter, a polysilicon film 54 is formed on the entire upper surface of the structure by a low pressure CVD method. Then, As (arsenic) ions are implanted into the polysilicon film 54 to form a diffusion source for forming an emitter diffusion region, thereby obtaining a structure shown in FIG. 2 (G).

Further, a diffusion source 56 for forming an emitter electrode and an emitter diffusion region for a bipolar transistor is patterned by using a well-known photolithography / etching technique to obtain a structure as shown in FIG. 2 (H). In this case,
Since the gate electrodes 34 and 36 are covered with the oxide films 48 and 50, they are not etched.

Next, using an ion implantation method, As ions are implanted into the NMOS transistor area 22 to form the low-concentration impurity region previously provided.
38 is partially changed to an N-type high concentration impurity region 58. The remaining low concentration impurity region is indicated by 38a. Subsequently, BF ₂ ⁺ is implanted into the PMOS transistor area 24 by ion implantation to form a high-concentration (P ⁺ type) impurity region 60, and a P-type impurity region 60 is formed in the base diffusion region 28 of the bipolar transistor area 20. ⁺
An N ⁺ -type collector contact region 64 is formed in the base contact region 62 and the collector region 16 to obtain a structure as shown in FIG. 2 (I).

Next, for example, as an interlayer insulating film 66 above the structure,
After the PSG film is provided by the CVD method, heat treatment is performed at 900 ° C. for about 30 minutes in a wet oxygen atmosphere. By this heat treatment, the PSG film 66 flows and flattening of the surface proceeds. At the same time, the respective regions containing impurities also diffuse and expand.
Due to this enlargement, the base diffusion region 28 is reduced from the initial 0.4 μm.
The base layer 68 diffuses deeply to 0.6 μm to become the base layer 68, the base contact region 62 becomes the base contact layer 70, the collector contact region 64 becomes the collector contact layer 72,
As from the diffusion source 56 into the base diffusion region 28 and thus the base layer 68
Impurities diffuse to form emitter layer 74. The collector region 16 in which these layers are formed becomes the collector layer 80.

Further, by this heat treatment, the low-concentration and high-concentration impurity regions 38a and 58 become a source or a drain (hereinafter, referred to as a source / drain) 76, and similarly, the high-concentration impurity region 60 becomes a source / drain layer 78. The appearance of the structure obtained in this way is shown in FIG. 2 (J).

Next, although not shown, as is well known, a contact hole for wiring connection between each transistor is formed, and an electrode is formed of a metal such as aluminum or other suitable material to form a BiCMOS.
Complete the semiconductor device.

(Problems to be Solved by the Invention) However, the BiCMOS semiconductor device having the structure manufactured by such a conventional method has two problems as described below.

Due to limitations in the manufacture of BiCMOS semiconductor devices, the bipolar transistor cannot be operated at a sufficiently high speed as compared with the case where the bipolar transistor is manufactured alone.

The variation in the current amplification factor of the formed bipolar NPN transistor is so large that the yield of LSI cannot be improved.

Hereinafter, these points will be briefly described with reference to a completed model of the bipolar transistor shown in FIGS. 3 and 4. FIG. 3 is a model diagram schematically showing, on an enlarged scale, a portion of the base layer 68, the emitter layer 74, the base oxide film 46, and the emitter electrode 56 made of polysilicon on the collector layer 80 of the bipolar transistor. FIG. 4 is a model diagram schematically showing the position and size relationship of the base layer 68 and the emitter layer 74 on the surface of the wafer 26. The boundaries 82 and 84 respectively contact the surface.
Indicated by

 First, the problem will be described.

Generally, the operational speed of a bipolar transistor, the current gain-bandwidth product or cutoff frequency (hereinafter, referred to as F _T.) Is known to be a Daito indeed fast. And this
It is known that F _T is given by 1 / 2πF _T = τ _e + τ _b + τ _x + τ _c (1) (for example, Document IV “Ultra High-Speed Digital Device Series 1 Ultra High-Speed Bipolar Device” Baifukan). In the expression (1), τ _{e in} the first term is a charge / discharge time constant of the emitter-base junction, τ _{b in} the second term is a base time constant, τ _{x in} the third term is a collector / depletion layer carrier transit time, and The fourth term τ _c is a base-emitter junction charge / discharge time.

Then, regarding this F _T , τ of the second term of the above equation (1)
_b (base time constant) is a key point (Ref.
Page 15), τ _b is given by τ _b = W _B ² / nD _B (2) Here, W _B is base width, n represents a constant that depends on the minority carrier distribution in the base, D _B is the diffusion constant of minority in the base carrier. Accordingly W _B is F _T becomes That enables high-speed operation greatly square relationship if narrow. In general W _B depends on the depth of the case base layer has a constant current amplification factor becomes narrower as it is shallow.

However, in the conventional manufacturing method described with reference to FIG. 2, since the base layer is formed before the gate of the MOS transistor is formed, even if the depth of the base layer is 0.4 μm immediately after the formation, the steps after the gate are formed. 0.6 by heat treatment during
It becomes deep down to μm. As a result, F _T could not be formed only bipolar transistor of about 4.5GHz.

Regarding F _T , especially in a low current region, τ _e (charge / discharge time constant of the emitter-base junction) in the first term of the above equation (1)
Is known to be dominant (page 45, line 9 of document IV). This τ _e is given by τ _e = kT / (qI _E × C _TE ) (3) Here, _CTE is the base-emitter capacitance, k is the Boltzmann constant, q is the amount of charge, T is the temperature (K), and _IE is the emitter current. Thus the temperature to allow F _T increases i.e. speed operation higher the C _TE decreases if constant.

This base-emitter capacitance _CTE is shown in FIG.
PN junction capacitance C _J between emitter layer 74 and base layer 68 and capacitance C of base oxide film 46 between emitter electrode 56 and base layer 68
It is known that this is given by equation (4) by _OX .

In _{C TE = C J + C OX} ... (4) Here, the dielectric constant of the silicon epsilon, the dielectric constant of air epsilon
_O , electric charge q, Fermi potential between emitter and base
V _{bi (EB)} Given by On the other hand, C _OX is the thickness of the oxide film 32 is d, a result the dielectric constant of SiO ₂ ε, C _OX = (opposing area between the emitter electrode and the base _{layer) (εε O / d) ×} ... (6 ).

Therefore, in the model of FIG. 4, this capacitance _CTE is obtained by calculation. Emitter area (W ₁ ×
W ₂ ) is set to 2 μm × 5 μm, and assuming that the misalignment margin W ₃ in the mask alignment step for forming the emitter layer 74 in the base diffusion region 28 (corresponding to the base layer 68) is 1 μm as usual, the boundary 84 Enclosed area ｛(W ₁ + 2W ₃ ) × (W ₂ +2
W ₃ )｝ is 4 μm × 7 μm. First, for C _J ,
Base carrier concentration of the emitter junction of the base layer 68 N _B is usually about 3 × 10 ¹⁷ ions / cm ^3, the depth of diffusion of the emitter layer 74 is for the normal 0.3μm about, also, V
_{If bi (EB)} is 0.7V and ε = 12, C _J = 8.6fF. On the other hand, as for C _OX, the thickness of the SiO ₂ film 32 is 200 ° as described above, and its relative dielectric constant ε is 3.5, so that C _OX = 27.9 fF. Therefore, the value of C _OX is about 10 times larger than the value when the bipolar transistor is manufactured alone. Then, C _TE = C _J + C _OX = 36.5 fF, which is larger than the C _{TE of the} bipolar transistor alone, so that τ _{e in} equation (1) also becomes large, and therefore, the high speed of the bipolar transistor in the low current region. There is a problem that the property is impaired.

As a first measure to reduce the value of C _OX , the base oxide film 4
Although a method of increasing the thickness d of 6 is conceivable, in the conventional method, as described with reference to FIG. 2 (B), since the oxide film for forming the gate oxide film is used as it is, this oxide film is thickened. Then, the source described in the step of FIG.
There is a disadvantage that ions of As (arsenic) and B (boron) are not implanted by ion implantation for forming the low concentration impurity region 38 for the drain layer.

Further, as a second countermeasure, there is a method to reduce the area facing the base layer of the emitter electrode, With this method, or there is only eliminated to reduce the margin W ₃ misalignment during mask alignment, this When the W ₃ is reduced, there is a disadvantage that it becomes impossible to form the emitter layer in misalignment.

In general, BiCMOS using devices with BiCMOS structure
A gate array or the like often comprises a circuit forming element such as a two-input NAND as a composite circuit of a bipolar transistor and a MOS transistor, as shown in FIG. 5 (refer to the literature "Transactions of the Institute of Electronics, Information and Communication Engineers c" (1988.9) quoted from p.1250) R
Regardless of the type, N type, or D type of BiCMOS logic gate, the MOS transistor drives the base current of the bipolar transistor in the final stage. Since MOS transistor is small driving capability, very small current only be supplied at the rising edge of the switching of the bipolar transistor, therefore, switching is faster the higher the cutoff frequency F _T in the low current region of the bipolar transistor. Such From point of view, it is desired that a higher cut-off frequency F _T of low emitter current region.

 Next, problems will be described.

As described above, in the above-described conventional method of providing a gate electrode with a sidewall in order to make an MOS device have an LDD structure, as described with reference to FIGS. After formation, a CVD film, for example, a PSG film 40 is provided once on the entire surface of the wafer, and then this P
The SG film 40 is anisotropically etched. However, a uniform thickness (usually about 4000 mm)
Although the PSG film 40 is provided, the thickness varies between 3% and 5% at the center portion and the edge portion of the same wafer. In addition, such a thickness variation occurs between the wafers. On the other hand, the RIE etching rate varies about 3 to 10% not only within the same wafer but also between different wafers. FIG. 5 shows the state of the variation in the etching amount when a plurality of silicon wafers are simultaneously etched for an appropriate time by the RIE etching. In FIG. 6, the frequency is plotted on the horizontal axis and the etching amount is plotted on the vertical axis. From this experimental result, it can be understood that the amount of etching of the wafer has reached several Å to a maximum of 200 Å.

By the way, for example, a 4000 .ANG. Thick CVD film (such as a PSG film 40 which is an insulating film shown in FIG. 2D) is formed on both MOS transistor regions 22 and 24 of the wafer except for the sidewalls 42 and 44. If this occurs, the protection oxide films 48 and 50 (FIG. 2 (F)) at the time of ion implantation to be formed in a later step will have variations. As a result, the depth of the high-concentration impurity regions 58 and 60 also varies, which affects the characteristics of the MOSFET. In order to avoid such a situation, the RIE etching time is usually controlled. However, if there is a variation in film formation of ± 5%, in order to perform etching so that the PSG film 40 does not remain on the wafer except for the side wall, it is assumed that the maximum thickness of the PSG film 40 is 4200 °, and the standard etching time That
An additional 10% to 30% overetch time needs to be added. Assuming that the maximum thickness of the PSG film 40 in the MOS transistor regions 22 and 24 is 4200 ° and the minimum thickness of the PSG film 40 in the bipolar transistor region 20 is 3800 °, FIG. In the step, the surface of the base diffusion region 28 is
There is a possibility that the base layer 68 will be etched away by 400 °, and as a result, the depth of the final base layer 68 in FIG. 2 (J) will be 0.56 μm. In this way, the PSG of this area 20 can be used not only between the same wafer but also between different wafers that are processed simultaneously.
If the film 40 has a maximum thickness of 4200 mm, the diffusion depth is 0.6 μm.
In contrast, when the minimum film thickness is 3800 mm, the depth becomes 0.04 μm (400 mm) deeper and the variation is 7 mm.
%.

However, as is well known, the current amplification factor of grounded emitter is strongly dependent on the total number of holes in the base width W _B and base layer, also, the base width W _B is contacted with the emitter layer 74 of the emitter electrode 56 Emitter layer 74 and base layer directly under the part
Since it corresponds to the distance perpendicular to the wafer surface between the junction boundary with 68 and the junction boundary between base layer 68 and collector layer 80, W _B = (base depth) − (emitter depth) Given. As described above, since the depth of the emitter layer is normally set to 0.3 μm, the base width W _B1 is 0.3 μm at the maximum thickness of the PSG film 40 described above, while the base width W _B2 is at the minimum thickness. W _B2 / W _B1 = 0.8
Therefore, there is a 20% variation. In the base layer 68, since the hole carriers are distributed unevenly in the emitter layer 74 side, it is turned into slightly base width W _B, and thus the current amplification factor of grounded emitter is large varies.

FIG. 7 is a diagram showing a state of the variation of the current amplification factor, and the vertical axis indicates the current amplification factor. Due to such variations in the current amplification factor, the yield of the BiCMOS LSI decreases.

Therefore, an object of the present invention is to eliminate the possibility that the base diffusion region of the bipolar transistor area is etched by RIE etching for forming a sidewall on the gate electrode of a MOS transistor, and furthermore, the distance between the emitter electrode and the base layer is reduced. It is an object of the present invention to provide a manufacturing method capable of reducing the oxide film capacity (the above-mentioned C _OX ).

According to the present invention, a bipolar transistor is provided in a first region on a surface of a semiconductor substrate of a first conductivity type, and an LDD structure is provided in a second region. In a method of manufacturing a semiconductor device having a MOS transistor, after forming a gate oxide film, a gate electrode and a sidewall of the gate electrode in the second region, a first method for forming a source and a drain of the MOS transistor is performed. Forming an oxide film with a predetermined thickness on the second region and the first region; and forming a first oxide film formed on the first region in the first region. A step of increasing the thickness of the portion including the region where the emitter is to be formed by the LOCOS method to form a second oxide film, and a predetermined region of the semiconductor substrate including a portion below the second oxide film. The bi-port Forming a base of the transistor, the second oxide layer, said emitter formation region above to form a window for exposing, the window and the second peripheral of the window
Forming an emitter electrode on the oxide film.

(Operation) According to the method of manufacturing a semiconductor device of the present invention, the following operation can be obtained.

... When viewed in the order of steps, the base layer is formed in a later step as compared with the conventional case, so that the number of heat treatments is reduced, and as a result, the depth of the base layer becomes smaller than in the conventional case.

... Since the base layer is formed after the formation of the gate electrode with the sidewall is completed, the base layer is not etched at all by RIE when the sidewall is formed. For this reason, the variation in the depth of the base layer becomes very small, so that the variation in the base width can be made very small.

... A base oxide film having a thickness larger than the thickness of the protection oxide film is formed in a region slightly wider than the region where the emitter layer is to be formed on the wafer, and then the region where the emitter layer is to be formed is exposed on the base oxide film. To form a second window. The remaining portion of the base oxide film becomes an insulating film which is sandwiched between the emitter electrode and the base layer at an edge portion of the emitter electrode and constitutes the capacitance C _OX . However, the thickness of the base oxide film is sufficiently thicker than that of the conventional protected oxide film (10 times thicker in the example of the embodiment), so that the value of C _OX becomes very small. Of course, this base oxide film (second oxide film) is
Since the second oxide film is formed by the method, a second oxide film having a uniform film thickness and a stable relative dielectric constant (good reproducibility of the relative dielectric constant) is obtained as compared with the case of using another film forming method such as a CVD method. Can be

(Embodiment) Hereinafter, a preferred embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. The following embodiment is a BiCMO having a bipolar transistor having a DOPOS emitter structure on a silicon wafer and P and NMOS transistors having an LDD structure having a gate electrode with a side wall.
An example in which the present invention is applied to the manufacture of an S semiconductor device will be described. However, the manufacturing method of the present invention is not applied only to the manufacture of this semiconductor device. For example, it is apparent that the present invention can be applied to the manufacture of a BiMOS semiconductor device having only a PMOS or NMOS transistor having an LDD structure in which a MOS transistor has a gate electrode with a sidewall. Further, the drawings used in the following description merely schematically show the shapes, dimensions, and arrangements of the respective components to the extent that the present invention can be understood, and the present invention is limited only to the illustrated examples. is not. Further, the conditions given in the embodiments described below are merely preferable examples. Therefore, the present invention is not limited only to these conditions.

1 (A) to 1 (N) show a method according to the present invention.
FIG. 9 is a diagram for describing the manufacturing procedure of the BiCMOS, and is a process diagram showing a state of the device in a main process with a cross-sectional view.
In the drawings, hatching or the like representing a cross section is partially omitted.

First, a wafer 100 is prepared. In this embodiment, the wafer 100 may be, for example, the P-type silicon substrate 102 having a specific resistance of 10 Ω · cm, but in this embodiment, as shown in FIG. (Ten
0) A region 10 for a bipolar transistor corresponding to a first region is provided on a semiconductor body having an epitaxial layer 104 provided on a surface.
6. The wafer 100 is the one in which the NMOS and PMOS transistor areas 108 and 110 corresponding to the second area have been defined. In this example, as is well known, antimony (Sb) is diffused to a depth of 5 μm from the surface of each of the regions corresponding to the areas 106 and 110 of the substrate 102 to provide an N ⁺ buried layer 112 having a sheet resistance of 20Ω / □. , And then on the (100) face of this substrate 102,
A boron (B) -doped P-type epitaxial layer 104 having a specific resistance of 1.0 Ωcm and a film thickness of 2.0 μm is provided, and is further provided on the upper side of the buried layer 112 in the bipolar transistor area 106 and the PMOS transistor area 110, respectively. Then, N regions 114 for forming respective transistors are provided so that the surface impurity concentration becomes 2 × 10 ¹⁶ ions / cm ³ at a diffusion depth of 2 μm from the surface of the epitaxial layer 104, and then the film thickness is determined by the LOCOS method. This wafer 100 is obtained by forming a field oxide film (SiO ₂ film here) of about 7000 °.

First, a gate electrode with a sidewall is formed on the wafer 100 thus prepared as described below.

First, a gate oxide film (SiO ₂ film) 118 serving as a gate insulating film of NMOS and PMOS transistors is formed to a thickness of 200 ° on the wafer 100 by a known method such as a thermal oxidation method. At this time, an insulating film (SiO ₂ film) 120 is formed to a thickness of 200 ° also in the bipolar transistor area 106 of the wafer 100 (FIG. 1B). Subsequently, the gate insulating film 118
Then, a polysilicon film (not shown) is once grown to a thickness of 4000 に よ っ て by a low pressure CVD method over the entire surface of the wafer on which the insulating film has been formed, and then, using a well-known photolithographic etching technique, the N and PMOS transistors are formed. Gate electrode 12
2 and 124 are formed respectively. Furthermore, the low-concentration N ^- drain region 1 of the NMOS transistor having a surface concentration of 4 × 10 ¹⁸ ions / cm ³ and a diffusion depth of 0.2 μm is formed by using a self-alignment technique.
Form 26. The structure obtained in this way is shown in FIG. 1 (C).

Subsequently, by a well-known CVD method, for example, as a sidewall forming material, the structure shown in FIG.
A PSG film 128 having a weight concentration of P ₂ O ₅ of 15 Wt% is formed to a thickness of 4000 ° (FIG. 1 (D)).

Subsequently, the PSG film 128 is etched by anisotropic etching using a well-known RIE (reactive ion etching) method so as to remain only on the side wall portions of the gate electrodes 122 and 124. As a result, sidewalls 130 and 132 can be formed, and further, the bipolar transistor area 106 of the wafer 100, the NMOS and PMOS transistor areas 108 and
110 is exposed (FIG. 1 (E)).

The wafer 100 on which the gate electrodes 122 and 124 with the sidewalls have been formed is left in a dry oxygen atmosphere at, for example, 950 ° C. for 30 minutes.
134 is formed (FIG. 1 (F)). This oxide film 134 functions as an etching stop layer at the time of etching for forming a window in an oxygen impermeable film for forming a base oxide film to be performed later, and also for forming an emitter electrode of a bipolar transistor to be performed later. Function as an etching stop layer during polysilicon etching, and
It has a function as a protection oxide film for ion implantation for forming source / drain layers of a MOS transistor.
Hereinafter, this oxide film 134 is referred to as a first oxide film or a protected oxide film 134.

Next, for example, a Si ₃ N ₄ film 136 as an oxygen impermeable film is formed to a thickness of 1000 ° on the entire surface of the wafer 100 on which the protection oxide film 134 is formed by a known CVD method (FIG. 1 (G)). ). Subsequently, the wafer 100 of the Si ₃ N ₄ film 136 is
A window 136a is formed in the Si ₃ N ₄ film 136 by removing a region on the surface which is slightly larger than the region corresponding to the region where the emitter layer is to be formed (FIG. 1 (H)). The oxygen impermeable film is made of Si ₃ N
_A film other than the _four films, for example, a polysilicon film may be used.

Next, in a partial region of the wafer 100 exposed from the above-described window 136a, the above-described protection oxide film 13 is formed as a second oxide film.
In this example, a base oxide film 138 having a thickness of 2000 mm is formed by the LOCOS method, and then a Si ₃ N ₄ film 136 is formed.
Is removed. Subsequently, the base oxide film 138 of the wafer 100
A base layer 140 is formed on a predetermined portion including the lower portion, that is, a portion of the bipolar transistor area 106. The base layer 140 is formed by implanting P-type impurity ions, for example, B ⁺ into the above-described predetermined portion at an acceleration voltage of 100 Kev by a conventional arbitrary suitable method, and then performing heat treatment to diffuse the portion, thereby changing the portion to P-type. Form. In this embodiment, the diffusion depth is 0.4 μm.
And the surface impurity concentration is 5 × 10 ¹⁷ ions / cm ³ .
Subsequently, using an ion implantation method, the NMOS transistor area
As (arsenic) is implanted into the source / drain formation region 142 at 108 and the collector contact extraction region 144 at the bipolar transistor region 106 under the conditions of an acceleration voltage of 40 KeV and a dose of 1.2 × 10 ¹⁶ ions / cm ³ . This state is the first
It is shown in FIG. In FIG. 1 (I), reference numeral 146 denotes a base contact take-out region. The diffusion depth of the base layer in the vicinity of the base contact extraction region 146 is deeper than the other base layers because the protection oxide film 134 is on the upper side and the film thickness is thinner than the base oxide film 138. In the illustrated example, they are shown as having the same depth.

Next, a second window 138a for exposing the region where the emitter layer is to be formed is formed in the base oxide film 138 having an area slightly larger than the region where the emitter layer is to be formed on the wafer by a known lithography technique and etching technique. (FIG. 1 (J)).

Next, the base oxide film 13 on which the second window 138a is formed
An emitter electrode forming material 148 containing an emitter layer forming diffusion source on the wafer 100 including
Is formed (FIG. 1 (K)). The emitter electrode forming material 148 of this embodiment is formed by forming a polysilicon film having a thickness of 2000 減 圧 by a low pressure CVD method, and then adding 2.0 (10 ¹⁶ ions / cm ³ ) to the polysilicon by ion implantation. It is formed by injecting.

Next, the above-mentioned emitter electrode forming material 148 is processed by a well-known photolithography technique and etching technique so that it remains over an area slightly larger than the second window 138, and the emitter layer 148 also serves as an emitter layer diffusion source. Electrode 14
8a is formed (FIG. 1 (L)).

Next, the PMOS transistor area 11 is formed by ion implantation.
BF ₂ ⁺ is applied to the expected source / drain region 150 of 0 and the base contact extraction region 146 of the bipolar transistor area 106 at an acceleration voltage of 70 KeV and a dose of 1.2 × 10 ¹⁵ ions.
/ cm ³ is selectively implanted (FIG. 1 (M)).

Next, an interlayer insulating film is formed on the structure shown in FIG.
Form 152. In this embodiment, the interlayer insulating film 152 is
For example, a film thickness 6 containing 20% by weight of P ₂ O ₅ formed by a CVD method.
It is a PSG film of 000Å. Then, the entire structure is
A heat treatment is performed at a temperature of 0 ° C. for 30 minutes in a wet oxygen (O ₂ ) atmosphere, and the PSG film 152 is caused to flow to planarize the surface. At the same time, as a result of this heat treatment, As impurities diffuse into the base layer 140 from the emitter electrode 148a also serving as a diffusion source for the emitter layer, and a portion of the base layer 140 is N-type having a depth of about 0.3 μm from the surface of the wafer 100. And the base layer 140 diffuses into the N region (collector region) 114 to form an initial diffusion depth.
Spread from 0.4 μm to 0.5 μm. Further, by this heat treatment, the source / rain formation regions 142 and 150 into which the impurity ions have been implanted become the source / drain layers 142a and 150a.
In addition, the collector contact extraction region 144 is a collector contact extraction layer 144a, and the base contact extraction region 146 is a base contact extraction layer 146a. The appearance of the structure obtained in this way is shown in FIG.

Next, although not shown, the structure of the BiCMOS semiconductor device is formed by using a well-known technique through forming an opening for wiring connection of each element, forming necessary electrodes, and the like. Detailed description is omitted.

According to the semiconductor device obtained by the method of this embodiment, the base depth can be 0.5 μm, which is 0.1 μm smaller than the conventional depth. Therefore, (the base depth) - base width W _B defined by (emitter depth) can narrow 0.05μm compared even considering the current amplification factor 0.3μm and conventional. As a result, the base time constant τ
_B can be reduced by (0.3) ² /(0.35) ² ≒ 73%.

Furthermore, the PN junction capacitance C _J between the emitter and the base is designed so that the junction depth, carrier concentration, and other conditions do not change from the conventional one, so that the same capacitance value C _J = 8.6 fF as the conventional one
Becomes However, since the distance d between the emitter electrode 148a and the base layer 140 is different from the conventional 200 ° and is as thick as about 2000 ° in this embodiment, the insulation d between the emitter electrode 148a and the base layer 140 is large. The capacitance C _OX due to the membrane is C _OX
= 2.79fF, resulting in base-emitter capacitance C _TE
Is C _TE = 11.4 fF. This capacity is the conventional capacity C _TE = 36.5
It is about 31% lower than fF.

According this reason the manufacturing method of the present invention, as shown in FIG. 8, the cut-off frequency - emitter current (F _T -
I _E ) The characteristics were significantly improved in the low current range. Note that in Figure 8, the horizontal axis is the emitter current, and the vertical axis is the cut-off frequency, even more F _T -I _E characteristics of examples shows by I, shows indicated by II is F _T in the prior art -I is _E characteristics.

Further, the variation of the current amplification factor is very small, such as 90 to 110, because the variation of the base width of the BiCMOS obtained by the manufacturing method of this embodiment is small.
It was much improved compared to ~ 400. (7th
Figure).

(Effects of the Invention) As is apparent from the above description, according to the method for manufacturing a semiconductor device of the present invention, the insulating layer between the emitter electrode and the base layer is not a protective oxide film but has a film thickness. Since a thick base oxide film is formed and the depth of the base layer is reduced, a high-speed bipolar transistor can be formed.

… The base layer is formed after completion of the formation of the gate electrode with the sidewall, which is a later process than the conventional process, so that the number of heat treatments is reduced, and the base layer is etched by RIE during the sidewall formation. Since nothing happens, the depth of the base layer becomes uniform. As a result, (the depth of the base layer) - because the base width W _B as defined in (emitter depth) is uniform, the current amplification factor of the emitter grounding can form uniform bipolar transistor. Also, the base oxide film (second oxide film) is
Since it is formed by the COS method, it is possible to stably form the second oxide film having a large and uniform film thickness and a predetermined relative dielectric constant. Therefore, a shallow base layer can be formed with good reproducibility. Further, as the insulating film sandwiched between the edge portion of the emitter electrode and the base layer, an insulating film having a large and uniform thickness and exhibiting a predetermined relative dielectric constant can be formed.

For this reason, it is possible to manufacture a semiconductor device in which a bipolar transistor and a MOS transistor are provided in the same wafer, and which can operate at a high speed and have a high yield when being made into an LSI.

[Brief description of the drawings]

1 (A) to 1 (N) show a manufacturing method of a BiCMOS according to the present invention.
FIGS. 2A to 2J are views showing a manufacturing method of a conventional method for manufacturing a BiCMOS semiconductor device, and FIGS. 2A to 2J are views showing a manufacturing method of a conventional BiCMOS semiconductor device. FIG. 4 is a schematic plan view showing an arrangement relationship between an emitter layer and a base layer, FIG. 5 is a view showing a BiCMOS logic gate, and FIG. FIG. 7 is an explanatory view of an etching amount of a silicon substrate in a manufacturing method, FIG. 7 is a distribution diagram of a current amplification factor of a bipolar transistor of a BiCMOS semiconductor device manufactured by an embodiment and a conventional method, and FIG. BiCMOS manufactured by the method of
It is F _T -I _E characteristic curve diagram of a bipolar transistor of the semiconductor device. 100 Wafer, 102 P-type silicon substrate 104 P-type epitaxial layer 106 Area for bipolar transistor 108 Area for NMOS transistor 110 Area for PMOS transistor 112 N ⁺ buried layer 114 N region (collector region) 116 field oxide film 118 gate insulating film 120 insulating film 122 gate electrode of NMOS transistor 124 gate electrode of PMOS transistor 126 low concentration N ^- drain region 128 ...... sidewall forming material (PSG film) 130, 132 ...... sidewall 134 ...... protection oxide film 136 ...... oxygen-impermeable film (Si ₃ N ₄ film) 136a ...... slightly larger area than the emitter formation region of the wafer 138: Base oxide film, 140: Base layer 142: Source / drain formation planned area 144: Collector contact extraction area 146: Base contact extraction area 138a: A window (second window) for exposing a region where an emitter layer is to be formed 148: An emitter electrode forming material and a diffusion source for an emitter layer 148a: An emitter electrode also serving as a diffusion source for an emitter layer 150: Source / drain formation Planned region 152: interlayer insulating film, 154: emitter layer 142a, 150a: source / drain layer 144a: collector contact extraction layer 146a: base contact extraction layer.

Claims (2)

(57) [Claims] A first region of a semiconductor substrate of a first conductivity type is provided with a bipolar transistor in a first region, and an LDD is formed in a second region of the semiconductor substrate.
In a method of manufacturing a semiconductor device having a MOS transistor having a structure, after forming a gate oxide film, a gate electrode, and a sidewall of the gate electrode in the second region, forming a source and a drain of the MOS transistor Forming a first oxide film with a predetermined thickness on the second region and the first region; and forming a first oxide film on the first region on the first region. Increasing the thickness of a portion of the region including the region where the emitter is to be formed by the LOCOS method to form a second oxide film; and a predetermined portion of the semiconductor substrate including a portion below the second oxide film. Forming a base of the bipolar transistor in the region of the above; forming a window in the second oxide film to expose the region where the emitter is to be formed; and forming the window and the second oxide film around the window Emitter on top The method of manufacturing a semiconductor device which comprises a step of forming a pole. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said second oxide film is formed by providing an oxygen-impermeable film on said first oxide film and forming said second oxide film on said first region. A method for manufacturing a semiconductor device, comprising: removing an oxygen-impermeable film on a part including an area where an emitter is to be formed by etching, and forming the oxygen-impermeable film remaining after the removal as a mask.