JP2014067854A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, which can suppress manufacturing cost by reducing a manufacturing time.SOLUTION: A semiconductor device 1 comprises: a P type semiconductor substrate 2; an N type diffusion layer 4 which is formed in the semiconductor substrate 2 and in which an N type first impurity diffuses from a surface 20 of the semiconductor substrate 2 to a predetermined depth d; a P type diffusion layer 6 which is formed in the semiconductor substrate 2 and in which a P type second impurity having a concentration lower than that of the first impurity diffuses from the surface 20 to a depth dshallower than the N type diffusion layer 4 and which is surrounded by the N type diffusion layer 4; and an N+ type diffusion layer 12 which is formed in the P type diffusion layer 6 and in which an N type third impurity having a concentration higher than each of the first impurity and the second impurity diffuses from the surface 20 to a depth dshallower than the depth dof the P type diffusion layer 6.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  As a conventional technique, a semiconductor device including an N-type epitaxial layer, a P + type buried layer, and an N + type buried layer is known (see, for example, Patent Document 1).

  In this semiconductor device, a vertical bipolar transistor is formed by an N type epitaxial layer, a P + type buried layer, and an N + type buried layer.

JP 2011-77484 A

  However, the conventional semiconductor device has a problem that the manufacturing time of the semiconductor device becomes long because the N-type epitaxial layer is epitaxially grown after the P + type buried layer and the N + type buried layer are formed.

  Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce the manufacturing cost by shortening the manufacturing time.

  According to one embodiment of the present invention, a semiconductor substrate having a first conductivity type and a first impurity formed in the semiconductor substrate and having a second conductivity type different from the first conductivity type are formed from the surface of the semiconductor substrate. A first diffusion layer diffused to a predetermined depth and a second impurity having a first conductivity type formed in the semiconductor substrate and having a concentration lower than that of the first impurity are introduced from the surface into the first diffusion layer. Is diffused to a shallow depth, and is formed in a second diffusion layer surrounded by the first diffusion layer and a second diffusion layer, and has a concentration higher than that of the first impurity and the second impurity. And a third diffusion layer in which a third impurity having a conductivity type of 2 is diffused from the surface to a depth shallower than the depth of the second diffusion layer.

  According to the present invention, the manufacturing cost can be suppressed by reducing the manufacturing time.

FIG. 1 is a cross-sectional view of main parts of a semiconductor device according to an embodiment. 2A (a) to 2 (d) are cross-sectional views of relevant parts showing a method for manufacturing a semiconductor device according to the present embodiment. 2B (e) to 2 (h) are main-portion cross-sectional views illustrating the manufacturing method of the semiconductor device according to the present embodiment.

(Summary of embodiment)
A semiconductor device according to an embodiment includes a semiconductor substrate having a first conductivity type, and a first impurity formed in the semiconductor substrate and having a second conductivity type different from the first conductivity type. A first diffusion layer diffused from the surface to a predetermined depth and a second impurity having a first conductivity type formed in the semiconductor substrate and having a concentration lower than that of the first impurity are first diffused from the surface. The first diffusion layer is diffused to a depth shallower than the first layer, and the second diffusion layer is surrounded by the first diffusion layer, and the second diffusion layer has a concentration higher than that of the first impurity and the second impurity. And a third diffusion layer in which a third impurity having a high second conductivity type is diffused from the surface to a depth shallower than the depth of the second diffusion layer.

[Embodiment]
(Configuration of Semiconductor Device 1)
FIG. 1 is a cross-sectional view of main parts of a semiconductor device according to an embodiment. In each drawing according to the embodiment, the ratio of the drawn image to the image may be different from the actual ratio.

As shown in FIG. 1, the semiconductor device 1 includes a semiconductor substrate 2 having a first conductivity type (P type) and a second conductivity type (N) formed in the semiconductor substrate 2 and different from the first conductivity type. first impurity having a mold) is an N-type diffusion layer 4 as a first diffusion layer diffused from the surface 20 of the semiconductor substrate 2 to a predetermined depth d _1, it is formed in the semiconductor substrate 2, first The second impurity having the first conductivity type whose concentration is lower than that of the first impurity diffuses from the surface 20 to a depth d ₂ shallower than the N-type diffusion layer 4, and its periphery is surrounded by the N-type diffusion layer 4. A P-type diffusion layer 6 as a second diffusion layer, and a third impurity having a second conductivity type formed in the P-type diffusion layer 6 and having a higher concentration than the first impurity and the second impurity. , N + -type expansion as a third diffusion layer diffused from the surface 20 to a shallow depth d ₃ than the depth d ₂ of the P-type diffusion layer 6 And a scattering layer 12.

  The semiconductor device 1 is formed as a fifth diffusion layer formed in the P-type diffusion layer 6 in which the fifth impurity having the first conductivity type diffuses from the surface 20 to a depth shallower than the P-type diffusion layer 6. As a fourth diffusion layer formed in the P-type base layer 8 and the N-type diffusion layer 4 and having the fourth impurity having the second conductivity type diffused from the surface 20 to a depth shallower than the N-type diffusion layer 4. N-type collector layer 10.

(Configuration of semiconductor substrate 2)
As the semiconductor substrate 2, for example, a Si substrate containing Si as a main component is used. The semiconductor substrate 2 contains, for example, P-type impurities. In the present embodiment, this P-type impurity is B (boron). Therefore, the semiconductor substrate 2 is a P-type Si substrate containing B.

  The thickness of the semiconductor substrate 2 is, for example, 600 μm.

(Configuration of N-type diffusion layer 4)
The N-type diffusion layer 4 is formed, for example, by introducing an N-type first impurity into the semiconductor substrate 2 and diffusing it by heat treatment.

  The N-type first impurity is, for example, P, As, Sb, or the like. In this embodiment, P is used as the first impurity.

For example, as shown in FIG. 1, the N-type diffusion layer 4 is formed by diffusing the first impurity from the surface 20 to a depth d ₁ (approximately 12 μm).

  Therefore, the semiconductor substrate 2 and the N-type diffusion layer 4 are PN junction.

(Configuration of P-type diffusion layer 6)
The P-type diffusion layer 6 is formed, for example, by introducing a P-type second impurity into the semiconductor substrate 2 and diffusing it by heat treatment.

The P-type second impurity is, for example, B, BF ₂ , In, or the like. In this embodiment, B is used as the second impurity.

For example, as shown in FIG. 1, the P-type diffusion layer 6 is formed by diffusing the second impurity from the surface 20 to a depth d ₂ (approximately 9 μm).

  Here, the diffusion of the first impurity and the second impurity is not performed by alternately performing introduction and heat treatment, but the heat treatment is performed after the introduction of the first impurity and the second impurity. Is called.

  By this heat treatment, as shown in FIG. 1, the first impurity intersects under the P-type diffusion layer 6 while diffusing. That is, the first impurity diffuses also below the P-type diffusion layer 6. One of the reasons for such diffusion is that impurities can be accurately introduced into a predetermined region.

  Therefore, the N-type diffusion layer 4 and the P-type diffusion layer 6 are PN junction.

  When the semiconductor device 1 is viewed from above, the N-type diffusion layer 4 is formed so as to surround the P-type diffusion layer 6.

(Configuration of P-type base layer 8)
The P-type base layer 8 is formed by selectively introducing a P-type fifth impurity into the P-type diffusion layer 6 and diffusing it by heat treatment.

The P-type fifth impurity is, for example, B, BF ₂ , In, or the like. In this embodiment mode, B is used as the fifth impurity.

For example, the P-type base layer 8 is formed by diffusing impurities from the surface 20 to a depth d ₄ (approximately 1.0 μm).

  An electrode 14 that is electrically connected to the P-type base layer 8 is formed on the P-type base layer 8.

(Configuration of N-type collector layer 10)
The N-type collector layer 10 is formed by selectively introducing an N-type fourth impurity into the N-type diffusion layer 4 and diffusing it by heat treatment.

  The N-type fourth impurity is, for example, P, As, Sb, or the like. In this embodiment, P is used as the fourth impurity.

The N-type collector layer 10 is formed, for example, by diffusion of impurities from the surface 20 to a depth d ₄ (approximately 1.0 μm).

  An electrode 15 that is electrically connected to the N-type collector layer 10 is formed on the N-type collector layer 10.

(Configuration of N + type diffusion layer 12)
The N + type diffusion layer 12 is formed, for example, by selectively introducing an N type third impurity into the P type diffusion layer 6 and diffusing it by heat treatment.

  The N-type third impurity is, for example, P, As, Sb, or the like. In this embodiment, P is used as the third impurity.

For example, as shown in FIG. 1, the N + type diffusion layer 12 is formed by diffusing a third impurity from the surface to a depth d ₃ (approximately 1.2 μm).

  An electrode 16 that is electrically connected to the N + type diffusion layer 12 is formed on the N + type diffusion layer 12. The electrodes 14 to 16 are formed using, for example, Poly-Si, Cu, Al, or the like.

  When the semiconductor device 1 is viewed from above, the semiconductor device 1 seems to have the P-type base layer 8 formed around the N + type diffusion layer 12 and the N-type collector layer 10 formed around the P-type base layer 8. It has a different shape.

  In the semiconductor device 1, a vertical bipolar transistor is formed by the N type diffusion layer 4, the P type diffusion layer 6, and the N + type diffusion layer 12.

  Below, an example of the manufacturing method of the semiconductor device 1 is demonstrated.

(Manufacturing method of the semiconductor device 1)
2A (a) to 2 (d) and FIGS. 2B (e) to (h) are cross-sectional views of relevant parts showing a method for manufacturing a semiconductor device according to the present embodiment.

  A first impurity having an N type different from the P type is selectively introduced into the semiconductor substrate 2 having a P type.

  Specifically, as shown in FIG. 2A (a), a resist pattern 30 is formed on a region where the P-type diffusion layer 6 is to be formed by photolithography or the like. Subsequently, P is introduced as a first impurity into the semiconductor substrate 2 by ion implantation using the resist pattern 30 as a mask. After the first impurity is introduced, the resist pattern 30 is removed by ashing.

The conditions for introducing this first impurity are a dose amount of 5.0 × 10 ¹³ [cm ⁻² ] and an acceleration energy of 130 [keV]. That is, the first impurity is introduced at a high concentration in a deep position of the semiconductor substrate 2.

  A P-type second impurity having a lower concentration than the first impurity is selectively introduced into the P-type semiconductor substrate.

  Specifically, as shown in FIG. 2A (b), a resist pattern 32 exposing a region where the P-type diffusion layer 6 is to be formed is formed by photolithography or the like. Subsequently, B is introduced into the semiconductor substrate 2 as a second impurity by ion implantation using the resist pattern 32 as a mask. After the second impurity is introduced, the resist pattern 32 is removed by an ashing process.

The conditions for introducing the second impurity are a dose of 3.0 × 10 ¹³ [cm ⁻² ] and an acceleration energy of 60 [keV]. That is, the second impurity is introduced at a lower concentration at a position shallower than the first impurity. The acceleration energy of the first impurity is higher than the acceleration energy of the second impurity. This is because the first impurity is introduced to a position deeper in the semiconductor substrate 2 than the second impurity.

  Note that the order of introduction of the first impurity and introduction of the second impurity is not limited to the above example. That is, the step of introducing the first impurity and the second impurity is performed in the order of forming the resist pattern 32 and introducing the second impurity, and subsequently forming the resist pattern 30 and introducing the first impurity. good. That is, the order of introducing the first impurity to form the N-type diffusion layer 4 and the order of introducing the second impurity to form the P-type diffusion layer 6 can be interchanged.

Next, the semiconductor substrate 2 is subjected to a heat treatment to diffuse the first impurity from the surface 20 of the semiconductor substrate 2 to a predetermined depth d ₁ to form the N-type diffusion layer 4. The second impurity is diffused to a depth d ₂ shallower than the layer 4 to form a P-type diffusion layer 6 surrounded by the N-type diffusion layer 4.

  Specifically, as shown in FIG. 2A (c), the semiconductor substrate 2 is heat-treated to diffuse the first impurity and the second impurity. This heat treatment is performed at 1200 ° for 10 hours.

  By this heat treatment, the first impurity is diffused to form the N-type diffusion layer 4, and the second impurity is diffused to form the P-type diffusion layer 6.

  Since the first impurity is introduced at a higher concentration with higher acceleration energy than the second impurity, it diffuses deeper and wider than the second impurity. Therefore, the P-type diffusion layer 6 is formed so that the periphery thereof is surrounded by the N-type diffusion layer 4. In other words, the side surface and the bottom surface other than the surface of the P-type diffusion layer 6 exposed on the surface 20 are in contact with the N-type diffusion layer 4. That is, the P-type diffusion layer 6 has PN bonds formed on the side and bottom surfaces, that is, at the boundary with the N-type diffusion layer 4. Therefore, in the vicinity of the bottom surface of the P-type diffusion layer 6, the concentration of the first impurity contained in the N-type diffusion layer 4 is not less than a predetermined concentration, that is, a concentration at which the semiconductor substrate 2 and the P-type diffusion layer 6 do not leak. The first impurity is diffused.

  Next, a fifth impurity having P type is selectively introduced into the P type diffusion layer 6.

  Specifically, as shown in FIG. 2A (d), a resist pattern 34 exposing a region for forming the P-type base layer 8 is formed by photolithography or the like. Subsequently, B is introduced as a fifth impurity into the semiconductor substrate 2 by ion implantation using the resist pattern 34 as a mask. After the fifth impurity is introduced, the resist pattern 34 is removed by an ashing process.

The conditions for introducing this fifth impurity are a dose of 3.0 × 10 ¹³ [cm ⁻² ] and an acceleration energy of 60 [keV].

  Next, a fourth impurity having N type is selectively introduced into the N type diffusion layer 4.

  Specifically, as shown in FIG. 2B (e), a resist pattern 36 exposing a region for forming the N-type collector layer 10 is formed by photolithography or the like. Subsequently, P is introduced as a fourth impurity into the semiconductor substrate 2 by ion implantation using the resist pattern 36 as a mask.

The conditions for introducing the fourth impurity are a dose of 1.0 × 10 ¹³ [cm ⁻² ] and an acceleration energy of 60 [keV].

  Note that the order of introduction of the fifth impurity and the introduction of the fourth impurity is not limited to the above example. That is, the fifth impurity and the fourth impurity introduction step may be performed in the order of forming the resist pattern 36 and introducing the fourth impurity, and subsequently forming the resist pattern 34 and introducing the fifth impurity. good. That is, the order of the step of introducing the fifth impurity to form the P-type base layer 8 and the step of introducing the fourth impurity to form the N-type collector layer 10 can be interchanged.

Next, heat treatment is performed on the semiconductor substrate 2 to diffuse the fourth impurity from the surface 20 to the depth d ₄ shallower than the depth d ₁ of the N-type diffusion layer 4 to form the N-type collector layer 10. Then, the fifth impurity is diffused from the surface 20 to the depth d ₄ shallower than the depth d ₂ of the P-type diffusion layer 6 to form the P-type base layer 8.

  Specifically, as shown in FIG. 2B (f), the semiconductor substrate 2 is subjected to heat treatment to diffuse the fourth impurity and the fifth impurity. This heat treatment is performed at 1000 ° for 6 hours.

  By this heat treatment, the fourth impurity is diffused to form the N-type collector layer 10, and the fifth impurity is diffused to form the P-type base layer 8.

  Next, a third impurity having N type is selectively introduced into the P type diffusion layer 6.

  Specifically, as shown in FIG. 2B (g), a resist pattern 38 exposing a region where the N + type diffusion layer 12 is to be formed is formed by photolithography or the like. Subsequently, P is introduced as a third impurity into the semiconductor substrate 2 by ion implantation using the resist pattern 38 as a mask. After the third impurity is introduced, the resist pattern 38 is removed by an ashing process.

The conditions for introducing the third impurity are a dose of 5.0 × 10 ¹⁵ [cm ⁻² ] and an acceleration energy of 60 [keV].

Next, heat treatment is performed on the semiconductor substrate 2 to diffuse the third impurity from the surface 20 to the depth d ₃ shallower than the depth d ₂ of the P-type diffusion layer 6, thereby forming the N + -type diffusion layer 12.

  Specifically, as shown in FIG. 2B (h), the semiconductor substrate 2 is heat-treated to diffuse the third impurity. This heat treatment is performed at 900 ° for 0.5 hour.

  By this heat treatment, the third impurity is diffused to form the N + type diffusion layer 12. The third impurity has a higher concentration than other impurities, and the region where the N + -type diffusion layer 12 is formed is surrounded by the P-type base layer 8, so that the P-type base layer 8 and the N-type collector are included. It diffuses in the longitudinal direction from the layer 10.

  Next, an electrode 14 is formed on the P-type base layer 8, an electrode 15 is formed on the N-type collector layer 10, and an electrode 16 is formed on the N + -type diffusion layer 12 by photolithography or the like, so that the semiconductor device 1 shown in FIG. 1 is obtained. .

(Effect of embodiment)
The semiconductor device 1 according to the present embodiment can reduce the manufacturing cost by reducing the manufacturing time. Specifically, the semiconductor device 1 is mainly formed by diffusion of impurities mainly by ion implantation and heat treatment as compared with a vertical bipolar transistor formed by forming an embedded diffusion layer and then epitaxially growing an epitaxial layer. Since the type bipolar transistor is formed, the manufacturing time can be shortened. Further, since the manufacturing time of the semiconductor device 1 is shortened, the manufacturing cost can be suppressed.

  As mentioned above, although some embodiment of this invention was described, these embodiment is only an example and does not limit the invention which concerns on a claim. These novel embodiments can be implemented in various other forms, and various omissions, replacements, changes, and the like can be made without departing from the scope of the present invention. In addition, not all the combinations of features described in these embodiments are essential to the means for solving the problems of the invention. Furthermore, these embodiments are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Semiconductor substrate 4 ... N type diffused layer 6 ... P type diffused layer 8 ... P type base layer 10 ... N type collector layer 12 ... N + type diffused layers 14-16 ... Electrode 20 ... Surface 30 ... Resist pattern 32 ... Resist pattern 34 ... Resist pattern 36 ... Resist pattern 38 ... Resist pattern

Claims (4)

A semiconductor substrate having a first conductivity type;
A first diffusion layer formed in the semiconductor substrate and having a second conductivity type different from the first conductivity type diffused from the surface of the semiconductor substrate to a predetermined depth;
A second impurity having the first conductivity type formed in the semiconductor substrate and having a lower concentration than the first impurity diffuses from the surface to a depth shallower than the first diffusion layer; A second diffusion layer surrounded by the first diffusion layer;
A third impurity having the second conductivity type formed in the second diffusion layer and having a higher concentration than the first impurity and the second impurity is introduced from the surface into the second diffusion layer. A third diffusion layer diffused to a depth shallower than the depth;
A semiconductor device comprising: A fourth diffusion layer formed in the first diffusion layer and having a fourth impurity having the second conductivity type diffused from the surface to a depth shallower than the first diffusion layer;
A fifth diffusion layer formed in the second diffusion layer, the fifth impurity having the first conductivity type being diffused from the surface to a depth shallower than the second diffusion layer;
The semiconductor device according to claim 1, comprising: Selectively introducing a first impurity having a second conductivity type different from the first conductivity type into a semiconductor substrate having a first conductivity type;
Selectively introducing a second impurity having the first conductivity type into the semiconductor substrate having the first conductivity type, the concentration of which is lower than that of the first impurity;
The semiconductor substrate is subjected to heat treatment to diffuse the first impurity from the surface of the semiconductor substrate to a predetermined depth to form a first diffusion layer, and is shallower than the first diffusion layer from the surface. Diffusing the second impurity to a depth and forming a second diffusion layer surrounded by the first diffusion layer; and
Selectively introducing a third impurity having the second conductivity type into the second diffusion layer;
Performing a heat treatment on the semiconductor substrate to diffuse the third impurity from the surface to a depth shallower than the depth of the second diffusion layer to form a third diffusion layer;
A method of manufacturing a semiconductor device including: Selectively introducing a fourth impurity having the second conductivity type into the first diffusion layer;
Selectively introducing a fifth impurity having the first conductivity type into the second diffusion layer;
The semiconductor substrate is subjected to heat treatment to diffuse the fourth impurity from the surface to a depth shallower than the depth of the first diffusion layer to form a fourth diffusion layer, and from the surface to the second diffusion layer. Diffusing the fifth impurity to a depth shallower than the depth of the diffusion layer to form a fifth diffusion layer;
The manufacturing method of the semiconductor device of Claim 3 containing this.

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