JPH02288205A - Chip element - Google Patents
Chip elementInfo
- Publication number
- JPH02288205A JPH02288205A JP1109703A JP10970389A JPH02288205A JP H02288205 A JPH02288205 A JP H02288205A JP 1109703 A JP1109703 A JP 1109703A JP 10970389 A JP10970389 A JP 10970389A JP H02288205 A JPH02288205 A JP H02288205A
- Authority
- JP
- Japan
- Prior art keywords
- chip element
- electrodes
- chip
- crossed
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 claims abstract description 10
- 239000004020 conductor Substances 0.000 abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 11
- 239000000919 ceramic Substances 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 3
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、印刷配線板に用いられる電気的なチップ素
子に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrical chip element used in a printed wiring board.
第７（２）は従来例のチップ素子の正面図で、第８図は
第７図における■−■線の断面図である。図において、
１はチップ素子、２はこのチップ素子１のベースを構成
するセラミック基板、３はこのセラミック基板２の両端
に略コ字状に導体材料により形成された電極、４はセラ
ミック基板２の片面上に上記両端の電極３間に例えば印
刷法などにより形成された印刷抵抗体である。7(2) is a front view of a conventional chip element, and FIG. 8 is a sectional view taken along the line ■-■ in FIG. In the figure,
1 is a chip element, 2 is a ceramic substrate constituting the base of this chip element 1, 3 is an electrode formed of a conductive material in a substantially U-shape at both ends of this ceramic substrate 2, and 4 is on one side of the ceramic substrate 2. This is a printed resistor formed between the electrodes 3 at both ends by, for example, a printing method.
第９図は上記従来例のチップ素子ｌを複数搭載した印刷
組立板５の正面図であり、６はこの印刷組立板５のベー
スを構成する樹脂基材などからなる印刷配線板、７ａ、
７ｂ、７ｃ、７ｄは従来例のチップ素子１の両端電極と
各々電気的にはんだ付けなどにより接続するように印刷
配線板６上に配設された導体パターンで、そのうちの導
体パターン７ｃはチップ素子ｌの両端の電極３と接触し
ないようチップ素子ｌの中央部付近を交叉して配設され
ている。FIG. 9 is a front view of a printing assembly board 5 on which a plurality of chip elements l of the above-mentioned conventional example are mounted, and 6 is a printed wiring board made of a resin base material etc. that constitutes the base of this printing assembly board 5, 7a,
7b, 7c, and 7d are conductor patterns arranged on the printed wiring board 6 so as to be electrically connected to both end electrodes of the conventional chip element 1 by soldering, etc., of which the conductor pattern 7c is connected to the chip element 1. They are arranged so as to cross near the center of the chip element l so as not to come into contact with the electrodes 3 at both ends of the chip element l.
従来のチップ素子は以上のように構成されているので、
印刷配線板上に２個以上のチップ素子を搭載する場合、
チップ素子が重ならないように印刷部・線板上に搭載し
なければならず、印刷配線板の面積Ｐ多く要する◇まに
、導体パターンがチップ素子を交叉通過するために導体
パターンをチップ素子電極間に配設する手段が必要にな
るという問題点かあった。Conventional chip elements are configured as described above, so
When mounting two or more chip elements on a printed wiring board,
The chip elements must be mounted on the printing section/wire board so that they do not overlap, which requires a large area P of the printed wiring board There was a problem in that it required a means to be placed between the two.
この発明は上記のような問題点を解消するためになされ
たもので、搭載印刷配線板の面積が小さくて済み、かつ
導体パターンをチップ素子１！極間に交叉して通過させ
る必要のないチップ素子を提供せんとするものである。This invention was made to solve the above-mentioned problems, and the area of the mounted printed wiring board can be small, and the conductor pattern can only be connected to one chip element! It is an object of the present invention to provide a chip element that does not need to be passed between electrodes.
この発明に係るチップ素子は、複数個の電気素子を基材
の表・裏両面に交叉配設し、かつ基材の各縁辺部に上記
複数個の電気素子と対応する電極を配設したものである
。The chip element according to the present invention has a plurality of electric elements disposed crosswise on both the front and back sides of a base material, and electrodes corresponding to the plurality of electric elements are disposed on each edge of the base material. It is.
〔１作用〕
この発明においては、同一基板の表・裏に電気素子を交
叉して配設したので、チップ素子を印刷配線板に搭載す
るスペースが小さくて済み、かつ導体パターンをチップ
素子電極間に交叉して通す必要がない。[1 Effect] In this invention, since the electric elements are disposed crosswise on the front and back sides of the same substrate, the space for mounting the chip elements on the printed wiring board is small, and the conductor pattern is placed between the chip element electrodes. There is no need to cross it.
第１図はこの発明の一実施例を示すチップ素子の正面図
、第２囚及び第８図は第１図における■−■線及び■−
■線の断面図である。これらの図において、■はチップ
素子、２はチップ素子ｌのペースとなる正方形のセラミ
ック基板、３ａ及び３ｂはこのセラミンク基板２の各縁
辺の対向部位に略コ字状に導体材料により形成され、互
いに交叉するよう配設された２対の電極′、４ａ及び４
ｂはセラミック基板２の表・裏両面で、かつ上記電極把
及び３ｂの上に交叉するように、例えば印刷法などによ
り形成された印刷抵抗体である。FIG. 1 is a front view of a chip element showing an embodiment of the present invention, and FIG. 2 and FIG.
■It is a cross-sectional view of the line. In these figures, ■ is a chip element, 2 is a square ceramic substrate that serves as a base for the chip element l, 3a and 3b are formed of a conductive material in a substantially U-shape on opposing sides of each edge of this ceramic substrate 2, Two pairs of electrodes', 4a and 4 arranged to cross each other
b is a printed resistor formed on both the front and back surfaces of the ceramic substrate 2 and over the electrode grip 3b by, for example, a printing method.
第４図は上記のように構成したチップ素子を搭載した印
刷組立板の正面図で、５はチップ素子を搭載した印刷組
立板、６は樹脂基材かＣ，なり、印刷組立板５のベース
となる印刷配線板、ム、７ｂ、７ｃ、７ｄはチップ素子
１の電極為及び３ｂと各々電気的にはんだ付けなどによ
り接続するように印刷配線板６上に配設された導体パタ
ーンである。FIG. 4 is a front view of the printing assembly board on which the chip elements configured as described above are mounted, 5 is the printing assembly board on which the chip elements are mounted, 6 is the resin base material or C, and the base of the printing assembly board 5 is shown. The printed wiring board 7b, 7c, and 7d are conductor patterns arranged on the printed wiring board 6 so as to be electrically connected to the electrodes and 3b of the chip element 1, respectively, by soldering or the like.
なお上記実施例では、セラミック基板２の表・裏両面に
ｌｌＦ！ｉずつの印刷抵抗体を配設したものを示したが
、第５図及び第６文のようにセラミック基板２の表・Ｓ
画面に複機の印刷抵抗体４ａＪｂなどの電気素子を配設
することもできる。In the above embodiment, llF! is applied to both the front and back surfaces of the ceramic substrate 2. Although the example in which printed resistors of i each are arranged is shown, as shown in Fig. 5 and 6th sentence,
It is also possible to arrange electric elements such as a multi-function printed resistor 4aJb on the screen.
以上のようにこの発明によれば、印刷抵抗など複数転の
ｍ気素子を基材の表・裏両面に交叉して配設したので、
チップ素子を印刷配線板に搭載するのに必要な印刷配線
板面積は小さくて済み、また導体パターンをチップ素子
ＩＩ極間に交叉して通過させる必要がないなどのすぐれ
た効果を奏する。As described above, according to the present invention, multi-turn m-air elements such as printed resistors are disposed crosswise on both the front and back sides of the base material.
The area of the printed wiring board required to mount the chip element on the printed wiring board is small, and there are excellent effects such as there is no need to pass the conductor pattern across the electrodes of the chip element II.
第１図はこの発明の一実施例によるチップ素子を示す正
面図、第２図及び第８図は第１図におけるｎ−ｕｓ及び
■−■線の断面図、第４図はこの発明によるチップ素子
を搭載した印刷組立板の正面図、第５図はこの発明の他
の実施例を示すチップ素子の正面図、第６図は第５図に
おける■−■線の断面図、第７図は従来のチップ素子を
示す正面図、第８図は第７図における■−■線の断面図
、第９図は従来のチップ素子を搭載した印刷組立板の正
面図である。
図中、ｌはチップ素子、２はセラミック基板・３ム３ｂ
は電極・４枳４ｂは印刷抵抗体、５は印刷組立板・６は
印刷配線板ｓ ７ａ、７ｂ、７ｃ、７ｄは導体パターン
である。
なお図中同一符号は同一または相当部分を示す。FIG. 1 is a front view showing a chip element according to an embodiment of the present invention, FIGS. 2 and 8 are cross-sectional views taken along the n-us and ■-■ lines in FIG. 1, and FIG. 4 is a chip element according to the present invention. FIG. 5 is a front view of a printing assembly board on which elements are mounted, FIG. 5 is a front view of a chip element showing another embodiment of the present invention, FIG. 6 is a sectional view taken along the line ■-■ in FIG. 5, and FIG. FIG. 8 is a front view showing a conventional chip element, FIG. 8 is a sectional view taken along the line ■--■ in FIG. 7, and FIG. 9 is a front view of a printing assembly board on which the conventional chip element is mounted. In the figure, l is a chip element, 2 is a ceramic substrate, and 3b is
4 is an electrode, 4b is a printed resistor, 5 is a printed assembly board, 6 is a printed wiring board, and 7a, 7b, 7c, and 7d are conductor patterns. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
または複数個の電気素子と、この各電気素子に対応し基
材の各縁辺部に延在して配設してなる電極とを備えたチ
ップ素子。One or more electric elements arranged to intersect each other on both the front and back surfaces of the base material, and electrodes extending from each edge of the base material to correspond to each of the electric elements. A chip element with
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1109703A JPH02288205A (en) | 1989-04-27 | 1989-04-27 | Chip element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1109703A JPH02288205A (en) | 1989-04-27 | 1989-04-27 | Chip element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02288205A true JPH02288205A (en) | 1990-11-28 |
Family
ID=14517072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1109703A Pending JPH02288205A (en) | 1989-04-27 | 1989-04-27 | Chip element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02288205A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0745408A (en) * | 1993-07-31 | 1995-02-14 | Nec Corp | Composite resistor |
| US7154373B2 (en) | 2002-03-25 | 2006-12-26 | Minowa Koa Inc. | Surface mounting chip network component |
-
1989
- 1989-04-27 JP JP1109703A patent/JPH02288205A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0745408A (en) * | 1993-07-31 | 1995-02-14 | Nec Corp | Composite resistor |
| US7154373B2 (en) | 2002-03-25 | 2006-12-26 | Minowa Koa Inc. | Surface mounting chip network component |
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