JPH0228392A - Printed wiring board of ceramic - Google Patents

Printed wiring board of ceramic

Info

Publication number
JPH0228392A
JPH0228392A JP17884588A JP17884588A JPH0228392A JP H0228392 A JPH0228392 A JP H0228392A JP 17884588 A JP17884588 A JP 17884588A JP 17884588 A JP17884588 A JP 17884588A JP H0228392 A JPH0228392 A JP H0228392A
Authority
JP
Japan
Prior art keywords
layer
thick film
conductor
plating
thick
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17884588A
Other languages
Japanese (ja)
Inventor
Tatsumi Kubo
久保 立身
Kenichi Yokota
健市 横田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyobo Co Ltd
Original Assignee
Toyobo Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyobo Co Ltd filed Critical Toyobo Co Ltd
Priority to JP17884588A priority Critical patent/JPH0228392A/en
Publication of JPH0228392A publication Critical patent/JPH0228392A/en
Pending legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To obtain a printed wiring board of ceramic having high accuracy and high characteristics and being cheap by arranging a thick resistor layer formed by burning, a thick conductor terminal layer, an insulator layer, and a conductor circuit part formed by electric plating. CONSTITUTION:A thick resistor layer 2 formed by burning, a thick conductor terminal layer 1, and an insulator layer 3, and further a conductor circuit part 4 formed by electric plating are arranged on a ceramic substrate 5. By providing the insulating layer 3 on the thick resistor layer 1, the resistor layer 2 can be protected from erosion by strong alkaline and strong acid chemicals used for wet plating process. Hereby, without losing the essential characteristics of the thick resistor 2, a conductor pattern 4 can be formed finely and very accurately by plating conductor, especially, by copper plating, and high accuracy advancement and high characteristics advancement of the printed wiring board of ceramic can be realized.

Description

【発明の詳細な説明】 (産業上の利用分1f) 本発明は、高精度、高特性をffするセラミックプリン
ト配線板に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application 1f) The present invention relates to a ceramic printed wiring board with high precision and high characteristics.

(従来の技術) 湿式めっき法を用いたセラミックプリント配線板におい
て、厚膜焼成抵抗体層とめっき導体回路部と組み合わせ
ようとするこころみは、すでに行なわれている。例えば
、厚膜抵抗体層を焼成により形成後、導体回路部と接す
る前記厚膜抵抗体層の端r部に、パラジウムを含むガラ
スペーストを印刷後焼成して端r部を形成し、感光性ポ
リイミドを絶縁層かつめっきレジストとして被覆し、化
学めっきにより導体回路部を形成する方法が知られてい
る。さらに特開昭49−82966号公報には、厚膜導
体パッドを形成し、該導体パッド間に抵抗体を印刷、焼
成し、化学めっきにより導体回路を形成する方法も開示
されている。
(Prior Art) Efforts have already been made to combine a thick film fired resistor layer with a plated conductor circuit section in a ceramic printed wiring board using a wet plating method. For example, after forming a thick film resistor layer by firing, a glass paste containing palladium is printed on the end r part of the thick film resistor layer in contact with the conductor circuit part and then fired to form the end r part, and the photosensitive A method is known in which polyimide is coated as an insulating layer and a plating resist, and a conductor circuit portion is formed by chemical plating. Further, JP-A-49-82966 discloses a method of forming thick film conductor pads, printing and firing a resistor between the conductor pads, and forming a conductor circuit by chemical plating.

(発明が解決しようとする課題) 湿式めっき法を用いてセラミックプリント配線板を作製
する場合、厚膜抵抗体を含む基板にそのまま用いようと
すれば、湿式めっきプロセスに含まれる処理薬品により
抵抗体が侵され、抵抗体の心気特性は著しく劣化する。
(Problems to be Solved by the Invention) When producing a ceramic printed wiring board using a wet plating method, if you try to use it as is on a board containing thick film resistors, the resistor will be damaged by the treatment chemicals included in the wet plating process. is affected, and the hypochondriacal properties of the resistor are significantly deteriorated.

また、導体回路形成後に、抵抗体を作製しようとすれば
、たとえば抵抗体が厚膜焼成型抵抗体であれば800℃
以−りのl!lJ度を必゛昂とするため、先に形成した
湿式めっき導体が銅導体の場合、導体の諸性性を損なっ
てしまう結果となる。又、上記したように抵抗体端子部
に、パラジウムを含むガラス層を介在させた場合、抵抗
体として、特に電流ノイズの増大を伴ってしまうという
欠点があった。又、「特開昭49−82988Jでは、
抵抗体−1−を非活性化塗膜で覆うためレーザー・トリ
ミング性が著しく劣り、又、導体部を化学めっきにより
形成するため、所望の膜厚を得るには非常な時間を要し
、さらに、膜物性も電気めっき皮膜に比べ劣る等の欠点
を有している。
In addition, if a resistor is to be manufactured after the conductor circuit is formed, for example, if the resistor is a thick film fired resistor, the temperature is 800°C.
Here it is! Since the 1J degree is required to be increased, if the previously formed wet-plated conductor is a copper conductor, various properties of the conductor will be impaired. Further, as described above, when a glass layer containing palladium is interposed in the terminal portion of the resistor, there is a drawback in that the resistor, in particular, is accompanied by an increase in current noise. Also, in ``Unexamined Japanese Patent Publication No. 49-82988J,
Since the resistor-1- is covered with a non-activated coating film, the laser trimmability is extremely poor, and since the conductor part is formed by chemical plating, it takes a lot of time to obtain the desired film thickness. However, the physical properties of the film are inferior to those of electroplated films.

(課題を解決するための手段) 本発明者らは、従来技術の問題点を解決し、高精度、高
特性を有するセラミックプリント配線板の作製を鋭意検
討した結果、セラミック基板−にに厚膜導体端子層と厚
膜抵抗体層及び該厚膜抵抗体層を保護するための絶縁体
層を焼成により形成し、しかる後例えば、基板全面に化
学めっきを施し、厚膜導体端子の一部または全部と接続
するように電気めっきにより導体回路を形成する方法が
、前記高精度、高特性を有し、かつ導体回路にl′を金
属を使用しないためより安価なセラミックプリント配線
板であることを見出した。
(Means for Solving the Problems) As a result of intensive studies to solve the problems of the conventional technology and to produce a ceramic printed wiring board having high precision and high characteristics, the present inventors found that a thick film on a ceramic substrate A conductor terminal layer, a thick-film resistor layer, and an insulator layer for protecting the thick-film resistor layer are formed by firing, and then, for example, chemical plating is applied to the entire surface of the substrate, and a part of the thick-film conductor terminal or The method of forming a conductor circuit by electroplating to connect all the parts has been found to be a ceramic printed wiring board that has the above-mentioned high precision and high characteristics, and is cheaper because no metal is used for the conductor circuit. I found it.

すなわち本発明は、セラミック基板」二に、焼成により
形成した厚膜抵抗体層、厚膜導体端子、絶縁体層が配さ
れ、かつ電気めっきにより形成された導体回路部が配さ
れていることを特徴とする、セラミックプリント配線板
である。
That is, the present invention provides a ceramic substrate having a thick film resistor layer formed by firing, a thick film conductor terminal, an insulator layer, and a conductor circuit portion formed by electroplating. This is a ceramic printed wiring board with special features.

本発明におけるセラミック基板とは、アルミナ系基板、
窒化アルミニウム基板、炭化ケイ素基板、ガラス系基板
などのセラミックス系基板である。また、前記セラミッ
ク系基板はそのまま使用することができるが、好ましく
はめっき導体回路の密着力を1−げるために基板表面を
機械的または化学的に粗化したセラミック基板を使用す
る。
The ceramic substrate in the present invention refers to an alumina-based substrate,
These are ceramic-based substrates such as aluminum nitride substrates, silicon carbide substrates, and glass-based substrates. Although the ceramic substrate can be used as is, it is preferable to use a ceramic substrate whose surface has been mechanically or chemically roughened in order to improve the adhesion of the plated conductor circuit.

本発明における厚膜導体端子層とは、厚膜抵抗体層と、
導体回路パターンを形成しているめっき導体回路部とを
接続するための中間端子層で、所謂導体焼成ペーストに
より形成するもので、例えば、銀、パラジウム、白金、
金、銅、ニッケルなどの導電性微粉末、金属酸化物及び
有機ビヒクルまたは必要により微量のガラス質フリット
から成りセラミック基板−ヒに印刷後、適当な条件Fで
焼成し形成したものである。厚膜抵抗体層とめっき導体
回路部の間に厚膜導体端子層を介在させる方法としては
、第1図から第3図に示すような例が考えられるが、い
ずれを用いてもよい。又厚膜抵抗体層とめっき導体回路
の間に厚膜導体層が介在しておればよく、図の例に限定
されるものではない。厚膜抵抗体層とは、例えば、銀、
パラジウム、ルテニウム化合物、Ta、Sn+  In
の酸化物、L a B oなどの導電性微粉末、ガラス
質フリット、金属酸化物及び有機ビヒクルから成り、厚
膜導体端Y−層の一部又は全部に接続するような位置に
抵抗体層を印刷し、適当な条件ドで焼成したものである
。絶縁体層とは厚膜抵抗体層を保護する耐薬品性のもの
で、厚膜絶縁体であり厚膜絶縁体とは、ガラス質フリッ
ト、金属酸化物及び有機ビヒクルから成り、厚膜抵抗体
層上に厚膜絶縁体を印刷し、適当な条件下で焼成する。
The thick film conductor terminal layer in the present invention refers to a thick film resistor layer,
This is an intermediate terminal layer for connecting the plated conductor circuit part forming the conductor circuit pattern, and is formed using a so-called conductor firing paste, such as silver, palladium, platinum,
It is made of conductive fine powder of gold, copper, nickel, etc., a metal oxide, an organic vehicle, or, if necessary, a small amount of glassy frit, and is formed by printing on a ceramic substrate and then firing it under suitable conditions F. As a method for interposing the thick film conductor terminal layer between the thick film resistor layer and the plated conductor circuit section, examples shown in FIGS. 1 to 3 can be considered, but any method may be used. Further, it is sufficient that a thick film conductor layer is interposed between the thick film resistor layer and the plated conductor circuit, and the present invention is not limited to the example shown in the figure. The thick film resistor layer is made of, for example, silver,
Palladium, ruthenium compound, Ta, Sn+ In
oxide, conductive fine powder such as L a Bo, glassy frit, metal oxide and organic vehicle, and a resistor layer at a position connected to a part or all of the Y-layer at the end of the thick film conductor. was printed and fired under appropriate conditions. The insulator layer is a chemical-resistant layer that protects the thick film resistor layer and is a thick film insulator. A thick film insulator is printed on the layer and fired under appropriate conditions.

本発明における化学めっきとは、銅、銀、白金、白金属
、金、ルテニウム、ニッケル、及びコバルトの化′?的
めっきのことであり、電気めっきとは銅、ニッケル、金
、’[1、クロム、亜鉛などの電気めっきのことである
。導体回路部の形成法としては、基板全面に化学めっき
をした後、ネガ型のめっきレジストを形成し、その後電
気めっきすることにより導体回路を形成するセミアディ
テブ法叉は、化学めっき後電気めっきにより厚付けし、
その後ポジ型のエツチングレジストを形成し非回路部を
エツチング除去して、導体回路を形成するサブトラクト
法があり、どちらでも実施可能である。
Chemical plating in the present invention refers to plating of copper, silver, platinum, platinum metal, gold, ruthenium, nickel, and cobalt. Electroplating refers to the electroplating of copper, nickel, gold, chromium, zinc, etc. The method for forming the conductor circuit is the semi-additive method, in which conductor circuits are formed by chemically plating the entire surface of the board, then forming a negative plating resist, and then electroplating. attached,
There is a subtract method in which a positive etching resist is then formed and the non-circuit portion is etched away to form a conductor circuit, but either method can be used.

本発明がII)能となったのは、(1)厚膜抵抗体層i
−に絶縁体層を設けることにより、湿式めっきプロセス
憾用いられる、高温強アルカリ及び強酸性の薬液による
侵蝕から抵抗体層を保護したこと、■導体回路部を形成
しているめっき導体層と厚膜抵抗体層の接続に厚膜導体
端T−層を介在させ、理想的な端r構造としたこと等が
考えられる。(3)絶縁体層が焼成によって得られるも
ので、レーザートリミングに適している。
The present invention has achieved II) functionality due to (1) thick film resistor layer i.
- The resistor layer is protected from corrosion by high-temperature strong alkali and strong acid chemicals used in the wet plating process by providing an insulator layer on the plated conductor layer forming the conductor circuit section. It is conceivable that a thick film conductor end T-layer is interposed in the connection of the film resistor layer to create an ideal end r structure. (3) The insulator layer is obtained by firing and is suitable for laser trimming.

(実施例) 本発明を更に詳細に説明するために実施例を挙げるが、
本発明はこれらの実施例によって何ら限定されるもので
はない。
(Example) Examples will be given to explain the present invention in more detail.
The present invention is not limited in any way by these Examples.

性能評価のための測定は次の方法によった。TCR(温
度抵抗係数)特性:所定の回路パターンを形成し、基板
を恒温チャンバー内の端子に接続し、チャンバー内を2
5℃に調節し、その時の値を抵抗値とし、その後温度を
125℃に一部げ、その時の抵抗値を記録し、次式によ
りTCRを算出した。
Measurements for performance evaluation were performed using the following method. TCR (temperature resistance coefficient) characteristics: A predetermined circuit pattern is formed, the board is connected to a terminal in a constant temperature chamber, and the inside of the chamber is
The temperature was adjusted to 5° C., and the value at that time was taken as the resistance value, and then the temperature was raised to 125° C., the resistance value at that time was recorded, and the TCR was calculated using the following formula.

ノイズ(電流雑音係数)特性薯析定の回路/(ターンを
形成し、基板を室温(25℃)においてQuan−Te
ch Re5istor−N1se Te5t SET
 315Bを用いて測定した。
Noise (current noise coefficient) characteristics analysis circuit
ch Re5istor-N1se Te5t SET
Measured using 315B.

実施例1 アルミナを96%含f「する縦50.8mm−横50.
8■■、厚さ0.835■璽の白色セラミック基板を3
40℃に保持された溶融苛性ソーダに、10分間浸漬し
基板表面を適度に粗化した。次に厚膜導体焼成ペースト
(# 9601 rESL、Inc。
Example 1 Containing 96% alumina, length: 50.8 mm - width: 50 mm.
8■■, thickness 0.835■ white ceramic substrate 3
The substrate surface was appropriately roughened by immersing it in molten caustic soda maintained at 40° C. for 10 minutes. Next, thick film conductor firing paste (#9601 rESL, Inc.) was used.

」)をスクリーン印刷法により所望箇所に塗布し150
℃で10分間乾燥した後、900℃で10分間(トータ
ル35分間)空気焼成し、厚膜導体端子を形成した。厚
膜導体端子層間の間隔は1.0■■とした。次いで肉厚
膜導体端子層にそれぞれ一部屯なる様に、厚膜抵抗体焼
成ペースト(R931ONr昭栄化学工業■」)をスク
リーン印刷法により塗布し、150℃で10分間乾燥し
、850℃で10分間(トータル35分間)空気焼成し
た。史に、厚膜抵抗体を保護するため厚膜抵抗体層全面
を被う様に厚膜絶縁体焼成ペースト(# 9137 r
Dupont Japan LTD、 J )をスクリ
ーン印刷法により塗布し、150℃で10分間乾燥し、
その後、550℃で2分間(トータル20分間)空気中
焼成した。厚膜抵抗体層の焼成後の形状は中1.0−n
、長さ1.5mm、厚さ10戸である。又厚膜絶縁体層
の焼成後の形状は巾1.2.、、長さ1.7.、、厚さ
10IJJaである。
'') was applied to the desired location using the screen printing method.
After drying at .degree. C. for 10 minutes, air baking was performed at 900.degree. C. for 10 minutes (35 minutes in total) to form a thick film conductor terminal. The spacing between the thick film conductor terminal layers was set to 1.0■■. Next, a thick film resistor firing paste (R931ONr Shoei Kagaku Kogyo ■) was coated on each thick film conductor terminal layer by screen printing, and dried at 150°C for 10 minutes, and then dried at 850°C for 10 minutes. Air baking was performed for 35 minutes (35 minutes in total). Historically, in order to protect the thick film resistor, thick film insulator firing paste (#9137 r
Dupont Japan LTD, J) was applied by screen printing method, dried at 150°C for 10 minutes,
Thereafter, it was baked in air at 550° C. for 2 minutes (20 minutes in total). The shape of the thick film resistor layer after firing is medium 1.0-n.
, 1.5 mm long and 10 mm thick. The shape of the thick film insulator layer after firing has a width of 1.2. ,,length 1.7. , , thickness is 10IJJa.

上記、厚膜導体端子層、厚膜抵抗体層及び厚膜絶縁体層
形成後のアルミナ基板にセミアデイティブ法により厚膜
導体端子層の一部に改なる様に、めっき導体回路パター
ンを形成した。具体的には、まず、前記基板全面を化学
鋼めっきで被覆した。化学鋼めっきは、PTHプロセス
4 [5hlpleyFar Eastコにより、1.
0戸の化学鋼めっき皮膜を得た。さらに、感光性ドライ
フィルムを用いてネガ型のメツキレジストを厚膜導体端
子層の一部に重なるように回路パターン状に形成し、電
気鋼めっきを約10sを析出させた。電気鋼めっき後、
レジストを剥離、薄付けの化学鋼めっき部分を、O,I
M  [20210,IM  H2SO4のエツチング
液で除去した。この電気特性の測定結果を表1に示す。
After forming the above thick film conductor terminal layer, thick film resistor layer and thick film insulator layer, a plated conductor circuit pattern is formed on the alumina substrate by a semi-additive method so as to become a part of the thick film conductor terminal layer. did. Specifically, first, the entire surface of the substrate was coated with chemical steel plating. Chemical steel plating is performed by PTH process 4 [5hlplay Far East Co., Ltd., 1.
0 chemical steel plating films were obtained. Furthermore, a negative plating resist was formed in a circuit pattern using a photosensitive dry film so as to partially overlap the thick film conductor terminal layer, and electrical steel plating was deposited for about 10 seconds. After electrical steel plating,
Peel off the resist and apply thin chemical steel plating to O, I
M [20210, IM Removed with H2SO4 etching solution. Table 1 shows the measurement results of the electrical properties.

(実施例2) 実施例1に示したと同・の方法で、表面粗化した白色セ
ラミック基板に厚膜焼成型抵抗体ペースト(R931O
Nr昭栄化学工業■」)を用いて、スクリーン印刷法に
より所望ケ所に塗布し、120℃で10分間乾燥した後
850℃で10分間(トータル35分間)空気焼成した
。次いで厚膜抵抗体層の両端一部に市なる様厚膜導体端
子層に厚膜導体焼成ペースト(TR−4940r[TI
Iマ、ソセイ■」)を用いて、スクリーン印刷法により
形成し、150℃で10分間乾燥後、850℃で10分
間(トータル35分間)空気焼成した。
(Example 2) Thick film fired resistor paste (R931O
Nr Shoei Kagaku Kogyo ■'') was applied to desired areas by screen printing, dried at 120°C for 10 minutes, and then air-baked at 850°C for 10 minutes (total 35 minutes). Next, a thick film conductor firing paste (TR-4940r [TI
After drying at 150° C. for 10 minutes, air baking was performed at 850° C. for 10 minutes (total 35 minutes).

史に厚膜抵抗体層を保護するため厚膜抵抗体層]二に市
なる様に、絶縁体焼成ペース)(#9137rDupo
nt Japan LTD、 J )をスクリーン印刷
法により塗布し、150℃で10分間乾燥後550℃で
2分間(トータル20分間)空気焼成した。厚膜抵抗体
層の焼成後の形状は巾1.0ms、長さ1.5.、、厚
さ10戸である。叉厚膜絶縁体層の焼成後の形状は中1
.2ml+、長さ1.Q+*m、厚さ10−である。
Thick film resistor layer to protect the thick film resistor layer] Insulator firing pace) (#9137rDupo
nt Japan LTD, J) by a screen printing method, dried at 150°C for 10 minutes, and then air-baked at 550°C for 2 minutes (total 20 minutes). The shape of the thick film resistor layer after firing is 1.0 ms in width and 1.5 ms in length. ,, 10 doors thick. The shape of the thick film insulator layer after firing is medium 1.
.. 2ml+, length 1. Q+*m, thickness 10-.

1・、肥厚膜抵抗体層、厚膜導体端子・層及び厚膜絶縁
体層形成後のアルミナ基板に実施例1と同様にセミアデ
イティブ法により厚膜導体端子層の一部又は全部に重な
るように、めっき導体回路パターンを形成した。この電
気特性を表1に示す。
1. After forming the thick film resistor layer, the thick film conductor terminal layer, and the thick film insulator layer, the alumina substrate is coated with a part or all of the thick film conductor terminal layer using the semi-additive method as in Example 1. Thus, a plated conductor circuit pattern was formed. The electrical characteristics are shown in Table 1.

(実施例3) 実施例1に示したと同一の方法で厚膜導体端子層、厚膜
抵抗体層及び厚膜絶縁体層を形成したアルミナ基板にセ
ミアデイティブ法により厚膜導体端子層の一部に重なる
様に、めっき導体回路パターンを形成した。具体的には
、まず、前記基板全面を化学ニッケルーボロンめっきで
被覆した。
(Example 3) A thick film conductor terminal layer was formed by a semi-additive method on an alumina substrate on which a thick film conductor terminal layer, a thick film resistor layer, and a thick film insulator layer were formed by the same method as shown in Example 1. A plated conductor circuit pattern was formed so as to overlap the area. Specifically, first, the entire surface of the substrate was coated with chemical nickel-boron plating.

化学ニッケルボロンめっきは前記基板を触媒活性化した
後、トップケミアロイB−1rlfi野製薬f業■」を
用い、1.opllの化学ニッケルーボロンめっき皮膜
を得た。さらに、感光性ドライフィルムを用いてネガ型
のメツキレジストを厚膜導体端子層の一部に市なるよう
に回路パターン吠に形成し、電気鋼めっきを約10−を
析出させた。電気鋼めっき後、レジストを剥離、薄付け
の化学ニッケルーボロンめっき部分を、O,IM  n
2o□10、  LM  112S04のエツチング液
で除去した。この電気特性の測定結果を表1に示す。
For chemical nickel boron plating, after catalytically activating the substrate, 1. A chemical nickel-boron plating film of opll was obtained. Further, using a photosensitive dry film, a negative plating resist was formed on a part of the thick film conductor terminal layer to form a circuit pattern, and electrical steel plating was deposited to a thickness of about 10 mm. After electrical steel plating, remove the resist and apply thin chemical nickel-boron plating to O, IM n
It was removed with an etching solution of 2o□10 and LM 112S04. Table 1 shows the measurement results of the electrical characteristics.

(実施例4) 実施例1に示したと同一の方法で厚膜導体端子層、厚膜
抵抗体層及び厚膜絶縁体層を形成したアルミナ基板にサ
ブトラクティブ法により厚膜導体端子の一部に市なる様
に、めっき導体回路パターンを形成した。ニー1体的に
は、まず、前記基板全面を化学鋼めっきで皮膜厚が1μ
厚になるように被覆し、次いで電気めっきで全面を厚付
けし10.0/f11厚の電気鋼めっき皮膜を得た。し
かる後、感光性ドライフィルムを用いてポジ型のエツチ
ングレジストを回路パターン伏に形成し、0、1M  
H2O210,1M  l12SO4のエツチング液を
用いて非導体回路部分を除去した。この電気特性の測定
結果を表1に示す。
(Example 4) A part of the thick film conductor terminal was formed by a subtractive method on an alumina substrate on which a thick film conductor terminal layer, a thick film resistor layer, and a thick film insulator layer were formed by the same method as shown in Example 1. A plated conductor circuit pattern was formed to match the pattern. First, the entire surface of the substrate is coated with chemical steel plating to a coating thickness of 1 μm.
Then, the entire surface was electroplated to obtain a 10.0/f11 thick electrical steel plating film. After that, a positive etching resist was formed on the circuit pattern using a photosensitive dry film, and 0, 1M
The non-conductive circuit portions were removed using an etching solution of H2O210, 1M 112SO4. Table 1 shows the measurement results of the electrical characteristics.

(比較例1) 実施例1に11クシたと同・の方法で、表面粗化した白
色セラミ・ツク基板に厚膜焼成型抵抗体ペースト(R9
31ON r昭和化学1−又」)をスクリーン印刷法に
より所望パターン状に塗布し、850℃で、10分間(
トータル35分間)空気中焼成して抵抗体層を形成した
。この抵抗体層上に抵抗体保護用厚膜ガラスペースト(
#9137 rDupontJapan LTD、J 
)を抵抗体端子部を残し、抵抗体表面および壁面をカバ
ーするようにスクリーン印刷法により塗布し、550℃
で、2分間(トータル20分間)空気中焼成した。抵抗
体層の焼成後形吠は、幅1.0■■、長さ1.5龍、厚
さ10−。
(Comparative Example 1) Thick film fired resistor paste (R9
31ON r Showa Kagaku 1-mata'') was applied in a desired pattern by screen printing method, and then heated at 850°C for 10 minutes (
A resistor layer was formed by firing in air for a total of 35 minutes. Thick film glass paste for protecting the resistor (
#9137 rDupontJapan LTD, J
) was applied by screen printing to cover the resistor surface and wall, leaving the resistor terminals, and heated at 550°C.
It was baked in the air for 2 minutes (total 20 minutes). After firing, the resistor layer has a width of 1.0 mm, a length of 1.5 mm, and a thickness of 10 mm.

ガラス絶縁層の焼成機形状は、幅1.0−1長さ1.5
嘗11厚さlOuであり、抵抗体層と十字型を成し、抵
抗体端子部として抵抗体層の両端250戸+tlがガラ
ス絶縁層に覆われていないものである。
The shape of the baking machine for the glass insulating layer is width 1.0-1 length 1.5
It has a thickness of 11 lOu, forms a cross shape with the resistor layer, and 250+tl at both ends of the resistor layer as resistor terminal portions are not covered with a glass insulating layer.

上記、抵抗体層および保護絶縁層形状後の基板に、実施
例1で示したと同様なセミアデイティブ法により抵抗体
端子部に重なるようにめっき導体回路パターンを形成し
た。この電気特性を表1に示す。
A plated conductor circuit pattern was formed on the substrate after forming the resistor layer and the protective insulating layer by the same semi-additive method as shown in Example 1 so as to overlap the resistor terminal portion. The electrical characteristics are shown in Table 1.

(比較例2) 実施例1記載と同・の方法で表面粗化した白色アルミナ
基板−Lに厚膜抵抗体焼成ペースト(#6829 rD
upont Japan LTD、 J )を用いて、
スクリーン印刷法により所望パターン状に塗布し、85
0℃で、10分間空気焼成した。次いで厚膜抵抗体層の
両端1<に「になる様に厚膜パラジウム・ガラス焼成ペ
ーストを用いて、厚膜パラジウム・ガラス層をスクリー
ン印刷法により塗布し150℃で10分乾燥し、850
℃で10分間(トータル35分間)空気焼成した。史に
厚膜抵抗体層−Eに屯なる様に絶縁体焼成ペースト(#
9137rDupont Japan LTD、 J 
)をスクリーン印刷法により塗布し、150°Cで10
分間乾燥し後550℃で2分間(トータル20分間)空
気焼成した。
(Comparative Example 2) Thick film resistor firing paste (#6829 rD
upont Japan LTD, J),
Apply it in a desired pattern by screen printing method, and
Air baking was performed at 0° C. for 10 minutes. Next, a thick film palladium glass layer was applied to both ends of the thick film resistor layer by screen printing using a thick film palladium glass firing paste so that
Air baking was performed at ℃ for 10 minutes (total 35 minutes). Historically, insulator firing paste (#
9137rDupont Japan LTD, J
) was applied by screen printing method and heated at 150°C for 10
After drying for a minute, air baking was performed at 550° C. for 2 minutes (20 minutes in total).

厚膜抵抗体層の焼成後の形状は巾1.0龍、長さ1.5
■−1厚さ10戸である。又厚膜絶縁体層の焼成後の形
状はIrjl、2sn+、長さ1.0龍、厚さ10戸で
ある。1−肥厚膜抵抗体層、厚膜パラジウム・ガラス端
子及び厚膜絶縁体層形成後のアルミナ基板に実施例1と
同様にセミアデイティブ法により厚膜パラジウム・ガラ
ス層に重なる様に、めっき導体回路パターンを形成した
。この電気特性を表1に示す。
The shape of the thick film resistor layer after firing is 1.0 mm in width and 1.5 mm in length.
■-1 The thickness is 10 units. The shape of the thick film insulator layer after firing is Irjl, 2sn+, length 1.0mm, and thickness 10mm. 1- After forming the thick film resistor layer, the thick film palladium/glass terminal, and the thick film insulator layer, a plated conductor was applied to the alumina substrate using the semi-additive method as in Example 1 so as to overlap the thick film palladium/glass layer. A circuit pattern was formed. The electrical characteristics are shown in Table 1.

表1 (発明の効果) 本発明の実施により、厚膜抵抗体の本来の特性をそこな
うことなく、導体パターンをめっき導体、特に銅めっき
で微細かつ高精度に形成できることは、セラミックプリ
ント配線板の高精度化、高特性化に極めて有益である。
Table 1 (Effects of the Invention) By carrying out the present invention, conductor patterns can be formed finely and with high precision using plated conductors, especially copper plating, without damaging the original characteristics of thick film resistors. This is extremely useful for improving precision and characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図から第3図は、厚膜抵抗体層とめっき導体回路の
間に厚膜導体端子層を介在させる方法の例示である(断
面図)。 図中の各符号は以下に記すような内容を示す。 ■ 厚膜導体端子層 ■ 厚膜抵抗体層 ■ 絶縁体層 ■ めっき導体回路部 ■ セラミック基板
1 to 3 are illustrations (cross-sectional views) of a method for interposing a thick film conductor terminal layer between a thick film resistor layer and a plated conductor circuit. Each symbol in the figure indicates the following content. ■ Thick film conductor terminal layer ■ Thick film resistor layer ■ Insulator layer ■ Plated conductor circuit section ■ Ceramic substrate

Claims (1)

【特許請求の範囲】[Claims] (1)セラミック基板上に少なくとも厚膜抵抗体層とめ
っき法による導体回路部が配されてなるセラミックプリ
ント配線板において、焼成によって形成された厚膜抵抗
体層と厚膜導体端子と絶縁体層が配され、かつ電気めっ
きによって形成された導体回路部が配されていることを
特徴とするセラミックプリント配線板。
(1) In a ceramic printed wiring board in which at least a thick film resistor layer and a conductor circuit section formed by plating are arranged on a ceramic substrate, the thick film resistor layer, the thick film conductor terminal, and the insulator layer are formed by firing. What is claimed is: 1. A ceramic printed wiring board, characterized in that a conductor circuit section formed by electroplating is disposed on the ceramic printed wiring board.
JP17884588A 1988-07-18 1988-07-18 Printed wiring board of ceramic Pending JPH0228392A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17884588A JPH0228392A (en) 1988-07-18 1988-07-18 Printed wiring board of ceramic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17884588A JPH0228392A (en) 1988-07-18 1988-07-18 Printed wiring board of ceramic

Publications (1)

Publication Number Publication Date
JPH0228392A true JPH0228392A (en) 1990-01-30

Family

ID=16055676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17884588A Pending JPH0228392A (en) 1988-07-18 1988-07-18 Printed wiring board of ceramic

Country Status (1)

Country Link
JP (1) JPH0228392A (en)

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