JPH02284495A - Ceramic printed wiring board - Google Patents
Ceramic printed wiring boardInfo
- Publication number
- JPH02284495A JPH02284495A JP10674689A JP10674689A JPH02284495A JP H02284495 A JPH02284495 A JP H02284495A JP 10674689 A JP10674689 A JP 10674689A JP 10674689 A JP10674689 A JP 10674689A JP H02284495 A JPH02284495 A JP H02284495A
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- layer
- conductor
- resistor
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 26
- 239000004020 conductor Substances 0.000 claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000007747 plating Methods 0.000 claims abstract description 22
- 239000012212 insulator Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 description 24
- 239000000126 substance Substances 0.000 description 13
- 238000010304 firing Methods 0.000 description 10
- 239000011521 glass Substances 0.000 description 9
- 238000007650 screen-printing Methods 0.000 description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000000654 additive Substances 0.000 description 4
- 230000000996 additive effect Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 239000011342 resin composition Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 150000003304 ruthenium compounds Chemical class 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000011121 sodium hydroxide Nutrition 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、高精度、高特性を有すセラミックプリント配
線板に関するものであり、特に、抵抗体を焼成による厚
膜抵抗体で形成し、導体部をめっき法により形成したこ
とを特徴とする混成型の小型化に優れ、高信頼性のセラ
ミックプリント配線板に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a ceramic printed wiring board having high precision and high characteristics, and in particular, the present invention relates to a ceramic printed wiring board having high precision and high characteristics. The present invention relates to a hybrid type ceramic printed wiring board which is excellent in size and highly reliable, and whose conductor portions are formed by a plating method.
（従来の技術）
湿式めっき法を用いたセラミック・プリント配線板にお
いて、厚膜抵抗体層とめっき導体回路部と組み合わせよ
うとする試みは、すてに行なわれている。例えば、厚膜
抵抗体層を焼成により形成後、導体回路部と接する前記
厚膜抵抗体層の端子部に、パラジウムを含むガラスペー
ストを印刷後焼成して端子部を形成し、感光性ポリイミ
ドを絶縁層かつ、めっきレジストとして被覆し、化学め
っきにより導体回路部を形成する方法が知られている。(Prior Art) Attempts have already been made to combine a thick film resistor layer with a plated conductor circuit in a ceramic printed wiring board using a wet plating method. For example, after forming a thick film resistor layer by firing, a glass paste containing palladium is printed on the terminal part of the thick film resistor layer in contact with the conductor circuit part and then fired to form the terminal part, and then photosensitive polyimide is applied. A method is known in which a conductive circuit portion is formed by coating with an insulating layer and a plating resist and chemical plating.
さらに特開昭４９−８２９６８号公報には、厚膜導体パ
ッドを形成し、該導体パ・ノド間に抵抗体を印刷、焼成
し、化学めっきにより導体回路部を形成する方法も開示
されている。Furthermore, JP-A-49-82968 discloses a method of forming a thick film conductor pad, printing and firing a resistor between the conductor pads, and forming a conductor circuit section by chemical plating. .
（発明が解決しようとする課題）
湿式めっき法を用いてセラミック・プリント配線板を作
製する場合、厚紙抗体を含む基板にそのまま用いようと
すれば、湿式めっきプロセスに含まれる処理薬品により
抵抗体が侵され、抵抗体の電気特性は著しく劣化する。(Problems to be Solved by the Invention) When producing a ceramic printed wiring board using a wet plating method, if you try to use it as is on a board containing cardboard antibodies, the processing chemicals included in the wet plating process will damage the resistor. The electrical properties of the resistor deteriorate significantly.
また、導体回路形成後に、抵抗体を作製しようとすれば
、たとえば抵抗体が厚膜焼成抵抗体であれば８００°Ｃ
以上の温度を必要とするため、先に形成した湿式めっき
導体が銅導体の場合、導体の諸特性を損なってしまう結
果となり又、導体パッドを形成し抵抗体層を形成する方
法においては、抵抗体の膜厚が、印刷方向、電極形状に
よりばらつき抵抗値の再現性が悪くなる恐れがあった。In addition, if you try to make a resistor after forming the conductor circuit, for example, if the resistor is a thick film fired resistor, the temperature is 800°C.
If the previously formed wet-plated conductor is a copper conductor, this will result in loss of various properties of the conductor. There was a risk that the film thickness of the body would vary depending on the printing direction and electrode shape, resulting in poor reproducibility of the resistance value.
又、上記したように抵抗体端子部（厚膜導体層）に、パ
ラジュムを含むガラス層を介在させた場合、抵抗体とし
て、特に電流ノイズの増大を伴ってしまうという欠点が
あった。Further, as described above, when a glass layer containing palladium is interposed in the resistor terminal portion (thick film conductor layer), there is a drawback that the resistor, in particular, is accompanied by an increase in current noise.
（課題を解決するための手段）
本発明者らは、従来技術の問題点を解決し、高精度、高
特性を有するセラミック・プリント配線板の作製を鋭意
検討した結果、セラミック基板上に厚膜抵抗体層と厚膜
導体端子層及び該厚膜抵抗体層を保護するための絶縁体
層を形成し、しかる後化学めっきを施し、厚膜導体端子
層の−・部または全部と接続するように導体回路を形成
する方法が、前記高精度、高特性を有し、かつ導体回路
に貴金属を使用しないためより安価なセラミック・プリ
ント配線板であることを見出した。(Means for Solving the Problems) The present inventors solved the problems of the conventional technology and, as a result of intensive study on the production of a ceramic printed wiring board having high precision and high characteristics, the present inventors found that a thick film on a ceramic substrate A resistor layer, a thick-film conductor terminal layer, and an insulator layer for protecting the thick-film resistor layer are formed, and then chemical plating is applied to connect to - part or all of the thick-film conductor terminal layer. It has been found that a method of forming a conductive circuit can produce a ceramic printed wiring board that has the above-mentioned high precision and high characteristics, and is less expensive because no precious metal is used in the conductive circuit.
すなわぢ本発明は、少なくとも、厚膜抵抗体層とめっき
による導体回路部がセラミック基板上に配されてなる、
セラミック・プリント配線板において、厚膜抵抗体層が
先ず形成され、該厚膜抵１ｊ’Ｌ体層の少なくとも一部
上に重なるように、厚膜導体層が形成され、かつ該厚膜
抵抗体層の少なくとも一部を覆うように絶縁体層が形成
され、かつ厚膜導体層の少なくとも一部に重なるように
、めっきによる導体回路部が形成されていることを特徴
とするセラミックプリント配線板である。In other words, the present invention provides at least a thick film resistor layer and a conductor circuit section formed by plating arranged on a ceramic substrate.
In the ceramic printed wiring board, a thick film resistor layer is first formed, a thick film conductor layer is formed so as to overlap at least a portion of the thick film resistor layer, and the thick film conductor layer is formed so as to overlap at least a portion of the thick film resistor layer. A ceramic printed wiring board, characterized in that an insulator layer is formed to cover at least a part of the layer, and a conductor circuit part by plating is formed to overlap at least a part of the thick film conductor layer. be.
本発明におけるセラミック基板とは、アルミナ系基板、
窒化アルミニウム基板、炭化ケイ素基板、ガラス系基板
などのセラミックス系基板である。The ceramic substrate in the present invention refers to an alumina-based substrate,
These are ceramic-based substrates such as aluminum nitride substrates, silicon carbide substrates, and glass-based substrates.
また、前記セラミック系基板はそのまま使用することが
できるが、好ましくはめっき導体の密着力を上げるため
に基板表面を機械的または化学的に粗化したセラミック
基板を使用する。特に、溶融アルカリによって粗面化さ
れたアルミナ系基板が好適である。Although the ceramic substrate can be used as is, it is preferable to use a ceramic substrate whose surface has been mechanically or chemically roughened in order to increase the adhesion of the plated conductor. Particularly suitable is an alumina-based substrate whose surface has been roughened by molten alkali.
本発明における厚膜導体端子層（厚膜導体層）とは、厚
膜抵抗体層と、導体回路パターンを形成しているめっき
導体層とを接続するための耐薬品性の中間端子層で、例
えば、銀、パラジウム、白金、金、銅、ニッケルなどの
導電性微粉末、金属酸化物及び有機ビヒクルまたは前記
成分と耐薬品性のガラス質フリットから成りセラミック
基板」二に印刷後、適当な条件下でｊ３’を成し形成し
たものである。厚膜抵抗体とめっき導体の間に厚膜導体
端子層を介在させる方法としては、第１．２図に示すよ
うな例が考えられるか、いずれを用いてもよい。また、
これらの例に限定されるものでもない。The thick film conductor terminal layer (thick film conductor layer) in the present invention is a chemical-resistant intermediate terminal layer for connecting the thick film resistor layer and the plated conductor layer forming the conductor circuit pattern. For example, conductive fine powders such as silver, palladium, platinum, gold, copper, nickel, metal oxides and organic vehicles or ceramic substrates made of chemically resistant glass frit with the above components are printed on a ceramic substrate and then subjected to suitable conditions. It is formed by forming j3' below. As a method for interposing a thick film conductor terminal layer between the thick film resistor and the plated conductor, an example as shown in FIG. 1.2 may be considered, or any method may be used. Also,
It is not limited to these examples either.
また、厚膜導体層として、より好ましいのは、前記印刷
のためのペース）・にガラス質フリットを含まないもの
である。Furthermore, the thick film conductor layer is more preferably one in which the printing paste does not contain vitreous frit.
厚膜抵抗体層とは、例えば、銀、バラジュウム、ルテニ
ウム化合物Ｎ Ｔ ａ ＋ Ｓ ｎ ＋ Ｉ ｎの酸
化物、Ｉ、 ａ Ｂ ｅなどの導電性微粉末、ガラス質
フリット、金属酸化物及び有機ビヒクルから成り、厚膜
導体端子層の一部又は全部に接続するような位置に抵抗
体層を印刷し、適当な条件下で焼成し形成したものであ
る。絶縁体層とは厚膜抵抗体を保護する耐薬品性のもの
で、厚膜絶縁体又は樹脂組成物のいずれでもよい。厚膜
絶縁体は、ガラス質フリッ）・、金属酸化物及び有機ビ
ヒクルから成り、厚膜抵抗体層上に厚膜絶縁体を印刷し
、適当な条件下で焼成する。又樹脂組成物は、耐薬品性
の物を用い、厚膜抵抗体層上に前記樹脂組成物を印刷し
、適当な条件下で硬化させる。導体回路部の形成法とし
ては、基板全面に化学めっきにより厚付けし、その後ポ
ジ型のエツチングレジストを形成し非回路部をエツチン
グ除去して、回路を形成するザブトラクト
た後、化学めっきにより回路形成するフルアデイティブ
法があり、どぢらても実施可能である。The thick film resistor layer includes, for example, conductive fine powder such as silver, baladium, oxide of ruthenium compound NTa + Sn + In, I, aBe, glassy frit, metal oxide, and organic It consists of a vehicle, and is formed by printing a resistor layer at a position where it connects to part or all of the thick film conductor terminal layer, and baking it under appropriate conditions. The insulator layer is a chemical-resistant layer that protects the thick film resistor, and may be either a thick film insulator or a resin composition. The thick film insulator consists of a glassy frit, a metal oxide, and an organic vehicle, and the thick film insulator is printed on the thick film resistor layer and fired under appropriate conditions. Further, a chemical-resistant resin composition is used, and the resin composition is printed on the thick film resistor layer and cured under appropriate conditions. The method for forming the conductive circuit section is to apply thick chemical plating to the entire surface of the board, then form a positive etching resist and remove the non-circuit section by etching to form the circuit.After that, the circuit is formed by chemical plating. There is a fully additive method that can be used either way.
＝６
本発明か可能となったのは、（１）厚膜抵抗体層」二に
絶縁体層を設けることにより、湿式めっきプロセスに用
いられる、高温強アルカリ及び強酸性の薬液に・よる侵
蝕から抵抗体層を保護したこと、（２）導体回路部を形
成しているめっき導体層と厚膜抵抗体層の接続に厚膜導
体端子層を介在させ、理想的な端子構造としたこと等が
考えられる。=6 The present invention has made possible the following: (1) By providing an insulator layer on the thick film resistor layer, corrosion caused by high-temperature strong alkaline and strong acidic chemicals used in the wet plating process can be avoided. (2) A thick film conductor terminal layer is interposed between the plated conductor layer forming the conductor circuit section and the thick film resistor layer, resulting in an ideal terminal structure. is possible.
（実施例）
本発明を更に詳細に説明するために実施例を挙げるが、
本発明はこれらの実施例によって何ら限定されるもので
はない。(Example) Examples will be given to explain the present invention in more detail.
The present invention is not limited in any way by these Examples.
性能評価のための測定は次の方法によった。Measurements for performance evaluation were performed using the following method.
ＴＣＲ（抵抗温度係数）特性：所定の回路パターンを形
成し、基板を恒温チャンバー内の端子に接続し、チャン
バー内を２５°Ｃに調節し、その時の値を抵抗値とし、
その後温度を１２５°Ｃに」二げ、その時の抵抗値を記
録し、次式によりＴＣＲを算出した。TCR (temperature coefficient of resistance) characteristics: Form a predetermined circuit pattern, connect the board to the terminals in a constant temperature chamber, adjust the temperature inside the chamber to 25°C, and take the value at that time as the resistance value.
Thereafter, the temperature was raised to 125°C, the resistance value at that time was recorded, and the TCR was calculated using the following formula.
ノイズ（電流雑音指数）特性：所定の回路パターンを形
成し、基板を室温（２５°Ｃ）においてＱｕａｎＴｅｃ
ｈ Ｒｅ５ｉｓｔｏｒ−Ｎｌｓｅ Ｔｅ５ｔ ＳＥＴ
３１５Ｂを用いて測定した。Noise (current noise figure) characteristics: A predetermined circuit pattern is formed, and the board is placed at room temperature (25°C) using QuanTec
h Re5istor-Nlse Te5t SET
Measured using 315B.
〔実施例１〕
アルミナ９６％含存する縦５０．８−ｍ、厚さ０．８３
５ｍｍの白紙セラミック基板を３４０°Ｃに保持された
溶融苛性ソーダに、１０分間浸漬し基板表面を適度に粗
化した。次に厚膜抵抗体焼成ペース１−（Ｒ９３１ＯＮ
ｒ昭栄化学工業１力」）をスクリーン印刷法により塗布
し、１５０°Ｃで１０分間乾燥し、８５０°Ｃで１０分
間（トータル３５分間）空気焼成した。次に厚膜導体焼
成ペースト（Ｈ４５６６ｒ昭栄化学工業ＩＪＪ）を抵抗
体と一部重なる様に、スクリーン印刷法により塗布し、
１５０°Ｃて１０分間乾燥し、８５０ ’Ｃで１０分間
（トータル３５分間）空気焼成した。抵抗体端子用厚膜
導体層間の間隔は１．０ｍｍとした。更に、厚膜抵抗体
を保護するため厚膜抵抗体層全面を被う様に厚膜絶縁体
焼成ペース）（ＡＰ５２３１「旭硝子」）をスクリーン
印刷法により塗布し、１５０ ’Ｃで１０分間乾燥し、
その後、６００′Ｃで１０分間（１−一タル３０分間）
空気中焼成した。[Example 1] Containing 96% alumina, length 50.8 m, thickness 0.83
A 5 mm blank ceramic substrate was immersed in molten caustic soda maintained at 340° C. for 10 minutes to appropriately roughen the substrate surface. Next, thick film resistor firing pace 1-(R931ON
Shoei Kagaku Kogyo Iriki") was applied by screen printing, dried at 150°C for 10 minutes, and air-baked at 850°C for 10 minutes (total 35 minutes). Next, thick film conductor firing paste (H4566r Shoei Kagaku Kogyo IJJ) was applied by screen printing so that it partially overlapped with the resistor.
It was dried at 150°C for 10 minutes and air-baked at 850'C for 10 minutes (total 35 minutes). The interval between the thick film conductor layers for resistor terminals was 1.0 mm. Furthermore, in order to protect the thick film resistor, thick film insulator baking paste (AP5231 "Asahi Glass") was applied by screen printing to cover the entire surface of the thick film resistor layer, and dried at 150'C for 10 minutes. ,
Then, at 600'C for 10 minutes (1-1 tar 30 minutes)
Fired in air.
厚膜抵抗体の焼成後の形状はｒｌｌｌ、０ｍｍ１長さ１
゜５ ｍｍ１厚さ１０μｍである。又厚膜絶縁体層の焼
成後の形状は’ｌＪｉ 、２ ｍｍ、長さ１．０ｍｍ１
厚さ１０μｍである。The shape of the thick film resistor after firing is rllll, 0 mm 1 length 1
゜5 mm 1 thickness 10 μm. The shape of the thick film insulator layer after firing is 'lJi, 2 mm, length 1.0 mm1.
The thickness is 10 μm.
」１記、厚膜抵抗体層、抵抗体端子用厚膜導体層及び厚
膜絶縁体層形成後のアルミナ基板にフルアデイティブ法
により厚膜導体端子層の一部に重なる様に、めっき導体
回路パターンを形成した。具体的には、まず、前記基板
全面を触媒活性化し、その後感光性ドライフィルムを用
いてネガ型のめっきレジス１へを厚膜導体端子層の一部
に重なるように回路パターン状に形成し、化学銅めっき
を約１０μｍを析出させ、最後にレジストを剥離した。1. After forming the thick film resistor layer, the thick film conductor layer for resistor terminals, and the thick film insulator layer, a plated conductor is coated on the alumina substrate using a full additive method so as to partially overlap the thick film conductor terminal layer. A circuit pattern was formed. Specifically, first, the entire surface of the substrate is catalytically activated, and then a circuit pattern is formed on the negative plating resist 1 using a photosensitive dry film so as to overlap a part of the thick film conductor terminal layer, Chemical copper plating was deposited to a thickness of about 10 μm, and finally the resist was peeled off.
化学銅めっきは、ＫＣ−１，０［日本鉱業］を用いた。For chemical copper plating, KC-1,0 [Nippon Mining Co., Ltd.] was used.
この電気特性の測定結果を表１に示す。Table 1 shows the measurement results of the electrical characteristics.
〔実施例２〕
実施例１に示したと同一の方法で厚膜抵抗体層、抵抗体
端子厚膜導体層及び厚膜絶縁体層を形成したアルミナ基
板にサブトラクティブ法により厚膜導体端子層の一部に
重なる様に、めっき導体回路パターンを形成した。具体
的には、まず、前記基板全面を触媒活性化し、その後化
学銅めっきて基板全面を皮膜厚が１０μ厚になるように
被覆した。[Example 2] A thick film conductor terminal layer was formed by a subtractive method on an alumina substrate on which a thick film resistor layer, a resistor terminal thick film conductor layer, and a thick film insulator layer were formed using the same method as shown in Example 1. A plated conductor circuit pattern was formed so as to partially overlap. Specifically, first, the entire surface of the substrate was catalytically activated, and then chemical copper plating was applied to coat the entire surface of the substrate to a film thickness of 10 μm.
次に、感光性ドライフィルムを用いてポジ型のエツチン
グレジストを回路パターン状に形成し、０．１Ｍ Ｈ
２０゜１０．１Ｍ Ｉ’１２Ｓ０４のエツチング液を
用いて非導体回路部分を除去した。この電気特性の測定
結果を表１に示す。Next, a positive etching resist was formed into a circuit pattern using a photosensitive dry film, and a 0.1M H
The non-conductive circuit portion was removed using an etching solution of 20°10.1M I'12S04. Table 1 shows the measurement results of the electrical properties.
〔比較例１〕
実施例１に示したと同一の方法で、表面粗化した白色セ
ラミック基板に厚膜力“Ｌ成型抵抗体ペース）（Ｒ９３
１ＯＮｒ昭和化学工業」）をスクリーン印刷法により所
望パターン状に塗布し、８５０°Ｃで、１０分間（トー
タル３５分間）空気中焼成して抵抗体層を形成した。こ
の抵抗体層」−に抵抗体保護用厚膜ガラスペース） （
ＡＰ５２３１ ｒ旭硝子」）を抵抗体端子部を残し、抵
抗体表面お上一
＝１０＝
び壁面をカバーするようにスクリーン印刷法により塗布
し、ｅ ｏ ｏ ’ｃで、１０分間（トータル３０分間
）空気中焼成した。抵抗体層の焼成後形状は、幅１．０
開長さ１．５０ｍ１厚さ１０μｍ０ガラス絶縁層の焼成
後形状は、幅１．０寸、長さ１．５■、厚さ１０μｍで
あり、抵抗体層と十字型を成し、抵抗体端子部として抵
抗体層の両端２５０μｍ巾がガラス絶縁層に覆われてい
ないものである。[Comparative Example 1] By the same method as shown in Example 1, thick film force "L molded resistor paste" (R93
1ONr (Showa Kagaku Kogyo)) was applied in a desired pattern by a screen printing method and baked in air at 850°C for 10 minutes (total 35 minutes) to form a resistor layer. This resistor layer is covered with a thick film glass space for protecting the resistor (
AP5231RAsahi Glass") was applied by screen printing method to cover the resistor surface and wall surface, leaving the resistor terminal area, and was applied for 10 minutes (total 30 minutes) Fired in air. The shape of the resistor layer after firing is a width of 1.0
Open length: 1.50 m, thickness: 10 μm. After firing, the glass insulating layer has a width of 1.0 cm, a length of 1.5 cm, and a thickness of 10 μm. In this example, a width of 250 μm at both ends of the resistor layer is not covered with a glass insulating layer.
上記、抵抗体層および保護絶縁層形状後の基板に、実施
例１で示したと同様なフルアデイティブ法により抵抗体
端子部に重なるひようにめっき導体回路パターンを形成
した。この型持性を表１に示す。After forming the resistor layer and the protective insulating layer, a plated conductor circuit pattern was formed on the substrate by the same full additive method as shown in Example 1 to overlap the resistor terminals. This mold retention is shown in Table 1.
〔比較例２〕
実施例１記載と同一の方法で表面粗化した白色アルミナ
基板上に抵抗体端子用の厚膜導体ペース） （Ｈ４５６
６ｒ昭栄化学工業」）をスクリーン印刷法により所望パ
ターン形状に塗布し、８５０°Ｃで１０分間（トータル
３５分間）空気中焼成して形成した。つぎに導体間に厚
膜焼成型抵抗体ペース１−（Ｒ９３１ＯＮｒ昭栄化学工
業」）をスクリーン印刷法により塗布し、８５０°Ｃて
、１０分間（トータル３５分間）空気中焼成して１０分
間（＋−−タル３５分間）空気焼成して抵抗体を形成し
た。この抵抗体層上に抵抗体保護用厚膜ガラスペースト
（ＡＰ５２３１ｒ旭硝子」）を導体端子部を残し、抵抗
体表面及び壁面をカバーする様にスクリーン印刷法によ
り塗布し、６００°Ｃで１０分間（トータル３０分間）
空気焼成した。厚膜抵抗体層の焼成後の形状は、幅１．
０ｍ１１．長さ１．５ｍｍ、厚さ１０μｍである。又厚
膜絶縁体層の焼成後の形状は１１．２ｍｎ＋、長さ１．
０ｗ１厚さ１０μｍである。上記厚膜導体層、厚膜抵抗
体層及び厚膜絶縁体層形成後のアルミナ基板に実施例１
と同様にフルアデイティブ法により厚膜導体層に重なる
様に、めっき導体回路パターンを形成した。この電気特
性を表１に示す。[Comparative Example 2] Thick film conductor paste for resistor terminals was placed on a white alumina substrate whose surface was roughened in the same manner as described in Example 1) (H456
6r (Shoei Kagaku Kogyo)) was applied in a desired pattern shape by a screen printing method, and baked in air at 850°C for 10 minutes (total 35 minutes). Next, thick film fired resistor paste 1- (R931ONr Shoei Kagaku Kogyo) was applied between the conductors by screen printing method, and baked in air at 850°C for 10 minutes (35 minutes in total) for 10 minutes (+ --35 minutes) was air fired to form a resistor. On this resistor layer, a thick film glass paste for resistor protection (AP5231r Asahi Glass) was applied by screen printing to cover the resistor surface and wall, leaving the conductor terminals, and heated at 600°C for 10 minutes ( 30 minutes in total)
Air fired. The shape of the thick film resistor layer after firing has a width of 1.
0m11. The length is 1.5 mm and the thickness is 10 μm. Also, the shape of the thick film insulator layer after firing is 11.2mm+, length 1.
0w1 thickness is 10 μm. Example 1 on the alumina substrate after forming the thick film conductor layer, thick film resistor layer and thick film insulator layer.
Similarly, a plated conductor circuit pattern was formed using the full additive method so as to overlap the thick film conductor layer. The electrical characteristics are shown in Table 1.
表 １
間に厚膜、導体端子層を介在させる方法の例示である（
断面図）。Table 1 is an example of a method of interposing a thick film or a conductor terminal layer between (
cross-sectional view).
Claims (1)
路部がセラミック基板上に配されてなるセラミックプリ
ント配線板において、厚膜抵抗体層が先ず形成され、該
厚膜抵抗体層の少なくとも一部上に重なるように、厚膜
導体層が形成され、かつ、該厚膜抵抗体層の少なくとも
一部を覆うように絶縁体層が形成され、かつ厚膜導体層
の少なくとも一部に重なるように、めっきによる導体回
路部が形成されていることを特徴とするセラミックプリ
ント配線板。(1) In a ceramic printed wiring board in which at least a thick film resistor layer and a conductive circuit portion formed by plating are disposed on a ceramic substrate, a thick film resistor layer is first formed, and at least one of the thick film resistor layers is formed. A thick film conductor layer is formed to overlap with the thick film conductor layer, and an insulator layer is formed to cover at least a portion of the thick film resistor layer, and an insulator layer is formed to overlap at least a portion of the thick film conductor layer. A ceramic printed wiring board characterized in that a conductive circuit portion is formed by plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10674689A JPH02284495A (en) | 1989-04-25 | 1989-04-25 | Ceramic printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10674689A JPH02284495A (en) | 1989-04-25 | 1989-04-25 | Ceramic printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02284495A true JPH02284495A (en) | 1990-11-21 |
Family
ID=14441486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10674689A Pending JPH02284495A (en) | 1989-04-25 | 1989-04-25 | Ceramic printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02284495A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019212907A (en) * | 2018-05-30 | 2019-12-12 | 京セラ株式会社 | Circuit board and electronic apparatus including the same |
-
1989
- 1989-04-25 JP JP10674689A patent/JPH02284495A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2019212907A (en) * | 2018-05-30 | 2019-12-12 | 京セラ株式会社 | Circuit board and electronic apparatus including the same |
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