JPH03205892A - Ceramic printed wiring board and its manufacture - Google Patents
Ceramic printed wiring board and its manufactureInfo
- Publication number
- JPH03205892A JPH03205892A JP177590A JP177590A JPH03205892A JP H03205892 A JPH03205892 A JP H03205892A JP 177590 A JP177590 A JP 177590A JP 177590 A JP177590 A JP 177590A JP H03205892 A JPH03205892 A JP H03205892A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thick film
- ceramic
- film resistor
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 34
- 238000007747 plating Methods 0.000 claims abstract description 34
- 239000004020 conductor Substances 0.000 claims abstract description 21
- 238000007772 electroless plating Methods 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 36
- 239000011241 protective layer Substances 0.000 claims description 18
- 239000003054 catalyst Substances 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 23
- 229910052802 copper Inorganic materials 0.000 abstract description 23
- 239000010949 copper Substances 0.000 abstract description 23
- 230000003197 catalytic effect Effects 0.000 abstract description 7
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 abstract description 6
- 238000001035 drying Methods 0.000 abstract description 4
- 238000007650 screen-printing Methods 0.000 abstract description 4
- 235000011121 sodium hydroxide Nutrition 0.000 abstract description 2
- 239000010409 thin film Substances 0.000 abstract 3
- 238000005245 sintering Methods 0.000 abstract 2
- 238000006555 catalytic reaction Methods 0.000 abstract 1
- 230000001376 precipitating effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 239000012190 activator Substances 0.000 description 4
- 230000002950 deficient Effects 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000002845 discoloration Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 235000019253 formic acid Nutrition 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- -1 luteium Chemical compound 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 150000002941 palladium compounds Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000011342 resin composition Substances 0.000 description 1
- 150000003304 ruthenium compounds Chemical class 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000011149 sulphuric acid Nutrition 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、高精度、高特性を有するセラミックプリント
配線板に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a ceramic printed wiring board having high precision and high characteristics.
(従来技術)
湿式めっきを用いたセラミックプリント配線板において
、厚膜抵抗体層とめっき導体回路を組み合わせようとす
るこころみは既に行われている。(Prior Art) Efforts have already been made to combine a thick film resistor layer and a plated conductor circuit in a ceramic printed wiring board using wet plating.
その製法は、大きく2つに分けられ、1つは、必要に応
じて穴をあけたセラミック基板に厚膜抵抗体層及び、抵
抗体保護層を配し、無電解めっきのみ、又は無電解めっ
きと電気めっきを併用し、該穴内壁をも含むセラミック
基板上に所望の厚さの金属層を形成した後、所望部にエ
ッチングレジスト膜を形成し、所望部以外の金属部をエ
ッチングにて除去し、回路パターンを形成する製造方法
でサブトラクティブ法と言われる製法である。もう1つ
の方法は、必要に応じて、穴をあけたセラミック基板に
厚膜抵抗体層及び抵抗体保護層を配し、無電解めっきよ
り該穴内壁をも含む、セラミック基板上に金属層を形成
した後、所望部以外にめっきレジスト膜を形成し、さら
に、所望の厚さの電気めっきを施し、めっきレジスト剥
離後、所望部以外の金属層をエッチング除去し、回路パ
ターンを得る製造法で、セミアディティブ法と言われる
方法である。The manufacturing method can be roughly divided into two types: one is to arrange a thick film resistor layer and a resistor protective layer on a ceramic substrate with holes as necessary, and use only electroless plating, or electroless plating. After forming a metal layer of the desired thickness on the ceramic substrate including the inner wall of the hole using a combination of electroplating and electroplating, an etching resist film is formed on the desired part, and the metal part other than the desired part is removed by etching. This manufacturing method is called the subtractive method, which is a manufacturing method for forming circuit patterns. Another method is to arrange a thick film resistor layer and a resistor protective layer on a ceramic substrate with holes as needed, and then apply a metal layer on the ceramic substrate, including the inner walls of the holes, by electroless plating. After the formation, a plating resist film is formed on areas other than the desired areas, electroplating is further performed to a desired thickness, and after the plating resist is removed, the metal layer is etched away on areas other than the desired areas, thereby obtaining a circuit pattern. This is a method called a semi-additive method.
上記、サブトラクティブ法及び、セミアディティブ法共
に厚膜抵抗体層及び、抵抗体保護層を形成した後、触媒
付与を行うため、本来不要部分である抵抗体保護層上に
も金属膜が形成される。該不要のめっき金属膜は、抵抗
体保護層に対して極めて接着力が弱いため後のエッチン
グ工程で除去されるものの、除去されるまでの工程の多
くの問題を引き起こす。例えば、無電解めっき中に抵抗
体保護層上のめっき金属膜が剥離し、これがめつき液中
に浮遊し、めっき液の劣化の原因となる。あるいは、抵
抗体保護膜とその上のめっき金属膜の間にめっき液やそ
の他の処理液が入り、後の工程でこれら液がにじみ出す
ことによって周囲の回路部を汚染、又は腐食させる。さ
らに、抵抗体保護ガラス上に半球型にふくれた強固なめ
っき膜が生じた場合は、めっきレジスト、あるいは、エ
ッチングレジストのパターン精度に著しい悪影響を与え
る等である。In both the subtractive method and the semi-additive method described above, since the catalyst is applied after forming the thick film resistor layer and the resistor protective layer, a metal film is also formed on the resistor protective layer, which is originally an unnecessary part. Ru. Although the unnecessary plated metal film has extremely weak adhesion to the resistor protection layer, it can be removed in a later etching process, but it causes many problems in the process until it is removed. For example, during electroless plating, the plating metal film on the resistor protective layer peels off and floats in the plating solution, causing deterioration of the plating solution. Alternatively, a plating solution or other processing solution may enter between the resistor protective film and the plated metal film thereon, and this solution may ooze out in a later process, contaminating or corroding the surrounding circuitry. Furthermore, if a strong plating film with a hemispherical bulge is formed on the resistor protection glass, it will have a significant adverse effect on the pattern accuracy of the plating resist or the etching resist.
(発明が解決しようとする課題)
本発明者らは、高精度、高特性を有するセラミックプリ
ント配線板製造方法において従来技術の問題点を解決す
べく鋭意研究を重ねた結果、本製造方法を見出した。(Problems to be Solved by the Invention) The present inventors have conducted intensive research to solve the problems of the conventional technology in a method for manufacturing a ceramic printed wiring board with high precision and high characteristics, and as a result, discovered the present manufacturing method. Ta.
(課題を解決するための手段)
すなわち本発明は、セラミック基板上に厚膜導体層、厚
膜抵抗体層及び該厚膜抵抗体層を保護するための抵抗体
保護層が配されて、且つ、湿式めっきによる導体回路が
配されてなるセラミックプリント配線板において、該厚
膜抵抗体層下のセラミック基板上にも無電解めっきを析
出させるための触媒金属が存在することを特徴とするセ
ラミックプリント配線板であり、前記セラミックプリン
ト配線板において、セラミック基板上に無電解めっきを
析出させるための触媒付与を厚膜抵抗体層及び、抵抗体
保護層を形成する前に行うことを特徴とするセラミック
・プリント配線板の製造方法である。(Means for Solving the Problems) That is, the present invention provides a method in which a thick film conductor layer, a thick film resistor layer, and a resistor protection layer for protecting the thick film resistor layer are arranged on a ceramic substrate, and , a ceramic printed wiring board having a conductor circuit formed by wet plating, characterized in that a catalyst metal for depositing electroless plating is also present on the ceramic substrate under the thick film resistor layer. A ceramic wiring board, characterized in that in the ceramic printed wiring board, a catalyst for depositing electroless plating on the ceramic substrate is applied before forming a thick film resistor layer and a resistor protective layer.・It is a method for manufacturing printed wiring boards.
本発明におけるセラミック基板とは、アルミナ系基板、
窒化アルミニウム基板、炭化ケイ素基板である。また、
前記セラミック系基板はそのまま使用することができる
が、好ましくは、めっき導体回路の密着力を上げるため
にセラミック基板表面を機械的、または/及び、化学的
に粗化したセラミック基板を使用することが好ましい。The ceramic substrate in the present invention refers to an alumina-based substrate,
These are aluminum nitride substrate and silicon carbide substrate. Also,
Although the ceramic substrate can be used as is, it is preferable to use a ceramic substrate whose surface has been mechanically and/or chemically roughened in order to increase the adhesion of the plated conductor circuit. preferable.
これらのセラミック基板は必要によりスルホールを形成
したものでもよい。These ceramic substrates may have through holes formed therein if necessary.
本発明における厚膜導体層とは、例えば、銀、銀/パラ
ジウム、金、銅、ニッケル等の導電性微粉末、有機ビヒ
クル、金属ビヒクル、金属酸化物および/またはガラス
フリットで構成されたぺ一ストを適当な条件下で焼成し
たものである。The thick film conductor layer in the present invention refers to a layer made of conductive fine powder of silver, silver/palladium, gold, copper, nickel, etc., an organic vehicle, a metal vehicle, a metal oxide, and/or a glass frit. It is made by firing the steel under appropriate conditions.
本発明における厚膜抵抗体層とは、例えば、銀、パラジ
ウム、ルテニウム化合物、タンタル、スズ、インジウム
の酸化物、ホウ化ランタン、炭素などの導電性微粉末、
ガラスフリット、金属酸化物、及び、有機ビヒクルで構
成されたペーストまたはフェノール、エポキシ、ポリイ
ミドなどの樹脂に前記導電性微粉末を配合した樹脂組成
物から成り、適当な条件下で焼成又は硬化したものであ
る。The thick film resistor layer in the present invention includes, for example, conductive fine powder of silver, palladium, ruthenium compound, tantalum, tin, indium oxide, lanthanum boride, carbon, etc.
A paste composed of a glass frit, a metal oxide, and an organic vehicle, or a resin composition in which the conductive fine powder is blended with a resin such as phenol, epoxy, or polyimide, and is fired or hardened under appropriate conditions. It is.
本発明における抵抗体保護層とは厚膜抵抗体上に形成さ
れた耐薬品性をもった絶縁体層で、例えば、ガラス質フ
リット、金属酸化合物、及び有機ビヒクルで構成された
ペースト、またはエボキシ、フェノール、ポリイミドな
どの樹脂から成り、適当な条件下で焼成又は硬化する。The resistor protective layer in the present invention is an insulating layer with chemical resistance formed on a thick film resistor, such as a paste composed of a glassy frit, a metal acid compound, and an organic vehicle, or an epoxy resin. , phenol, polyimide, etc., and is fired or hardened under appropriate conditions.
本発明における無電解めっきとは、スズ、ニッケル、銅
、銀、金、白金、ルテイウム、コバルトの無電解めっき
である。Electroless plating in the present invention refers to electroless plating of tin, nickel, copper, silver, gold, platinum, luteium, and cobalt.
本発明における触媒付与とは、無電解めっきのための触
媒金属をセラミック表面に吸着させることであり、この
触媒液は公知のパラジウム化合物溶液が好ましいが、銅
、白金、金及び、他の金属化合物溶液でもよい。この触
媒金属は、厚膜抵抗体層を形成する際に酸化され、触媒
能力を失う場合があるため無電解めっきを行う前に還元
処理を行う。この還元法は、例えば、蟻酸に浸漬後15
0℃で加熱処理をする方法、又は、還元剤溶液に浸漬す
る方法があるが特に限定されるものではない。Catalyzing in the present invention means adsorbing a catalytic metal for electroless plating onto the ceramic surface, and the catalytic solution is preferably a known palladium compound solution, but it may also be a solution of copper, platinum, gold, or other metal compounds. A solution may be used. This catalytic metal is oxidized when forming the thick film resistor layer and may lose its catalytic ability, so a reduction treatment is performed before electroless plating. This reduction method can be used, for example, for 15
There are a method of heat treatment at 0° C. and a method of immersion in a reducing agent solution, but these are not particularly limited.
(実施例)
本発明を更に詳細に説明するために実施例を挙げるが、
本発明はこれらの実施例によって何ら限定されるもので
ない。(Example) Examples will be given to explain the present invention in more detail.
The present invention is not limited in any way by these Examples.
く実施例−1〉
所望の箇所にスルホールを配したアルミナを96%含有
する縦50.8m+a、横50.8m−厚さ0.835
+o+aの白色セラミック基板を340℃に保持された
溶融苛性ソーダに10分間浸漬し、セラミック基板表面
を適当に粗化した。次に、前記セラミック基板全面に無
電解銅めっきのためし触媒付与を行った。触媒付与プロ
セスは、PTHプロセス4[シプレイ ファーイースト
■製]ヲ用いた。上記セラミック基板を温風乾燥後、厚
膜導体焼成ペーストをスクリーン印刷法により塗布し、
150℃で10分間乾燥し、900℃で10分間(トー
タル35分間)空気焼成し、厚膜導体端子層を形成した
。厚膜導体端子層間の間隔は1. 0Uとした。次いで
両厚膜導体端子層のそれぞれ一部重なる様に、厚膜抵抗
体焼成ペース} (R9310N)[昭栄化学工業株製
]をスクリーン印刷法により塗布し、150℃で、10
分間乾燥し、850℃で10分間(トータル35分間)
空気焼成した。更に、厚膜抵抗体を保護するため厚膜抵
抗体層全面を被うように厚膜抵抗体保護層(オーバーコ
ート用ガラスペーストG#5238)[昭栄化学工業■
製コをスクリーン印刷法により塗布し、150℃で10
分間乾燥し、その後、600℃で10分間(トータル3
5分間)空気中焼成した。次に上記セラミック基板を9
0%の蟻酸に5分間浸漬後、150℃で10分間乾燥し
、無電解銅めっき浴に浸漬することによってセラミック
基板上に約1.0μmの銅めっき皮膜を得た。無電解銅
めっき浴には、キューポジット250浴[シプレイ フ
ァー イースト■製コを用いた。このとき、厚膜抵抗体
保護層上には銅めっき皮膜は形成されなかった。さらに
、ネガ型レジストを感光性ドライフイルムAP838[
東京応化工業1N]を用いて所望部以外の部分に形成し
、所望部に電気銅めっきを約10μm析出させた。その
後、化学鋼めっき部分を0.1M−H2 02 /O.
IM・H2SO4のエッチング液で除去し、図1に示す
回路を形成した。この方法にて、50μmのラインスペ
ースのファインパターンを得ることができた。不良率は
O%であった(n=100)。Example-1〉 Containing 96% alumina with through holes arranged at desired locations, length 50.8 m + a, width 50.8 m - thickness 0.835
A +o+a white ceramic substrate was immersed in molten caustic soda maintained at 340° C. for 10 minutes to appropriately roughen the surface of the ceramic substrate. Next, a catalyst was applied to the entire surface of the ceramic substrate for electroless copper plating. The catalyst application process used PTH process 4 [manufactured by Shipley Far East ■]. After drying the above ceramic substrate with hot air, a thick film conductor firing paste was applied by screen printing method,
It was dried at 150° C. for 10 minutes and air fired at 900° C. for 10 minutes (35 minutes in total) to form a thick film conductor terminal layer. The spacing between thick film conductor terminal layers is 1. It was set to 0U. Next, thick film resistor firing paste (R9310N) [manufactured by Shoei Kagaku Kogyo Co., Ltd.] was applied by screen printing so that both thick film conductor terminal layers were partially overlapped, and heated at 150°C for 10 minutes.
Dry for 10 minutes at 850℃ (total 35 minutes)
Air fired. Furthermore, in order to protect the thick film resistor, a thick film resistor protective layer (glass paste for overcoat G#5238) [Shoei Chemical Co., Ltd.] was applied so as to cover the entire surface of the thick film resistor layer.
Coating material was applied by screen printing method and heated at 150℃ for 10 minutes.
Dry for 1 minute, then at 600℃ for 10 minutes (total 3 minutes).
5 minutes) in air. Next, attach the above ceramic substrate to 9
After being immersed in 0% formic acid for 5 minutes, it was dried at 150° C. for 10 minutes and immersed in an electroless copper plating bath to obtain a copper plating film of about 1.0 μm on the ceramic substrate. As the electroless copper plating bath, Cuposit 250 bath [manufactured by Shipley Far East ■] was used. At this time, no copper plating film was formed on the thick film resistor protective layer. Furthermore, the negative resist was coated with photosensitive dry film AP838 [
Tokyo Ohka Kogyo 1N] was used to deposit electrolytic copper plating in a thickness of about 10 μm on the desired portions. After that, the chemical steel plated part was coated with 0.1M-H2 02 /O.
It was removed using an IM.H2SO4 etching solution, and the circuit shown in FIG. 1 was formed. By this method, a fine pattern with a line space of 50 μm could be obtained. The defective rate was 0% (n=100).
〈実施例−2〉
実施例−1で示した同様の方法で適度に粗化したセラミ
ック基板の全面に無電解銅めっきのための触媒を付着さ
せた。触媒付与プロセスはアクチベーターシステムネオ
ガント[日本シェーリング■コを用いた。上記基板を温
風乾燥後、実施例−1と同じ方法で厚膜導体端子層、厚
膜抵抗体層及び、厚膜抵抗体保護層を形成し、触媒金属
還元処理を行った。次に、上記セラミック基板を無電解
めっき浴に浸漬し、セラミック基板上に約10μmの銅
めっき皮膜を得た。無電解めっき浴はkc−10浴[日
本鉱業■製]を用いた。このとき、厚膜抵抗体保護層上
には、銅めっき皮膜は析出しなかった。さらに、ポジ型
エッチングレジストを感光性ドライフイルム[AP 8
3 8東京応化工業■製コを用いて形成し、I M−
H 2 0 2 / I M・H2SO4のエッチング
液にて、非回路部分を除去し、レジストを剥離した。こ
の方法にて、50μmラインスペースのファインパター
ンが得られた。不良率は0%であった(n=100)。<Example 2> A catalyst for electroless copper plating was deposited on the entire surface of a ceramic substrate that had been appropriately roughened using the same method as shown in Example 1. The catalyst application process used the activator system Neogant [Nippon Schering Co., Ltd.]. After drying the substrate with warm air, a thick film conductor terminal layer, a thick film resistor layer, and a thick film resistor protective layer were formed in the same manner as in Example 1, and a catalytic metal reduction treatment was performed. Next, the ceramic substrate was immersed in an electroless plating bath to obtain a copper plating film of about 10 μm on the ceramic substrate. As the electroless plating bath, KC-10 bath [manufactured by Nippon Mining Co., Ltd.] was used. At this time, no copper plating film was deposited on the thick film resistor protective layer. Furthermore, the positive etching resist was coated with a photosensitive dry film [AP 8
3 8 Tokyo Ohka Kogyo Co., Ltd.
The non-circuit portions were removed using an etchant of H 2 O 2 /IM·H 2 SO 4 and the resist was peeled off. By this method, a fine pattern with a line spacing of 50 μm was obtained. The defective rate was 0% (n=100).
〈実施例−3〉
実施例−1で示した同様の方法で適度に粗化したセラミ
ック基板に、実施例−1で示した同様の方法で厚膜導体
端子層を形成した。次に上記基板の全面に無電解銅めっ
きのための触媒を付着させた。触媒付与プロセスは、ア
クチベーターシステム ネオガント[日本シェーリング
■コを用いた。<Example 3> A thick film conductor terminal layer was formed in the same manner as in Example 1 on a ceramic substrate that had been appropriately roughened in the same manner as in Example 1. Next, a catalyst for electroless copper plating was deposited on the entire surface of the substrate. The catalyst application process used the activator system Neogant [Nippon Schering Co., Ltd.].
上記基板を温風乾燥後、実施例−1と同様の方法で厚膜
抵抗体及び厚膜抵抗体保護層を形成し、触媒金属還元処
理を行った。次に、上記セラミック基板を無電解めっき
浴に浸漬し、セラミック基板上に約10μmの銅めっき
皮膜を得た。無電解めっき浴はKC− 1 0浴[日本
鉱業■製コを用いた。After drying the substrate with warm air, a thick film resistor and a thick film resistor protective layer were formed in the same manner as in Example 1, and a catalytic metal reduction treatment was performed. Next, the ceramic substrate was immersed in an electroless plating bath to obtain a copper plating film of about 10 μm on the ceramic substrate. The electroless plating bath used was KC-10 bath [manufactured by Nippon Mining Co., Ltd.].
このとき、厚膜抵抗体保護層上には、銅めっき皮膜は析
出しなかった。さらに、ポジ型エッチングレジストを感
光性ドライフイルム[AP838東京応化工業番力製]
を用いて形成し、1M−H202 /IM−H2So4
のエッチング液にて、非回路部分を除去し、レジストを
剥離した。この方法にて、50μmラインスペースのフ
ァインパターンが得られた。不良率はO%であった(n
= 1 00)。At this time, no copper plating film was deposited on the thick film resistor protective layer. Furthermore, a positive etching resist was coated with a photosensitive dry film [AP838 manufactured by Tokyo Ohka Kogyo Banriki].
1M-H202 /IM-H2So4
The non-circuit parts were removed using an etching solution, and the resist was peeled off. By this method, a fine pattern with a line spacing of 50 μm was obtained. The defective rate was 0% (n
= 1 00).
〈比較例−1〉
実施例−1で示した同様の方法で適度に粗化したセラミ
ック基板に厚膜抵抗体層、厚膜導体端子層及び、厚膜抵
抗体保護層を形成後、上記セラミック基板の全面に無電
解銅めっきのための触媒付与を行い、つづいて、無電解
銅めっきを行った。<Comparative Example-1> After forming a thick-film resistor layer, a thick-film conductor terminal layer, and a thick-film resistor protective layer on a suitably roughened ceramic substrate using the same method as shown in Example-1, the above ceramic A catalyst for electroless copper plating was applied to the entire surface of the substrate, and then electroless copper plating was performed.
触媒付与プロセスは、アクチベータシステムネオガント
[日本シェーリング■コを用い、無電解銅めっき浴には
キューポジト250浴[シプレイファー イースト■製
]を用いた。このとき、厚膜抵抗体保護層上の一部分の
めっき膜は、厚膜抵抗体保護層上から剥離し、めっき洛
中に浮遊した。For the catalyst application process, the activator system Neogant (manufactured by Nippon Schering Co., Ltd.) was used, and the electroless copper plating bath was Cuposito 250 bath (manufactured by Shipley Far East Co., Ltd.). At this time, a portion of the plating film on the thick film resistor protective layer was peeled off from the thick film resistor protective layer and floated in the plating layer.
さらに、無電解めっき後、厚膜抵抗体層周囲の銅めっき
被膜に顕著な変色が見られた。次に、実施例−1と同様
の方法で回路を形成した。この方法によって、50μm
ラインスペースのファインパターンに導体短絡不良が発
生した。不良率は80%であった(n=100)。Furthermore, after electroless plating, significant discoloration was observed in the copper plating film around the thick film resistor layer. Next, a circuit was formed in the same manner as in Example-1. By this method, 50 μm
A conductor short-circuit failure occurred in the line space fine pattern. The defect rate was 80% (n=100).
く比較例−2〉
実施例−1で示した同様の方法で適当に粗化したセラミ
ック基板に厚膜抵抗体層厚膜導体端子層及び、厚膜抵抗
体保護層を形成後、上記セラミック基板の全面に無電解
めっきのための触媒付与を行い、つづいて無電解銅めっ
きを行い、約10μmの銅めっき被膜を得た。触媒付与
プロセスはアクチベータシステムネオガント[日本シェ
ーリング■コを用い、無電解めっき浴はKC− 1 0
浴[日本鉱業■製コを用いた。このとき厚膜抵抗体保護
膜上の銅めっき皮膜にふくれ不良が発生した。Comparative Example-2> After forming a thick-film resistor layer, a thick-film conductor terminal layer, and a thick-film resistor protective layer on a suitably roughened ceramic substrate using the same method as in Example-1, the ceramic substrate was A catalyst for electroless plating was applied to the entire surface, and then electroless copper plating was performed to obtain a copper plating film of about 10 μm. The catalyst application process used the activator system Neogant [Nippon Schering Co., Ltd., and the electroless plating bath was KC-10.
Bath [made by Nippon Mining Co., Ltd.] was used. At this time, a blistering defect occurred in the copper plating film on the thick film resistor protective film.
次に実施例−2と同じ方法で回路を形成した。この方法
によって、導体欠損不良が発生した。不良率は76%で
あった(n= 1 0 0)。Next, a circuit was formed in the same manner as in Example-2. This method resulted in conductor loss defects. The defective rate was 76% (n=100).
(発明の効果)
本発明の実施により、厚膜抵抗体保護膜上に密着性の劣
るめっき皮膜の形成が防止できるため、これによって引
き起こされる問題を解消できる。(Effects of the Invention) By carrying out the present invention, it is possible to prevent the formation of a plating film with poor adhesion on the thick film resistor protective film, thereby solving the problems caused by this.
よって、高精度、高信頼性を持ったセラミックプリント
配線板の製造方法として極めて有益である。Therefore, it is extremely useful as a method for manufacturing ceramic printed wiring boards with high precision and high reliability.
図1は、実施例1、2及び比較例1、2の評価に用いた
パターン平面概略図である。
1. めっき導体50μmラインスペース2 厚膜抵抗
体層及び、抵抗体保護層
3. 導体端子層FIG. 1 is a schematic plan view of a pattern used for evaluation of Examples 1 and 2 and Comparative Examples 1 and 2. 1. Plated conductor 50μm line space 2 Thick film resistor layer and resistor protection layer 3. conductor terminal layer
Claims (2)
び、該厚膜抵抗体層を保護するための抵抗体保護層が配
されて、且つ、湿式めっきによる導体回路が配されてな
るセラミックプリント配線板において、該厚膜抵抗体層
下のセラミック基板上にも無電解めっきを析出させるた
めの触媒金属が存在することを特徴とするセラミックプ
リント配線板。(1) A thick film conductor layer, a thick film resistor layer, and a resistor protection layer for protecting the thick film resistor layer are arranged on a ceramic substrate, and a conductor circuit by wet plating is arranged. 1. A ceramic printed wiring board characterized in that a catalyst metal for depositing electroless plating is also present on the ceramic substrate under the thick film resistor layer.
法において、セラミック基板上に無電解めっきを析出さ
せるための触媒付与を厚膜抵抗体層及び、抵抗体保護層
を形成する前に行うことを特徴とするセラミックプリン
ト配線板の製造方法。(2) Claim 1. A method for manufacturing a ceramic printed wiring board, characterized in that a catalyst for depositing electroless plating on a ceramic substrate is applied before forming a thick film resistor layer and a resistor protective layer. Method of manufacturing the board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP177590A JPH03205892A (en) | 1990-01-08 | 1990-01-08 | Ceramic printed wiring board and its manufacture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP177590A JPH03205892A (en) | 1990-01-08 | 1990-01-08 | Ceramic printed wiring board and its manufacture |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03205892A true JPH03205892A (en) | 1991-09-09 |
Family
ID=11510950
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP177590A Pending JPH03205892A (en) | 1990-01-08 | 1990-01-08 | Ceramic printed wiring board and its manufacture |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03205892A (en) |
-
1990
- 1990-01-08 JP JP177590A patent/JPH03205892A/en active Pending
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