JPH0227858B2 - - Google Patents
Info
- Publication number
- JPH0227858B2 JPH0227858B2 JP57022353A JP2235382A JPH0227858B2 JP H0227858 B2 JPH0227858 B2 JP H0227858B2 JP 57022353 A JP57022353 A JP 57022353A JP 2235382 A JP2235382 A JP 2235382A JP H0227858 B2 JPH0227858 B2 JP H0227858B2
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- circuit
- mismatch
- synchronization
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0605—Special codes used as synchronising signal
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57022353A JPS58139540A (ja) | 1982-02-15 | 1982-02-15 | フレ−ム同期保護回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57022353A JPS58139540A (ja) | 1982-02-15 | 1982-02-15 | フレ−ム同期保護回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58139540A JPS58139540A (ja) | 1983-08-18 |
| JPH0227858B2 true JPH0227858B2 (cs) | 1990-06-20 |
Family
ID=12080280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57022353A Granted JPS58139540A (ja) | 1982-02-15 | 1982-02-15 | フレ−ム同期保護回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58139540A (cs) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3229079A1 (de) * | 1982-08-04 | 1984-02-09 | Bayer Ag, 5090 Leverkusen | Formmassen aus vinylchloridpolymerisat, pfropfpolymeren und polymeren weichmachern mit hoher alterungsbestaendigkeit |
| JPH0377446A (ja) * | 1989-08-19 | 1991-04-03 | Fujitsu Ltd | 前方後方保護カウンタ |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5430244A (en) * | 1977-08-12 | 1979-03-06 | Konishi Kk | Gel composition |
-
1982
- 1982-02-15 JP JP57022353A patent/JPS58139540A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58139540A (ja) | 1983-08-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4920535A (en) | Demultiplexer system | |
| US4404675A (en) | Frame detection and synchronization system for high speed digital transmission systems | |
| US3950616A (en) | Alignment of bytes in a digital data bit stream | |
| CA1212723A (en) | System for transmitting digital information signals | |
| US5228036A (en) | Frame synchronization stabilizer | |
| US3938086A (en) | Circuit arrangement for correcting slip errors in pcm receivers | |
| JPH0227858B2 (cs) | ||
| US3546592A (en) | Synchronization of code systems | |
| CA2052811C (en) | Framing bit sequence detection in digital data communication systems | |
| JP2710525B2 (ja) | ジッタ抑制回路 | |
| US4771421A (en) | Apparatus for receiving high-speed data in packet form | |
| JPS63232652A (ja) | フレ−ム同期保護回路 | |
| JP2502406Y2 (ja) | ラインエラ―計数装置 | |
| SU1518903A2 (ru) | Устройство дл выделени маркера кадровой синхронизации | |
| JP2748912B2 (ja) | フレーム同期回路 | |
| SU1644397A2 (ru) | Устройство дл выделени сигнала фазового пуска | |
| JPH03235441A (ja) | セル同期回路 | |
| JPS60144046A (ja) | フレ−ム同期回路 | |
| JP2849952B2 (ja) | フレーム同期回路 | |
| JPH03187542A (ja) | 同期回路 | |
| JPH0691514B2 (ja) | ビツト列一致判定回路 | |
| JPH0581098B2 (cs) | ||
| JPH0314250B2 (cs) | ||
| JPS6410975B2 (cs) | ||
| JPH07107071A (ja) | 制御信号処理回路 |