JPH02275633A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH02275633A
JPH02275633A JP1097947A JP9794789A JPH02275633A JP H02275633 A JPH02275633 A JP H02275633A JP 1097947 A JP1097947 A JP 1097947A JP 9794789 A JP9794789 A JP 9794789A JP H02275633 A JPH02275633 A JP H02275633A
Authority
JP
Japan
Prior art keywords
trench
insulating film
integrated circuit
diffusion layer
metal wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1097947A
Other languages
Japanese (ja)
Inventor
Takashi Kusakari
草刈 隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1097947A priority Critical patent/JPH02275633A/en
Publication of JPH02275633A publication Critical patent/JPH02275633A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To lower electric resistance and current density in a joining section on a semiconductor substrate by forming a trench to a metallic wiring and the joining section and spreading the area of joining. CONSTITUTION:An inter-layer insulating film 3a is shaped onto a silicon substrate 1a, and a diffusion layer 2a is formed. The silicon substrate 1a is etched while using the contact hole 5a of the inter-layer insulating film 3a as a mask and a trench 6a is shaped, and a metallic wiring 4a is grown and the trench 6a is buried. Consequently, the diffusion layer 2a and the metallic wiring 4a are brought into contact on the surface of the trench 6a, thus increasing a contact area. Accordingly, electric resistance in a joining section is lowered, and current density is reduced, thus preventing the generation of electro- migration.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路に関し、特に金属配線と半導体
基板の拡散層との接合部の形状に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to the shape of a joint between a metal wiring and a diffusion layer of a semiconductor substrate.

〔従来の技術〕[Conventional technology]

従来の半導体集積回路における金属配線とシリコン基板
の拡散層との接合部の形状は第3図に示すように平面的
構造を有していた。
In a conventional semiconductor integrated circuit, the shape of a junction between a metal wiring and a diffusion layer of a silicon substrate has a planar structure as shown in FIG.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の金属配線とシリコン基板上の拡散層との
接合部の形状は平面的であるため、微細加工技術の発展
に伴って接合面積が減少してきている。またそれに伴い
、接合部(コンタクト孔)の形状が悪化してきている。
Since the above-described conventional bonding portion between the metal wiring and the diffusion layer on the silicon substrate has a planar shape, the bonding area has been decreasing with the development of microfabrication technology. In addition, as a result, the shape of the joint portion (contact hole) has deteriorated.

従って接合部での電気抵抗が増大して特性不良になった
り、電流密度が増大してエレクトロマイグレーションが
発生し易い等の問題がある。
Therefore, there are problems such as an increase in electrical resistance at the junction, resulting in poor characteristics, and an increase in current density, which tends to cause electromigration.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体集積回路は、半導体基板上に設けられた
絶縁膜と、前記絶縁膜に設けられたコンタクト孔を介し
て前記半導体基板の所定部と接触する金属配線とを有す
る半導体集積回路において、前記半導体基板の前記コタ
クト孔部に設け−られたトレンチを有し、前記金属配線
が前記トレンチを埋め込んでいるというものである。
A semiconductor integrated circuit of the present invention includes an insulating film provided on a semiconductor substrate, and a metal wiring that contacts a predetermined portion of the semiconductor substrate through a contact hole provided in the insulating film. A trench is provided in the contact hole of the semiconductor substrate, and the metal wiring buries the trench.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の実施例1を示す半導体チ、ンブの断面
図である。シリコン基板1aに層間絶縁膜3aを形成し
、拡散層2aを形成する。次に、層間絶縁膜3aのコン
タクト孔5aをマスクにしてシリコン基板1aをエツチ
ングしてトレンチ6aを形成し、その後金属配線4aを
成長させてトレンチ6aを埋め込む。
FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention. An interlayer insulating film 3a is formed on a silicon substrate 1a, and a diffusion layer 2a is formed. Next, using the contact hole 5a of the interlayer insulating film 3a as a mask, the silicon substrate 1a is etched to form a trench 6a, and then a metal wiring 4a is grown to fill the trench 6a.

トレンチ6aの表面で拡散M2aと金属配線4aが接触
しているので接触面積が大きくとれる。
Since the diffusion M2a and the metal wiring 4a are in contact with each other on the surface of the trench 6a, a large contact area can be obtained.

第2図は本発明の実施例2を示す半導体チップの断面図
である。
FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention.

シリコン基板1bに眉間絶縁膜3bを成長させ、接合部
のシリコン基板をエツチングしてトレンチ6bを形成す
る。このとき層間絶縁膜3bにはコンタクト孔5bが形
成される。次にトレンチ外周に沿って拡散層2bを形成
しその後金属配線4bを成長させる。
A glabellar insulating film 3b is grown on the silicon substrate 1b, and the silicon substrate at the joint portion is etched to form a trench 6b. At this time, a contact hole 5b is formed in the interlayer insulating film 3b. Next, a diffusion layer 2b is formed along the outer periphery of the trench, and then a metal wiring 4b is grown.

この実施例では1〜レンチ表面からみて拡散層の厚さが
一定であり、金属配線と拡散層以外の半導体部分で接触
することがないので一層確実にコンタクトをとれるとい
う利点がある。
In this embodiment, the thickness of the diffusion layer is constant when viewed from the surface of the wrench, and there is no contact between the metal wiring and the semiconductor portion other than the diffusion layer, so there is an advantage that contact can be made more reliably.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、金属配線と半導体基板上
の接合部に、トレンチを設けることにより接合面積を広
げまたそれに伴い接合部の形状を良くすることができる
。従って接合部での電気抵抗を小さくし、また電流密度
を小さくでき半導体集積回路の特性及び信顆性の改善が
可能となる効果がある。
As explained above, in the present invention, by providing a trench at the joint between the metal wiring and the semiconductor substrate, the joint area can be expanded and the shape of the joint can be improved accordingly. Therefore, the electrical resistance at the junction can be reduced, and the current density can be reduced, making it possible to improve the characteristics and reliability of the semiconductor integrated circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例1を示す半導体チップの断面図
、第2図は本発明の実施例2を示す半導体チップの断面
図、第3図は従来例を示す半導体チップの断面図である
。 1、la、lb−シリコン基板、2.2a。 2b・・・拡散層、3.3a、3b・・・層間絶縁膜、
4.4a、4b・・−金属配線、5.5a、5b・・・
コンタクト孔、6a  6b・・・トレンチ。
FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention, FIG. 2 is a sectional view of a semiconductor chip showing a second embodiment of the present invention, and FIG. 3 is a sectional view of a semiconductor chip showing a conventional example. be. 1, la, lb - silicon substrate, 2.2a. 2b...diffusion layer, 3.3a, 3b... interlayer insulating film,
4.4a, 4b...-metal wiring, 5.5a, 5b...
Contact hole, 6a 6b...trench.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に設けられた絶縁膜と、前記絶縁膜に設け
られたコンタクト孔を介して前記半導体基板の所定部と
接触する金属配線とを有する半導体集積回路において、
前記半導体基板の前記コタクト孔部に設けられたトレン
チを有し、前記金属配線が前記トレンチを埋め込んでい
ることを特徴とする半導体集積回路。
In a semiconductor integrated circuit having an insulating film provided on a semiconductor substrate, and a metal wiring that contacts a predetermined portion of the semiconductor substrate through a contact hole provided in the insulating film,
A semiconductor integrated circuit comprising a trench provided in the contact hole of the semiconductor substrate, and the metal wiring embeds the trench.
JP1097947A 1989-04-17 1989-04-17 Semiconductor integrated circuit Pending JPH02275633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1097947A JPH02275633A (en) 1989-04-17 1989-04-17 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1097947A JPH02275633A (en) 1989-04-17 1989-04-17 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH02275633A true JPH02275633A (en) 1990-11-09

Family

ID=14205867

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1097947A Pending JPH02275633A (en) 1989-04-17 1989-04-17 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH02275633A (en)

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