JP2003188174A - Semiconductor device and its fabricating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a dummy wiring pattern in which (1) restriction on the pattern is relaxed, (2) no extra step is required other than a dummy wiring pattern, (3) complication of process is avoided, (4) dependency on other wiring layer is eliminated, and (5) the potential is fixed such that patterns not fixed to any potential are reduced as compared with a conventional method. <P>SOLUTION: A dummy diffusion pattern 9 is formed on a semiconductor device having an actual diffusion pattern. An interlayer insulation film 10 is formed thereon and through holes 11 are made through the interlayer insulation film. Subsequently, an actual wiring pattern 1 and a dummy wiring pattern 2 are formed on the interlayer insulation film. In this regard, the dummy wiring pattern 2 is arranged to overlap the dummy diffusion pattern 9 and connected electrically therewith through the through holes 11 thus forming a dummy wiring pattern 2 having a fixed potential. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for processing wirings of fine elements and an interlayer film.

[0002]

2. Description of the Related Art As semiconductor elements are highly integrated and miniaturized, processing problems due to variations in pattern density on the same surface of a semiconductor device are becoming apparent. For example, in the step of etching the wiring layer, the degree of etching depends on the density of the wiring pattern, so that excessive or insufficient etching occurs. Also, C
Even in the flattening process of the interlayer film by MP (Chemical Mechanical Polishing) or the like, nonuniformity of the film thickness called dishing occurs due to the density of the wiring pattern.

Conventionally, a dummy wiring pattern is provided in a sparse portion of the wiring pattern on the semiconductor device to alleviate the difference in in-plane sparseness and denseness.

However, these wiring dummy patterns are surrounded by an interlayer film and are not fixed to any potential. For this reason, the parasitic capacitance between the wiring dummy pattern and the actual wiring pattern becomes large, and this becomes a large resistance, which causes a decrease in the circuit operation speed. In addition, the potential change of the actual wiring pattern also changes the potential of the wiring dummy pattern coupled by this parasitic capacitance. This affects the circuit operation, which makes the operation unstable. Further, since the addition of the parasitic capacitance value affects the signal speed, it is difficult to accurately estimate the signal delay value, and it is difficult to calculate the LSI design.

As means for solving these, for example, a method disclosed in Japanese Patent Laid-Open No. 6-69201, which reduces the parasitic capacitance by increasing the distance between the dummy wiring pattern and the actual wiring pattern, and Japanese Patent Laid-Open No. 2000-286263.
There is a method of removing the parasitic capacitance by hollowing out the wiring dummy pattern installed after the completion of the planarization by CMP, which is disclosed in Japanese Patent Laid-Open Publication No. 2003-242242.

However, in the case of Japanese Patent Laid-Open No. 6-69201, the layout design rule becomes complicated because the pattern is restricted, and a special tool such as a pattern detection program is required. Japanese Patent Laid-Open No. 2000-28626
In the case of Japanese Unexamined Patent Publication No. 3, there is a problem that a step of removing the wiring dummy pattern must be added after the flattening is completed and the reliability of the cavity portion must be ensured.

There is also a method of installing another insulator in place of the wiring dummy pattern so that parasitic capacitance does not occur, but in this case, the manufacturing process becomes much more complicated than when the wiring dummy pattern is formed. There is a problem that ends up.

In this way, the method of removing the parasitic capacitance or the method of not generating the parasitic capacitance complicates the design rule and the manufacturing process.

On the other hand, as another means, JP-A-8-213
As disclosed in Japanese Patent Laid-Open No. 763/763, a method of fixing the potential of a wiring dummy pattern through another wiring layer in a multilayer structure, and as shown in Japanese Patent Laid-Open No. 11-321738, a wiring grid is provided on a semiconductor device, all of which are provided. A dummy wiring pattern whose potential is fixed is placed on the wiring grid of, then the actual wiring pattern is placed at the required location, and then the wiring dummy pattern around the actual wiring pattern is deleted to create the actual wiring pattern and the wiring dummy. There is a method of creating a wiring layout that is not connected to the pattern.

When the potential of the wiring dummy pattern is fixed in this way, the parasitic capacitance value between the wirings becomes uniform, so that a large decrease in circuit operation and unstable operation can be suppressed. Design calculations are possible.

However, the method disclosed in Japanese Patent Laid-Open No. 8-213763 requires another wiring layer different from the layer in which the potential of the wiring dummy pattern is fixed. Also, with it,
There is a problem that layout restrictions are imposed on other wiring layers.

In the method disclosed in Japanese Patent Laid-Open No. 11-321738, since the wiring layout is created on a plane, for example, when the wiring dummy pattern is arranged inside the actual wiring pattern formed in the loop shape. In some cases, the wiring dummy pattern is electrically isolated.

In view of the above points, the present invention reduces pattern restrictions, does not require addition of a new process other than formation of a wiring dummy pattern, does not complicate the process, and does not use other wiring layers. Not depend on,
It is an object of the present invention to provide a semiconductor device in which a wiring dummy pattern whose potential is fixed is laid out so as to reduce all wiring dummy patterns which are not fixed to any potential, and a manufacturing method thereof.

[0014]

In order to achieve the above object, in the invention described in claim 1, a step of preparing a semiconductor substrate (3) having a semiconductor layer (4, 5) and a surface layer portion of the semiconductor layer. Forming a plurality of trenches (6) in the substrate to form an actual diffusion pattern (8) and a diffusion dummy pattern (9), and forming an interlayer insulating film (10) on the semiconductor layer. The step of forming a plurality of through holes (11) in the film, and the real wiring pattern is arranged on the interlayer insulating film so as to overlap the real diffusion pattern, and the real diffusion pattern and the electrical diffusion pattern are electrically connected through the through holes. And connecting the wiring dummy pattern to the diffusion dummy pattern so as to overlap the diffusion dummy pattern, and electrically connecting the wiring dummy pattern to the diffusion dummy pattern through the through hole. It is set to.

According to this method, since the wiring dummy pattern is simply connected to the diffusion dummy pattern existing below this, there are few restrictions on the wiring dummy pattern,
Wiring design rules are not complicated. In addition, since the wiring dummy pattern can be designed almost independently of the actual wiring pattern, there is little influence on the layout of the actual wiring pattern, and the degree of freedom in layout design is high.

The diffusion dummy pattern is formed in STI-CMP planarization in many semiconductor devices,
In manufacturing such a semiconductor device, it is not necessary to add a new process other than forming the wiring dummy pattern. Further, there is no need for a complicated manufacturing process as in the case of forming an insulating pattern instead of the wiring dummy pattern.

Further, in this method, another wiring layer is not required to fix the potential of the wiring dummy pattern, and the layout of the actual wiring pattern and the wiring dummy pattern whose potential is fixed is created in the same layer. can do. As a result, there are no restrictions on the wiring layout to other wiring layers.

Further, as in the case where the wiring dummy pattern is arranged inside the loop-shaped actual wiring pattern, the potential can be fixed even in the wiring dummy pattern which is electrically isolated in the past.

Further, a plurality of wiring dummy patterns may be formed as in claim 2, and at least one of the plurality of wiring dummy patterns is formed so as to overlap a plurality of diffusion dummy patterns. It may be electrically connected to the diffusion dummy pattern.

The invention according to claim 1 or 2 provides the semiconductor device according to claim 3 or 4.

The reference numerals in parentheses of the above-mentioned means indicate the correspondence with the concrete means described in the embodiments described later.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 shows a wiring layout pattern when a region of a semiconductor device formed by applying an embodiment of the present invention is viewed from above a semiconductor substrate. The shaded areas are various wiring patterns.

In FIG. 1, an actual wiring pattern 1 is formed on the surface of the semiconductor device. As the actual wiring pattern 1, for example, a signal line 1a and a ground line 1b are arranged. Then, a plurality of substantially rectangular wiring dummy patterns 2a as wiring dummy patterns 2 and a plurality of substantially rectangular wiring dummy patterns are connected in a region where the signal line 1a and the ground line 1b are not arranged. Two
b, and a substantially rectangular wiring dummy pattern 2c connected to the ground line 1b.

FIG. 2 shows a sectional view of a part of the semiconductor device shown in FIG. The P-type well 4a of the first semiconductor layer 4 is formed on the semiconductor substrate 3, and the second semiconductor layer 5 is further formed thereon. A semiconductor layer is constituted by these first and second semiconductor layers. Then, the second semiconductor layer 5
A trench 6 is formed so as to penetrate from the surface to the P-type well 4a. At this time, the second semiconductor layer 5 is surrounded by the trench 6, and a convex portion that shares the side wall with the trench 6 is formed. In the following, a region of the convex portion where the semiconductor element is formed will be referred to as an actual diffusion pattern 8
Will be called. This real diffusion pattern 8 is STI (Sh
It is electrically isolated from the surroundings by an insulating film 7 formed in the trench 6 called “allow trench isolation”. In addition, a region of the protrusion that is not formed for the purpose of forming a semiconductor element will be referred to as a diffusion dummy pattern 9 below.

Here, in order to explain the diffusion dummy pattern 9, a cross section of each main region of a semiconductor device having no diffusion dummy pattern and a semiconductor device having a diffusion dummy pattern in FIGS. 3A and 3B, respectively. The figure is shown.

In the semiconductor device in which the region where the semiconductor element is formed is surrounded by the insulating film 7 formed in the trench to electrically isolate the surrounding region from the surrounding region, as shown in FIG.
When the diffusion dummy pattern 9 is not formed as shown in (a), a region having a high density of convex portions and a region having a low density of convex portions are formed on the surface layer of the second semiconductor layer. Therefore, when the insulating film 7 is formed on the trench 6 so as to fill the inside of the trench 6 and the insulating film 7 is flattened by CMP, the polishing rate of the sparse region and the dense region is reduced. Due to the difference, excessive polishing occurs in the sparse region.

Therefore, in order to prevent this, FIG.
As shown in, the diffusion dummy pattern is formed in the sparse region so as to reduce the density of the protrusions on the surface layer of the semiconductor.

Then, in FIG. 2, an interlayer insulating film 10 is formed on the actual diffusion pattern 8 and the diffusion dummy pattern 9. Further, an actual wiring pattern 1 and a wiring dummy pattern 2 are formed on it.

The wiring dummy patterns 2a and 2b in FIG. 1 overlap the diffusion dummy pattern 9 as shown in FIG. 2, and the wiring dummy patterns 2a and 2b are the interlayer insulating film 1.
It is electrically connected to the diffusion dummy pattern through the through hole 11 formed in 0. Further, here, the second semiconductor layer 5 forming the diffusion dummy pattern 9 is
It has the same conductivity type as that of the P-type well layer 4a therebelow. Although not shown, the P-type well layer 4a has the same conductivity type as that of the semiconductor substrate which is set to the ground potential, so that the wiring dummy pattern 2 is fixed to the substrate (ground) potential.

The wiring dummy pattern 2c in FIG.
Since it is connected to the ground line 1b, the Grand
It is fixed at (ground) potential.

In this way, the wiring dummy patterns 2a and 2b are formed.
Since the potential is fixed by being connected to the diffusion dummy pattern 9, the parasitic capacitance between the wiring dummy pattern and the actual wiring pattern becomes uniform in any region. Also, the wiring dummy pattern 2c is connected to the ground line 1b without being electrically isolated, so that the parasitic capacitance becomes constant. This suppresses an increase in parasitic capacitance and operation instability, and enables LSI design calculation.

Next, FIGS. 4 to 8 show wiring layout diagrams in respective steps when designing a wiring layout on the semiconductor device of FIG. The wiring layout method will be described below with reference to these drawings.

First, in the process shown in FIG. 4, one set of wiring dummy patterns 20 of the same shape is exactly overlapped on the substantially rectangular diffusion dummy pattern 9,
The wiring dummy patterns 20 and the diffusion dummy patterns 9 are arranged so as to be spread over the entire semiconductor device at regular intervals such that they do not come into contact with the adjacent set. However, in FIG. 4, the wiring dummy pattern 20 and the diffusion dummy pattern 9 are shifted for convenience so that they can be distinguished. Since these are connected through the through hole 11 in a later step, it is sufficient that at least a region corresponding to the area of the through hole 11 is overlapped, and it is not necessary that they are exactly overlapped.

At this time, both dummy patterns 20,
The shapes of 9 are substantially rectangular, but other shapes may be used. Further, it is easiest to make both dummy patterns 20 and 9 have the same shape, but if necessary, they may have different shapes.

Next, in the process shown in FIG. 5, the actual diffusion pattern 8 is arranged. At this time, among the diffusion dummy patterns 9 arranged in FIG. 4, those which overlap the position of the actual diffusion pattern 8 are not arranged. In FIG. 5, for convenience,
Only the actual diffusion pattern 8 and the diffusion dummy pattern 9 are shown.

On the other hand, in the process shown in FIG. 6, the signal line 1a and the ground line 1b are arranged. At this time, the signal lines 1a, G among the wiring dummy patterns 20 arranged in FIG.
Nothing overlapping the position of the land line 1b is arranged. Note that, in FIG. 6 as well, the actual wiring pattern 1
And only the actual wiring dummy pattern 20 are shown.

In the process shown in FIG. 7, the wiring dummy pattern 2a of the wiring dummy pattern 20 on which the diffusion dummy pattern 9 is located is connected to the diffusion dummy pattern 9 through the through hole 11. .

Next, in the process shown in FIG. 8, one of the wiring dummy patterns 20 in which the diffusion dummy pattern 9 is not located on the lower side or the presence of the polysilicon wiring is connected to the diffusion dummy pattern 9 through the through hole 11. Among the wiring dummy patterns adjacent to each other, the wiring dummy pattern 2b is formed by connecting to the wiring dummy pattern 2a on which the diffusion dummy pattern 9 is located below. At this time, the wiring dummy pattern 2
b has a configuration including a wiring dummy pattern 2a connected to the diffusion dummy pattern 9. As a result, even the wiring dummy pattern in which the diffusion dummy pattern 9 is not located on the lower side can be fixed to the substrate potential.

In FIG. 8, the wiring dummy pattern 2b is used.
Is configured to include a plurality of wiring dummy patterns 2a, but it is sufficient to include at least one wiring dummy pattern 2a. Further, although the wiring dummy pattern 2b is one, it may be formed in a shape divided into a plurality of pieces. In this case, each wiring dummy pattern 2b may include at least one wiring dummy pattern 2a.

When the wiring dummy pattern 20 cannot be connected to the substrate potential even in the process of FIGS.
Of the wiring dummy patterns 20, the diffusion dummy pattern 9 is not located on the lower side, and the wiring dummy pattern 2 is surrounded by the actual wiring pattern 1 and cannot be connected to the adjacent wiring dummy pattern 2a, or is connected to the adjacent wiring dummy pattern. If it is impossible to connect with the diffusion dummy pattern 9, the following two methods are used.

In the first method, if the wiring dummy pattern 2c is surrounded by the ground line 1b like the wiring dummy pattern 2c shown in FIG. 8, the wiring dummy pattern 2c is grounded.
Connect to line 1b. In this way, the wiring dummy pattern 2c is fixed to the ground (ground) potential. In addition,
Even if the wiring dummy pattern 2c is surrounded by the power supply line, the wiring dummy pattern 2c may be connected to the power supply line.

In the second method, when it is impossible to fix to any potential due to the influence on the parasitic capacitance such as when surrounded by the signal line 1a, this method is used. The wiring dummy pattern 2d is not arranged. In this case, since it is surrounded by the actual wiring pattern 1, it is assumed that the wiring density in this region is high.
Even if the wiring dummy pattern 2d is not arranged, there are few problems in the process.

However, if the wiring dummy pattern 2d is not arranged and the wiring density in this region is likely to decrease, the wiring dummy pattern 2d may be formed without being fixed to any potential. In such a case, it is rare, and even if it exists, the formed region is considered to be very small, so that it is considered that the parasitic capacitance is not significantly affected.

By the above method, finally, as shown in FIG. 1, the necessary actual wiring is arranged on the semiconductor device, and the wiring dummy pattern having the fixed potential is arranged in the region where the actual wiring is not arranged. A layout pattern can be obtained.

As a result, since the actual wiring pattern and the wiring dummy pattern having a fixed potential can be formed on the surface of the semiconductor layer, the density of the wiring on the surface of the semiconductor layer can be eliminated. Further, it is possible to suppress a drastic decrease in circuit operation and unstable operation. In addition, the LSI design can be calculated.

This method uses the diffusion dummy pattern 9 formed conventionally, and also forms the through hole 11 for connecting the diffusion dummy pattern 9 and the wiring dummy patterns 2a and 2b. However, since this can be formed at the same time as the contact hole provided for connecting the actual wiring pattern 1 and the element portion, it is necessary to add a step other than the step of forming the wiring dummy patterns 2a, 2b, 2c. There is no. Further, the manufacturing process does not become complicated. That is, the semiconductor device can be manufactured in the existing manufacturing process only by considering the data processing in the layout design.

Further, according to this method, when the potential of the wiring dummy pattern 2 is fixed, another wiring layer is not required, and the wiring dummy pattern 2 whose potential is fixed can be laid out as a single layer. Therefore, the layout of other layers is not restricted without depending on the multilayer structure.

Further, even if the wiring dummy pattern 2 is arranged in the loop-shaped actual wiring pattern, the wiring dummy pattern 2 is fixed to the potential by connecting to the diffusion dummy pattern 9 located under the wiring dummy pattern 2. can do. This makes it possible to reduce the number of wiring dummy patterns that are not fixed to any potential, as compared with the conventional method of fixing the potential of the wiring dummy patterns. Since the area density is high in the small loop-shaped actual wiring pattern, the wiring dummy pattern 2 may be deleted.

Further, in the layout design at this time, for example, by combining with the data processing for creating a photomask, the judgment processing such as "if it exists" or "if it does not exist" is a simple AND / OR logic. Can be replaced. From this, the design rule of the wiring dummy pattern is not complicated, so that a special tool such as a pattern detection program is unnecessary, and the wiring dummy pattern whose potential is fixed can be designed by a general-purpose layout design tool. .

Further, the wiring dummy pattern 1 can be arranged in a necessary area with almost no influence on the layout of the actual wiring pattern 1. Therefore, when using a conventional real wiring layout, it often does not need to be modified. Further, even when a new actual wiring layout is designed, there are few restrictions on the layout, so the degree of freedom in design is high.

(Second Embodiment) In the first embodiment, the wiring dummy pattern 2 is fixed to the substrate potential. However, if necessary, it is fixed to the power supply potential or a potential that reduces the influence of the wiring capacitance. Is also good.

FIG. 9 is a sectional view of a semiconductor device having a wiring dummy pattern whose potential is fixed in addition to the substrate potential. For example, when the first semiconductor layer 4 on the lower side of the wiring dummy pattern 2e is the N-type well layer 4b and the N-type well layer 4b has the power supply potential as in the right part of FIG. By setting the conductivity type of the second semiconductor layer 5 forming the diffusion dummy pattern 9 to be the same N type as the N type well layer 4b, the wiring dummy pattern 2e connected to the diffusion dummy pattern 9 is set to the power supply potential. Can be fixed.

(Other Embodiments) Further, like the wiring dummy pattern 2f near the center of FIG. 9, the wiring dummy pattern is connected to the actual diffusion pattern 8 by the actual wiring pattern 1.
You may connect with. In this case, the wiring dummy pattern 2
The second semiconductor layer 5 forming the diffusion dummy pattern 9 on the lower side of f is formed to have the conductivity type opposite to that of the P-type well layer 4a. Alternatively, the contact hole may not be provided below the wiring dummy pattern 2f. In any case, the wiring dummy pattern 2f is fixed to the potential of the area of the actual diffusion pattern 8 Even in the same semiconductor device, the wiring dummy patterns fixed to a plurality of different potentials are laid out. It is also possible.

In the case of the multilayer wiring, the wiring layout may be designed by replacing the diffusion dummy pattern 9 in FIGS. 6 to 8 with the wiring dummy pattern in the lower layer. For example, first, the wiring layout created in the above-described embodiment is set as the first layer, and the actual wiring pattern 1 and the wiring dummy pattern 20 are created as shown in FIG. 8 in the wiring layout of the second layer thereon. Then, as shown in FIG. 7, the wiring dummy pattern 2a at a position overlapping the wiring dummy pattern of the first layer is connected to the wiring dummy pattern of the first layer through the via hole (through hole 11).

Further, as shown in FIG. 8, the wiring dummy pattern 20 is formed so as to include the wiring dummy pattern 2a for connecting the wiring dummy pattern 20 in which the wiring dummy pattern of the first layer is not located on the lower side to the wiring dummy pattern of the first layer. A pattern 2b is formed and electrically connected to the wiring dummy pattern of the first layer. Furthermore, among the electrically isolated wiring dummy patterns, those that can be connected to the actual wiring pattern of the substrate line or the power supply line are connected, and those that cannot be connected are not placed at that location or remain electrically isolated. To place.

By such a method, it is possible to design the layout of the wiring dummy pattern having a fixed potential even in a multilayer. Even with such a multilayer structure, there are few restrictions on the layout of other layers.

[Brief description of drawings]

FIG. 1 is a diagram showing a wiring layout pattern when a region of a semiconductor device formed by applying a first embodiment of the present invention is viewed from above a semiconductor substrate.

2 is a cross-sectional view of a portion of the semiconductor device of FIG.

FIG. 3 is a sectional view of a main part of a semiconductor device for explaining a diffusion dummy pattern.

FIG. 4 is a diagram showing a design process of the wiring layout of FIG.

FIG. 5 is a diagram showing a wiring layout design process following FIG. 4;

FIG. 6 is a diagram showing a wiring layout design process following FIG. 5;

FIG. 7 is a diagram showing a wiring layout design process following FIG. 6;

FIG. 8 is a diagram showing a wiring layout design process following FIG. 7;

FIG. 9 is a partial cross-sectional view of a semiconductor device formed by applying the second embodiment and other embodiments.

[Explanation of symbols]

1 ... Actual wiring pattern, 2 ... Wiring dummy pattern, 3 ... Semiconductor substrate, 4 ... First semiconductor layer, 5 ... Second semiconductor layer, 6 ...
Trench, 7 ... Insulating film, 8 ... Actual diffusion pattern, 9 ... Diffusion dummy pattern, 10 ... Interlayer insulating film, 11 ... Through hole.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yasushi Tanaka             1-1, Showa-cho, Kariya city, Aichi stock market             Inside the company DENSO F term (reference) 5F033 KK01 QQ09 QQ37 UU01 VV02                       XX01 XX02 XX23                 5F038 CA18 CD02 CD05 CD10 CD13                       EZ20                 5F064 DD13 DD14 DD24 DD50 EE14                       EE15 EE17 EE22 EE43 EE60

Claims (4)

[Claims] 1. A semiconductor layer (4, 4) on a semiconductor substrate (3).
Among the plurality of trenches (6) formed in the surface layer portion of 5), the insulating film (7) formed in the plurality of trenches, and the plurality of convex portions of the semiconductor layer formed by the trench, the semiconductor An actual diffusion pattern (8) formed in an element formation region, a diffusion dummy pattern (9) formed in a semiconductor element non-formation region, an interlayer insulating film (10) formed on the semiconductor layer, A method for manufacturing a semiconductor device having an actual wiring pattern (1) and a wiring dummy pattern (2) formed on the interlayer insulating film, the semiconductor substrate (3 having the semiconductor layers (4, 5). )
A step of forming an actual diffusion pattern (8) and a diffusion dummy pattern (9) by forming the plurality of trenches (6) in a surface layer portion of the semiconductor layer, and The interlayer insulating film (10) is formed on
Forming a plurality of through holes (11) in the interlayer insulating film, arranging the actual wiring pattern on the interlayer insulating film so as to overlap the actual diffusion pattern, and through the through holes. Electrically connecting to the actual diffusion pattern, arranging the wiring dummy pattern so as to overlap the diffusion dummy pattern, and electrically connecting to the diffusion dummy pattern through the through hole. A method of manufacturing a semiconductor device, comprising: 2. In the step of forming the wiring dummy pattern (2), a plurality of the wiring dummy patterns are formed, and at least one of the wiring dummy patterns is formed so as to overlap the plurality of diffusion dummy patterns. ,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring dummy pattern is electrically connected to the plurality of diffusion dummy patterns. 3. A semiconductor device having an actual wiring pattern (1) and a wiring dummy pattern (2), the semiconductor layer (4, 5) formed on a semiconductor substrate (3).
A plurality of trenches (6) formed in the surface layer portion of the semiconductor layer and an insulating film (7) formed in the plurality of trenches; and a convex portion surrounded by the plurality of trenches in the surface layer portion. Among these, the actual diffusion pattern (8) formed in the semiconductor element forming region of the semiconductor layer, the diffusion dummy pattern (9) formed in the semiconductor element non-forming region, and the actual diffusion pattern (8) formed on the semiconductor layer. An interlayer insulating film (10) and a plurality of through holes (1
1) and an actual wiring pattern (1) and a wiring dummy pattern (2) having a predetermined shape formed on the interlayer film, wherein the actual wiring pattern overlaps the actual diffusion pattern, The wiring dummy pattern is electrically connected to the actual diffusion pattern via a through hole, and the wiring dummy pattern overlaps the diffusion dummy pattern, and is electrically connected to the diffusion dummy pattern via the through hole. A semiconductor device which is connected. 4. A plurality of the wiring dummy patterns (2) are formed, and at least one of the wiring dummy patterns is formed to overlap a plurality of the diffusion dummy patterns, and the wiring dummy patterns are formed in the plurality of the wiring dummy patterns. The semiconductor device according to claim 3, wherein the semiconductor device is electrically connected to the diffusion dummy pattern.