JPH1126576A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a malfunction of a circuit by electrically connecting an exposed semiconductor substrate and a dummy electrode made by patterning the conductive material, on an insulating film and in a contact hole. SOLUTION: A silicon oxide film 4 is formed on the surface of a semiconductor substrate 1 and then resist is applied onto the surface of the silicon oxide film 4. With the resist as a mask, the silicon oxide film 4 is etched and thereby a contact hole 31 is formed. After that, polycrystalline silicon films 12a, 21b are formed on the entire surface. On these polycrystalline silicon films 12a, 12b, a high melting point metal film 5 is deposited and then the polycrystalline silicon films 12a, 12b and the high melting point metal film 5, which are used as conductive materials, are patterned to form dummy electrodes 12a, 12b, 5. These dummy electrodes 12a, 12b, 5 are electrically connected to the semiconductor substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a device having a dummy pattern formed thereon and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 8 shows a plurality of circuit forming regions 10 in which circuit blocks in one semiconductor chip 100 are formed.
1 and a circuit isolation region 102 existing around the circuit isolation region and isolating each circuit formation region. Circuit formation area 10
In No. 1, unevenness occurs in the interlayer insulating film deposited on the upper surface due to the presence of steps such as a gate electrode and two or more wiring layers constituting a circuit. Therefore, the circuit isolation region 102
When an interlayer insulating film is deposited without forming an electrode, a wiring, or the like, a difference occurs in the height of the interlayer insulating film with respect to the circuit formation region 101. Therefore, a dummy pattern including a dummy element region, a dummy electrode, and a dummy wiring layer is also formed in the circuit isolation region 102, and an interlayer insulating film is deposited thereon.

FIG. 9 shows a vertical sectional structure of a dummy pattern in a conventional circuit isolation region 102. A P well 11b is formed on the surface of the semiconductor substrate 1, and the P well 11b is formed.
Are separated by trench grooves 3. A silicon oxide film 4 formed by a thermal oxidation method is formed on the surface of the dummy element region, and a dummy gate electrode is formed thereon. The dummy gate electrode is
It comprises a polycrystalline silicon film 12 and a high melting point metal film 5 such as tungsten.

A first interlayer insulating film 6 is deposited so as to cover the dummy element region and the entire surface of the trench 3. At the time when the interlayer insulating film 6 is deposited, there is a step on the surface due to the presence of the dummy gate electrode.
It is planarized by mechanical polishing. A first-layer dummy wiring layer 7 is formed on the surface of interlayer insulating film 6, and a second-layer interlayer insulating film 8 is formed so as to cover the entire surface.
Is deposited. After the interlayer insulating film 8 is planarized by CMP, a second-layer dummy wiring layer 9 is formed. Further, the third interlayer insulating film 10 is formed so as to cover the entire surface.
Is deposited, and the surface thereof is planarized by CMP.

[0005]

However, in the conventional semiconductor device and the method of manufacturing the same, there is a problem that the provision of the dummy pattern increases the stray capacitance. As is clear from FIG. 9, a silicon oxide film 4 is formed between the dummy gate electrode composed of the polycrystalline silicon film 12 and the refractory metal film 5a and the semiconductor substrate 1 to be insulated. Therefore, a stray capacitance has been generated between the dummy gate electrode and the semiconductor substrate 1. Further, a stray capacitance also occurs between the dummy gate electrode and the dummy wiring layer 7 and between the dummy wiring layer 7 and the dummy wiring layer 9.

For this reason, according to the conventional semiconductor device and the method for manufacturing the same, a malfunction may occur in the circuit due to the stray capacitance generated by the dummy pattern.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a semiconductor device and a method of manufacturing the same capable of preventing a circuit from malfunctioning due to a stray capacitance caused by a dummy pattern formed for planarization. The purpose is to provide.

[0008]

A method of manufacturing a semiconductor device according to the present invention is a method of forming a dummy pattern in a region where a circuit is not formed on a semiconductor substrate, wherein an insulating film is formed on a surface of the semiconductor substrate. Forming a contact hole in the insulating film to expose the surface of the semiconductor substrate; and depositing a conductive material on the insulating film and on the surface of the semiconductor substrate exposed in the contact hole. And patterning the conductive material to form the dummy electrode, wherein the dummy electrode and the semiconductor substrate are electrically connected. Here, the conductive material forming the dummy electrode must have a step of implanting impurity ions of the same conductivity type as the substrate.

With this configuration, the generation of stray capacitance between the dummy electrode and the semiconductor substrate is prevented.

The manufacturing method of the present invention further comprises the steps of: depositing an interlayer insulating film on the surfaces of the dummy electrode and the insulating film and planarizing the surface; and forming a contact hole in the interlayer insulating film; Exposing the surface of the dummy electrode;
Filling the contact hole with a conductive material, and patterning by depositing a wiring material on the surface of the interlayer insulating film and the conductive material filling the contact hole,
Forming a dummy wiring layer. In this case, the dummy electrode is electrically connected to the semiconductor substrate, and the dummy electrode and the dummy wiring layer are electrically connected. As a result, the semiconductor substrate is electrically connected to the dummy electrode, and the dummy electrode and the dummy wiring layer are electrically connected to each other, and generation of stray capacitance between these conductive layers is prevented.

According to another manufacturing method of the present invention, the wiring layer has the first structure,
The second dummy wiring layer has a multi-layer structure, in which a dummy electrode and a semiconductor substrate are electrically connected in a contact region, and a conductive material filling a first contact hole formed in a first interlayer insulating film. The dummy electrode and the first dummy wiring layer are electrically connected by a material, and the first dummy wiring layer and the second dummy wiring layer are formed by a conductive material filling a second contact hole formed in the second interlayer insulating film. Is electrically connected to the dummy wiring layer.

Alternatively, another manufacturing method of the present invention comprises a step of forming an insulating film on the surface of the semiconductor substrate, and a step of depositing a first interlayer insulating film on the surface of the insulating film to planarize the surface. Forming a first contact hole in the insulating film and the first interlayer insulating film at the same time to expose a surface of the semiconductor substrate; and filling the first contact hole with a conductive material. Forming a wiring material on a surface of a conductive material filling the first interlayer insulating film and the first contact hole, and patterning the wiring material;
Forming a dummy wiring layer, depositing a second interlayer insulating film on the surface of the first interlayer insulating film and the surface of the first dummy wiring layer, and planarizing the surface; Forming a second contact hole in the interlayer insulating film or the insulating film and the first interlayer insulating film and the second interlayer insulating film;
Exposing at least one of the surface of the first dummy wiring layer and the surface of the semiconductor substrate; and filling the second contact hole with a conductive material;
Forming a second dummy wiring layer by depositing a wiring material on a surface of a conductive material filling the second interlayer insulating film and the third contact hole and patterning the wiring material, thereby forming a second dummy wiring layer. And at least one set of the semiconductor substrate and the first dummy wiring layer, the semiconductor substrate and the first dummy wiring layer and the second dummy wiring layer, or the semiconductor substrate and the second dummy wiring layer. It is characterized by being electrically connected.

In this case, any one set of a semiconductor substrate and a first dummy wiring layer, a first dummy wiring layer and a second dummy wiring layer, or one set between the semiconductor substrate and the second dummy wiring layer. The generation of stray capacitance between them is prevented.

In addition, a dummy element forming region in which the first contact hole is opened in the insulating film is separated by a trench formed in the semiconductor substrate, and the dummy element forming region is formed in the semiconductor substrate. On the surface, they may be arranged in a lattice, staggered lattice, or randomly.

A semiconductor device according to the present invention is a device in which a dummy pattern is formed in a region of a semiconductor substrate where a circuit is not formed, and is formed on a surface of the semiconductor substrate and has a first contact hole. A film, and a dummy electrode formed of a conductive material of the same conductivity type as the substrate on the surface of the semiconductor substrate exposed in the first contact hole, wherein the dummy electrode and the semiconductor substrate are electrically connected to each other. It is characterized by being connected.

In another semiconductor device according to the present invention, an insulating material is further formed on the surface of the dummy electrode and the insulating film, and a second contact hole is opened so that the surface of the dummy electrode is exposed. An interlayer insulating film, a conductive material filling the second contact hole of the interlayer insulating film, and a wiring material formed on a surface of the conductive material filling the interlayer insulating film and the second contact hole. Wherein the dummy electrode and the semiconductor substrate are electrically connected, and the dummy electrode and the dummy wiring layer are electrically connected.

In another semiconductor device according to the present invention, a dummy wiring layer is formed as first and second dummy wiring layers, and the dummy electrode is electrically connected to the semiconductor substrate. And the first dummy wiring layer is electrically connected, and the first dummy wiring layer and the second dummy wiring layer are electrically connected.

Still another semiconductor device according to the present invention is an insulating film formed on a surface of a semiconductor substrate and having a first contact hole formed therein, and an insulating film exposed in the insulating film and the first contact hole. A first interlayer insulating film formed on a surface of a semiconductor substrate, wherein a second contact hole is opened in the first contact hole, and a first interlayer insulating film which fills the first contact hole and the second contact hole. A first conductive material and a wiring material formed on a surface of the first interlayer insulating film, or on a surface of the first conductive material filling the first interlayer insulating film and the second contact hole; The first dummy wiring layer,
The surface of the first dummy wiring layer and / or the surface of the conductive material filling the second contact hole is formed of an insulating material on the surfaces of the dummy wiring layer and the first interlayer insulating film. A second interlayer insulating film in which a third contact hole is formed, a second conductive material filling the third contact hole in the second interlayer insulating film, and the second interlayer insulating film. A film and a second dummy wiring layer formed of a wiring material on a surface of a second conductive material filling the third contact hole, wherein the semiconductor substrate and the first dummy wiring layer, or At least one set of a semiconductor substrate and the first dummy wiring layer and the second dummy wiring layer, or at least one set of the semiconductor substrate and the second dummy wiring layer is electrically connected.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a vertical sectional structure of a semiconductor device according to a first embodiment of the present invention and a method of manufacturing the same in each step. The following steps are performed for the semiconductor chip 10 shown in FIG.
0, a method of forming a dummy pattern in the circuit isolation region 102 where no circuit block is formed,
The formation of the dummy pattern is performed in the same step as the formation of the element in the circuit block 101 and by the same method.

First, as shown in FIG. 1A, on the surface of a semiconductor substrate 1, a dummy element region is
A trench 3 having a depth of about 0.5 μm is formed by performing reactive ion etching. A TEOS ozone film is deposited on the entire surface by using a chemical vapor method (hereinafter, referred to as a CVD method), and the surface is flattened by CMP to fill the inside of the trench 3.

As shown in FIG. 1B, about 90 degrees Celsius
Thermal oxidation is performed at 0 ° to form a silicon oxide film 4 having a thickness of about 100 Å on the surface of the semiconductor substrate 1.
N-type impurity ions are selectively implanted into the surface portion of the semiconductor substrate 1 to form an N-well 11a, and P-type impurity ions are selectively implanted to form a P-well 11b.

A resist is applied to the surface of the silicon oxide film 4 to form a resist film in which a contact hole for making an electrical connection between the dummy electrode and the semiconductor substrate 1 is formed. As shown in c), the silicon oxide film 4 is etched to form a contact hole 31. A polycrystalline silicon film 12 is deposited on the entire surface by a CVD method. As shown in FIG. 1D, a resist film 13 is formed on the surface of the polycrystalline silicon film 12 by opening a region where the P well 11b is formed. Using this resist film 13 as a mask, for example, boron as a P-type impurity is selectively ion-implanted into the polycrystalline silicon film 12 to form a polycrystalline silicon film 12b. As shown in FIG. 1E, the resist film 13 is removed, and a resist film 14 is formed by opening a region in which an N well is formed. Ions are implanted to form a polycrystalline silicon film 12a. Therefore, the dummy electrode and the semiconductor substrate become ohmic.

In this ion implantation step, in the circuit block shown in FIG. 8, P-type impurity ions are formed in the polycrystalline silicon film formed on the N-well, and N-type impurity ions are formed in the polycrystalline silicon film formed on the P-well. It can be performed simultaneously with the step of implanting ions.

On the surfaces of the polycrystalline silicon films 12a and 12b, a refractory metal film 5 such as tungsten is deposited to a thickness of about 1000 to 2000 angstroms by a sputtering method. A resist film is formed by opening a portion other than a region where a dummy electrode is to be formed, and this is used as a mask to form a polycrystalline silicon film 1 as shown in FIG.
The dummy electrodes 12a, 12b, and 5 are formed by patterning the 2a and 12b and the refractory metal film 5. Thus, the semiconductor substrate 1 on which the P well 11b is formed is electrically connected to the polycrystalline silicon film 12b into which the P-type impurity is introduced, and the semiconductor substrate 1 on which the N well 11a is formed.
And polycrystalline silicon film 12a into which the N-type impurity is introduced is electrically connected.

As shown in FIG. 1 (g), a silicon oxide film is deposited to a thickness of about 500 angstroms on the entire surface by the CVD method, and further, for example, BPSG (boron, phosphorus, SiO ₂ , glass) 1) A first interlayer insulating film 6 composed of a film is deposited to a thickness of about 10,000 to 20,000 angstroms and planarized by CMP.

Thereafter, in the first embodiment, a first wiring layer 17 and a second interlayer insulating film 8 connected to elements formed in the circuit block 101 shown in FIG. 8 are formed. Then, the second-layer wiring layer 18 and the third-layer interlayer insulating film 10 connected to the same layer 101 are formed and flattened, thereby flattening the interlayer insulating film 8. Get.

According to the first embodiment, the polycrystalline silicon film 12a constituting the dummy electrode and the N well 11a
Is electrically connected, and similarly, the polycrystalline silicon film 12b forming the dummy electrode and the semiconductor substrate 1 on which the P well 11b is formed are electrically connected. Therefore, the stray capacitance between the electrode and the substrate, which existed in the conventional device shown in FIG. 8, disappears. As a result, it is possible to prevent a malfunction of the circuit which has conventionally occurred due to the stray capacitance.

Next, a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described. The first
In this embodiment, the dummy electrodes are electrically connected to the semiconductor substrate, but in the present embodiment, the dummy electrodes are further connected between the dummy wiring layers and the dummy electrodes, and between the plurality of Tammy wiring layers. There is a feature.

FIG. 1 shows a manufacturing method according to the second embodiment.
(G) is the same as the dummy electrodes 12a, 5 or 12b and 5 in the first embodiment up to the step of forming the first interlayer insulating film 6. Thereafter, in the second embodiment, as shown in FIG. 1H, the contact hole 15 is opened so that the surface of the refractory metal film 5 constituting the dummy electrode in the interlayer insulating film 6 is exposed. Make a hole. The entire surface of the interlayer insulating film 6 and the contact hole 1
A high melting point metal such as tungsten is deposited by a CVD method so as to fill the inside of the contact hole 5, and the contact hole 15 is filled by performing an etch back. Alternatively, a high melting point metal such as tungsten is selectively grown and filled only in the contact hole 15 by the CVD method.

As shown in FIG. 1I, aluminum is deposited by sputtering to a thickness of about 4000 angstroms. A resist film is formed by applying a resist to form a wiring pattern, and the aluminum film is subjected to reactive ion etching using the resist film as a mask to form a first dummy wiring layer 7 and a wiring layer 17. As a result, the dummy electrode and the first-layer dummy wiring layer 7 are electrically connected via the refractory metal embedded in the contact hole 15. The patterning of the first dummy wiring layer 7 is performed in the circuit block 1 shown in FIG.
1st wiring layer 1 connected to the element formed at 01
7 is performed in the same step as the patterning. FIG. 1 (i)
When the wiring layer 17 extends over the dummy electrode as shown in FIG. 7, the dummy electrode is not connected to the dummy wiring layer.

Thereafter, an interlayer insulating film 8 made of, for example, TEOS ozone is formed by CVD so as to cover about 1
Deposit to a thickness of 20,000 to 20,000 angstroms, and flatten the surface by CMP.

As in the step of forming the contact hole 15 and the first dummy wiring layer 7 shown in FIGS. 1H and 1I, the contact hole 16 and the second dummy wiring layer are formed. And are formed. As shown in FIG. 1 (j),
A contact hole 16 is formed in the interlayer insulating film 8 so that the surface of the first dummy wiring layer 7 is exposed. A high melting point metal such as tungsten is deposited by a CVD method so as to fill the entire surface of the interlayer insulating film 8 and the inside of the contact hole 16, and then etched back to form the contact hole 1.
Fill in 6. Alternatively, a high melting point metal such as tungsten is selectively grown and filled only in the contact hole 16 by the CVD method.

As shown in FIG. 1 (k), aluminum is deposited to a thickness of about 8000 angstroms by sputtering and patterned by reactive ion etching to form a second dummy wiring layer 9. As a result, the second-layer dummy wiring layer 9 and the first-layer dummy wiring layer 7 are electrically connected via the refractory metal embedded in the contact hole 16. The patterning of the second dummy wiring layer 9 is performed in the same step as the patterning of the second wiring layer 18 connected to the elements formed in the circuit block 101 shown in FIG. At this time,
Although not shown, when the second wiring layer 18 extends on the first dummy wiring layer 7, the first dummy wiring layer 7 is not connected to the second dummy wiring layer 9. The interlayer insulating film 10 is covered with the CVD method by about 100 to cover the entire surface.
Deposit to a thickness of 00 to 20000 angstroms, and flatten the surface by CMP.

According to the second embodiment, as apparent from FIG. 3 showing the final cross-sectional structure, the semiconductor substrate 1 and the polycrystalline silicon film 12a forming the dummy electrode are formed.
12b, the refractory metal film 5 constituting the dummy electrode and the first dummy wiring layer 7 are connected, and the first dummy wiring layer 7 and the second dummy wiring layer are further connected. 9
Is connected, almost all of the stray capacitance generated conventionally between these conductive layers disappears. This makes it possible to prevent a malfunction of the circuit.

In the second embodiment, the second dummy wiring layer 9 is connected to the semiconductor substrate 1 via the first dummy wiring layer 7, the dummy electrodes 12a (12b) and 5 in this order. doing. However, there are various forms of connection between the semiconductor substrate and the second wiring layer. As shown in FIG. 4, the surface of the semiconductor substrate 1 exposed in the contact region 31 and the first dummy wiring layer 7 in the contact region 31 are connected to the high melting point embedded in the contact hole 15 without the dummy electrode therebetween. The first dummy wiring layer 7 and the second dummy wiring layer 9 may be connected by the metal film 15 and the refractory metal film 16 embedded in the contact hole 16. Alternatively, as shown in FIG. 5, the semiconductor substrate 1 and the second-layer dummy wiring layer 9 are embedded in the dummy electrodes and the contact holes 13 without the intervention of the first-layer dummy wiring layer 7. Alternatively, they may be directly connected via a high-melting-point metal.

Next, FIGS. 6 and 7 show the dummy element region 32 surrounded by the dummy element isolation region 3, the dummy electrodes 12a (12b) and 5 in the dummy element region 32, and the dummy electrode or dummy wiring. An example of the arrangement of a contact region 31 with the semiconductor substrate 1 is shown. As shown in FIG. 6, the dummy element regions 32 may be arranged in a matrix, may be arranged in a staggered pattern as shown in FIG. 7, or may be arranged randomly. To more evenly flatten the surfaces of the interlayer insulating films 6, 8, and 10 in the circuit isolation region 102, the staggered arrangement shown in FIG. 7 is desirable.

The above-described embodiment is merely an example and does not limit the present invention. For example, in FIGS. 1 and 2, a dummy pattern is formed on the semiconductor substrate 1 on which the P well 11a and the N well 11b are formed. However, the present invention can be applied to a case where a dummy pattern is formed on a semiconductor substrate on which only one conductivity type well is formed, or a case where a dummy pattern is formed on a semiconductor substrate on which no well is formed. is there. Although a P-type semiconductor substrate is used in the above embodiment, the present invention may be applied to an N-type semiconductor substrate. Further, the material of the dummy electrode, the wiring layer, and the like is not limited to the materials described in the embodiment, and any other material may be used as long as it is conductive with the semiconductor substrate.

[0039]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, at least one of the dummy electrode and the dummy wiring layer is electrically connected to the semiconductor substrate. In the meantime, it is possible to prevent the stray capacitance that has been conventionally generated from disappearing, thereby preventing a malfunction from occurring in the circuit.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a method of manufacturing a semiconductor device according to first and second embodiments of the present invention for each process.

FIG. 2 is a longitudinal sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a longitudinal sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a longitudinal sectional view showing an application example of the semiconductor device according to the second embodiment.

FIG. 5 is a longitudinal sectional view showing another application example of the semiconductor device according to the second embodiment.

FIG. 6 is a plan view showing an arrangement of dummy patterns of the semiconductor device according to the first or second embodiment of the present invention.

FIG. 7 is a plan view showing another arrangement of the dummy patterns of the semiconductor device according to the first or second embodiment of the present invention;

FIG. 8 is a plan view showing a circuit formation region and a region separating the circuit formation region in the semiconductor chip.

FIG. 9 is a longitudinal sectional view showing a structure of a semiconductor device in which a conventional dummy pattern is formed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 3 Trench groove 4 Silicon oxide film 5 Refractory metal film 6, 8, 10 Interlayer insulating film 7, 9 Dummy wiring layer 17, 18 Wiring layer 11a N well 11b P well 12, 12a, 12b Polycrystalline silicon film 13 , 15, 16, 31 Contact hole 32 Dummy element region

Claims (12)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a dummy pattern is formed in a region where a circuit is not formed on a semiconductor substrate, a step of forming an insulating film on a surface of the semiconductor substrate, and forming a contact hole in the insulating film. Exposing a surface of the semiconductor substrate, depositing a conductive material on the insulating film and a surface of the semiconductor substrate exposed by the contact hole, and patterning the conductive material to form a conductive material. Forming a dummy electrode, wherein the dummy electrode and the semiconductor substrate are electrically connected. 2. A method of manufacturing a semiconductor device, wherein a dummy pattern is formed in a region of a semiconductor substrate where a circuit is not formed, a step of forming an insulating film on a surface of the semiconductor substrate, and a first contact hole in the insulating film. Exposing a surface of the semiconductor substrate by opening a hole; depositing a conductive film on the insulating film and the surface of the semiconductor substrate exposed by the first contact hole; Forming a dummy electrode by patterning on the surface; depositing an interlayer insulating film on the surface of the dummy electrode and the insulating film to planarize the surface; and forming a second contact hole in the interlayer insulating film. A step of exposing the surface of the dummy electrode; a step of filling the second contact hole with a conductive material; Forming a dummy wiring layer by depositing a wiring material on a surface of a conductive material filling the tact hole and patterning the wiring material, wherein the dummy electrode and the semiconductor substrate are electrically connected, and the dummy A method of manufacturing a semiconductor device, wherein an electrode is electrically connected to the dummy wiring layer. 3. A method of manufacturing a semiconductor device in which a dummy pattern is formed in a region of a semiconductor substrate where a circuit is not formed, a step of forming an insulating film on a surface of the semiconductor substrate, and a first contact hole in the insulating film. Opening a hole to expose the surface of the semiconductor substrate; depositing a conductive material on the insulating film and on a surface of the semiconductor substrate exposed by the first contact hole; Forming the dummy electrode by patterning; depositing a first interlayer insulating film on the surface of the dummy electrode and the insulating film to planarize the surface; Opening a second contact hole to expose a surface of the dummy electrode; filling the second contact hole with a conductive material; Depositing a wiring material on a surface of a conductive material filling the second contact hole and patterning to form a first dummy wiring layer; and forming a first dummy wiring layer on the first interlayer insulating film and the first Depositing a second interlayer insulating film on the surface of the dummy wiring layer and planarizing the surface; and forming a third contact hole in the second interlayer insulating film or the first and second interlayer insulating films. A step of exposing the surface of the first dummy wiring layer or the surface of the dummy electrode; a step of filling the third contact hole with a conductive material; Forming a second dummy wiring layer by depositing a wiring material on the surface of the conductive material filling the third contact hole and patterning the wiring material, and electrically connecting the dummy electrode and the semiconductor substrate to each other. Connection And one set of the dummy electrode, the first dummy wiring layer and the second dummy wiring layer, the dummy electrode and the first wiring layer, and the dummy electrode and the second wiring layer are electrically connected to each other. A method for manufacturing a semiconductor device, comprising: 4. A method of manufacturing a semiconductor device, wherein a dummy pattern is formed in a region of a semiconductor substrate where a circuit is not formed, wherein: a step of forming an insulating film on a surface of the semiconductor substrate; Depositing an interlayer insulating film, and flattening the surface; simultaneously opening a first contact hole in the insulating film and the first interlayer insulating film to expose a surface of the semiconductor substrate; Filling the first contact hole with a conductive material, depositing a wiring material on the surface of the first interlayer insulating film and the conductive material filling the first contact hole, and performing patterning; Forming a dummy wiring layer, and depositing a second interlayer insulating film on a surface of the first interlayer insulating film and the surface of the first dummy wiring layer to planarize the surface; Interlayer insulating film or Open a second contact hole in the insulating film, the first interlayer insulating film, and the second interlayer insulating film, and at least one of a surface of the first dummy wiring layer and a surface of the semiconductor substrate. Exposing one side; filling the second contact hole with a conductive material; depositing a wiring material on the surface of the second interlayer insulating film and the conductive material filling the second contact hole. Forming a second dummy wiring layer by patterning the semiconductor substrate with the semiconductor substrate, the first dummy wiring layer and the second dummy wiring layer, or the semiconductor substrate and the first dummy wiring layer. A method for manufacturing a semiconductor device, wherein at least one set of a wiring layer or the semiconductor substrate and the second dummy wiring layer is electrically connected. 5. The semiconductor device according to claim 1, further comprising a step of implanting impurity ions of the same conductivity type as the semiconductor substrate into the conductive material forming the dummy electrode. Semiconductor device manufacturing method. 6. A dummy element forming region in which said first contact hole is opened in said insulating film is separated by a trench formed in said semiconductor substrate, and said dummy element forming region is formed in said semiconductor substrate. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is arranged in a lattice shape, a staggered lattice shape, or at random on a surface. 7. A semiconductor device in which a dummy pattern is formed in a region of a semiconductor substrate where no circuit is formed, an insulating film formed on a surface of the semiconductor substrate and having a first contact hole formed therein; And a dummy electrode formed of a conductive material on the surface of the semiconductor substrate exposed in the contact hole of (a), wherein the dummy electrode and the semiconductor substrate are electrically connected. . 8. A semiconductor device in which a dummy pattern is formed in a region of a semiconductor substrate where no circuit is formed, an insulating film formed on a surface of the semiconductor substrate and having a first contact hole formed therein; A dummy electrode formed of a first conductive material on the surface of the semiconductor substrate exposed at the contact hole, and a surface of the dummy electrode formed of an insulating material on the surfaces of the dummy electrode and the insulating film. An interlayer insulating film in which a second contact hole is opened so that the second insulating film is exposed; a second conductive material filling the second contact hole of the interlayer insulating film; And a dummy wiring layer formed of a wiring material on a surface of a second conductive material filling the contact hole, wherein the dummy electrode is electrically connected to the semiconductor substrate. Is a semiconductor device, characterized in that said dummy electrode and the dummy wiring layer are electrically connected. 9. A semiconductor device in which a dummy pattern is formed in a region of a semiconductor substrate where no circuit is formed, an insulating film formed on a surface of the semiconductor substrate and having a first contact hole formed therein; A dummy electrode formed of a first conductive material on the surface of the semiconductor substrate exposed at the contact hole, and a surface of the dummy electrode formed of an insulating material on the surfaces of the dummy electrode and the insulating film. A first interlayer insulating film in which a second contact hole is opened so that the first contact hole is exposed; a second conductive material that fills the second contact hole in the first interlayer insulating film; A first dummy wiring layer formed of a wiring material on a surface of a second conductive material that fills the second contact hole with the interlayer insulating film of the first dummy wiring layer; A second interlayer insulating film formed of an insulating material on a surface of the first interlayer insulating film and having a third contact hole formed so as to expose a surface of the first dummy wiring layer; A third conductive material that fills the third contact hole of the second interlayer insulating film; and a wiring material on a surface of the third conductive material that fills the second interlayer insulating film and the third contact hole. Wherein the dummy electrode and the semiconductor substrate are electrically connected, the dummy electrode and the first dummy wiring layer are electrically connected, and A semiconductor device, wherein a first dummy wiring layer and the second dummy wiring layer are electrically connected. 10. A semiconductor device in which a dummy pattern is formed in a region of a semiconductor substrate where no circuit is formed, an insulating film formed on a surface of the semiconductor substrate and having a first contact hole formed therein, and the insulating film And a first interlayer insulating film formed on the surface of the semiconductor substrate exposed at the first contact hole and having a second contact hole opened at a portion corresponding to the first contact hole; A first conductive material that fills a first contact hole and the second contact hole, and fills a surface of the first interlayer insulating film or fills the first interlayer insulating film and the second contact hole A first dummy wiring layer formed of a wiring material on a surface of a first conductive material, and a first dummy wiring layer formed on a surface of the first dummy wiring layer and the first interlayer insulating film. A third contact hole formed of an edge material and having a third contact hole formed so as to expose a surface of the first dummy wiring layer and / or a surface of a first conductive material filling the second contact hole. A second conductive material filling the third contact hole of the second interlayer insulating film, a second conductive material filling the third contact hole of the second interlayer insulating film, and a second conductive material filling the third contact hole of the second interlayer insulating film. A second dummy wiring layer formed of a wiring material on a surface of a conductive material, wherein the semiconductor substrate and the first and second dummy wiring layers or the first dummy wiring layer are provided. A wiring layer and the second dummy wiring layer, or the semiconductor substrate and the second dummy wiring layer made of first and second conductive materials;
Wherein at least one of the sets is electrically connected. 11. The semiconductor device according to claim 7, wherein impurity ions of the same conductivity type as the semiconductor substrate are implanted into the dummy electrode. 12. A dummy element forming region in which said first contact hole is opened in said insulating film is separated by a trench formed in said semiconductor substrate, and said dummy element forming region is formed of said semiconductor substrate. The semiconductor device according to any one of claims 7 to 11, wherein the semiconductor device is arranged in a lattice shape, a staggered lattice shape, or randomly on the surface.