JPH06338567A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To keep a plug low in current density so as to lengthen a wiring in service life by a method wherein the major axis of a contact plug or a via contact plug located on a semiconductor board side is set larger than the width of a wiring conductor, and the plug is integrally and continuously formed with the wiring conductor. CONSTITUTION:A lower wiring 3 is laid on a lower interlayer insulating film 2 on a board 1, and a silicon oxide film 4 t in thickness is formed on the lower wiring 3. Then, the silicon oxide film 4 is etched as thick as C after a resist process, and a groove 6 correspondent to the shape of an upper wiring 5 is formed on both the sides of a projection 4a. Furthermore, the residual silicon oxide film 4 and the lower interlayer insulating film 2 are etched after a resist process for the formation of a via contact hole 7. A titanium nitride layer 8 is formed on the silicon oxide film 4, a tungsten layer 9 is formed thereon, and an upper wiring 5 is formed inside the via contact hole 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art Conventionally, on a surface of a semiconductor substrate having an integrated circuit such as an LSI, wiring has a multi-layered structure and an insulating film is interposed between layers, and the wiring is connected to the substrate through a contact hole or a via contact hole formed in this insulating film. Alternatively, the lower layer wiring and the upper layer wiring are connected to each other. When the degree of integration increases and the element becomes finer and the contact hole or via contact hole becomes finer than 1 μm, it is difficult to secure sufficient coverage by conventional Al sputtering. A means for improving the coverage of Al by embedding it with a plug such as W or Al is used.

As one of the concrete methods, for example, a paper "A Quarter-Micron Planarized Interconnection"
Technology With Self-aligned Plug (K.Uno et al, Pr
oceeding IEDM 92, P. 305 to 308, 1992) ", a trench for wiring is formed, a contact hole is formed on the trench by etching, and then a CV is formed in the trench and the contact hole.
It has been reported that a wiring can be obtained by filling tungsten with D once.

[0004]

However, in the method of the above-mentioned paper, since the groove and the etching layer for etching the contact hole are provided in the upper layer of the interlayer insulating film, the groove is formed and then the When the contact hole is formed by etching, the hole diameter can be made equal to the width of the groove. As a result, when the integration of the LSI progresses and the ratio of the height of the wiring to the width of the wiring becomes larger than 1, the current density of the plug becomes higher than that of the wiring, and the life of the plug becomes short. Further, although there is a report regarding the contact between the substrate and the wiring layer, there is no report regarding the contact between the wiring layers, and there is a concern that the formation of the wiring is incomplete.

An object of the present invention is to provide a semiconductor device and a method of manufacturing the same that solve the above problems.

[0006]

The first aspect of the present invention is as follows.
In a semiconductor device in which wiring conductors are laminated in multiple layers on a semiconductor substrate via interlayer insulating films, the major axis of a contact plug or via contact plug located on the semiconductor substrate side with respect to the conductor in the wiring conductor is the wiring conductor. Is larger than the width of the semiconductor device.

A second aspect of the present invention is a semiconductor device having an interlayer insulating film on a wiring conductor layer, wherein the contact plug or the via contact plug is located on the semiconductor substrate side with respect to the contact plug or the via contact plug. The semiconductor device is characterized by being in contact with the upper surface, the side surface, and further the lower surface of the wiring conductor in the wiring conductor layer.

Furthermore, a third aspect of the present invention is a method of manufacturing a semiconductor device, which comprises stacking wiring conductors in multiple layers on a semiconductor substrate with an interlayer insulating film interposed therebetween, wherein a region of the wiring conductor layer is selectively formed. Etching is then performed to selectively open contact holes or via contact holes whose major axis is larger than the width of the wiring conductor and whose depth is deeper than the upper surface of the wiring conductor layer located on the semiconductor substrate side and shallower than the lower surface. A method for manufacturing a semiconductor device is characterized by burying a conductor for use in the semiconductor device.

[0009]

[Operation] According to the present invention, since the current density at the plug can be made approximately the same as that of the wiring conductor layer, the lower layer wiring and the plug can be connected not only on the surface of the lower layer wiring but also on the lower surface, As a result, the lower layer wiring and the upper layer wiring can be connected with a small contact resistance, so that the life of the plug can be extended.

[0010]

Embodiments of the present invention will be described in detail with reference to the process chart of FIG. As shown in FIG. 1A, after a lower layer wiring 3 is formed on the lower layer interlayer insulating film 2 deposited on the substrate 1, a silicon oxide film 4 having a film thickness t is formed on the lower layer wiring 3 by the CVD method. To form a film. The magnitude of the film thickness t corresponds to the sum of the film thickness a corresponding to the upper interlayer insulating film and the film thickness c of the upper wiring,
For example, 16000Å. Then, as shown in FIG. 1 (b), the silicon oxide film 4 is etched by a thickness c through a resist process to form a convex portion 4a having a width d corresponding to the space between wirings of, for example, 8000Å. Corresponding to the shape of the upper layer wiring 5 on both sides, for example, width: 8000Å and depth: 8000Å groove 6
To form. As shown in FIG. 1 (c), the silicon oxide film 4 and the lower interlayer insulating film 2 remaining after the resist process are etched to form a via contact hole 7 having a diameter b of 10000 Å and a depth of 18000 Å, for example. To form.

Here, supplementing the state of contact between the upper and lower wirings and the plug portion, FIG. 2A shows a conventional example, in which the current density of the plug portion 10, the upper layer wiring 5 and the lower layer wiring 3 is Although it is about the same, as LSI integration progresses, as shown in FIG. 2B, the wiring height w with respect to the wiring width w
If the ratio h / w becomes larger than 1, the current density flowing through the plug portion 10 becomes larger than the current density flowing through the wiring, and the reliability of the plug portion 10 is significantly reduced.

Therefore, in FIG. 2 (c), the diameter of the plug portion 10 is made larger than the width of the wiring, and the contact between the lower layer wiring 3 and the plug portion 10 is not only on the upper surface of the lower layer wiring 3, but also on the side surface and the lower surface thereof. Since the increase of the contact resistance can be suppressed by taking the above, it is possible to eliminate the decrease in reliability of the plug portion 10. Further, as shown in FIG. 3, even if the upper portion of the via contact hole 7 is not located directly above the lower layer wiring 3, if the via contact hole 7 is etched near the side wall of the lower layer wiring 3, electrons in the wiring may be lost. The radical molecules of the etchant attract each other and are etched in the direction in which the lower layer wiring 3 exists. As shown in FIG. 1D, a titanium nitride (TiN) layer 8 is formed on the silicon oxide film 4 by a sputtering method, for example, 500 Å, and a tungsten (W) layer 9 is formed thereon by a CVD method, for example, 9000 Å. To a thickness corresponding to the above, and the upper layer wiring 5 is formed including the portion corresponding to the plug in the via contact hole 7.

In this way, the via contact hole 7
It is possible to integrally and continuously form the connection between the lower layer wiring 3 and the upper layer wiring 5 via the. When the contact hole is provided in the lower interlayer insulating film 2 to connect the substrate 1 and the lower wiring 3 to each other, the same process may be performed according to the above steps 1 to 3. In addition, although W is used for the upper wiring 5 in the above-described embodiment, the present invention is not limited to this. For example, an Al alloy such as Al or AlSi or AlCu may be used to form a film by the CVD method. Good.

Further, not only when the wiring has two layers or less,
It goes without saying that the method of the present invention can also be applied to the case of multiple layers. Further, although the silicon oxide film 4 as the interlayer insulating film is deposited on the lower layer wiring 3 in the above-described embodiment, in the case of the substrate provided with the diffusion layer, the insulating film may be directly deposited on the substrate. Good.

[0015]

As described above, according to the present invention,
Since the plug in the contact hole or the via contact hole and the upper wiring are integrally and continuously formed, the following effects can be obtained. In the interlayer insulating film, the hole diameter can be made larger than the width of the groove, so that the current density of the plug portion is not increased and the wiring life can be lengthened. Since the plug in the contact hole or the via contact hole and the lower layer wiring are connected to the upper surface, the side surface, and the lower surface of the lower layer wiring, an increase in contact resistance can be suppressed. Even if the upper part of the contact hole or the via contact hole is not directly above the lower layer wiring, the contact hole or the via contact hole is opened toward the lower layer wiring, which is a self-aligning effect. This allows LS
This is effective when the integration of I progresses and the ratio of the wiring height to the wiring width is large.

[Brief description of drawings]

FIG. 1 is a process drawing showing an example of the present invention.

FIG. 2 is a perspective view showing a wiring structure.

FIG. 3 is a perspective view showing a wiring structure.

[Explanation of symbols]

 1 Substrate 2 Lower Interlayer Insulation Film 3 Lower Wiring (Wiring Conductor Layer) 4 Silicon Oxide Film (Interlayer Insulation Film) 5 Upper Wiring (Wiring Conductor Layer) 6 Groove 7 Via Contact Hole 8 Titanium Nitride Layer 9 Tungsten Layer 10 Plug

Claims (5)

[Claims] 1. A semiconductor device in which wiring conductors are laminated in multiple layers on a semiconductor substrate via inter-layer insulating films, wherein a contact plug or a via contact plug located on the semiconductor substrate side with respect to the conductor in the wiring conductor is provided. A semiconductor device having a major axis larger than a width of the wiring conductor. 2. A semiconductor device having an interlayer insulating film on a wiring conductor layer, wherein the contact plug or the via contact plug is located on the semiconductor substrate side with respect to the contact plug or the via contact plug. A semiconductor device, which is in contact with an upper surface and a side surface of the semiconductor device. 3. The contact plug or the via contact plug is in contact with the upper surface, the side surface and the lower surface of the wiring conductor in the wiring conductor layer located on the semiconductor substrate side with respect to the contact plug or the via contact plug. The semiconductor device according to claim 2. 4. A method of manufacturing a semiconductor device, comprising: forming a plurality of wiring conductors on a semiconductor substrate via interlayer insulating films; selectively etching a region of the wiring conductor layer;
After that, a contact hole or a via contact hole is selectively opened so that its major axis is larger than the width of the wiring conductor and its depth is deeper than the upper surface of the wiring conductor layer located on the semiconductor substrate side and shallower than the lower surface, and a conductor for wiring is formed. A method for manufacturing a semiconductor device, comprising: 5. The depth of the contact hole or the via contact hole is formed deeper than the lower surface of the wiring conductor layer located on the semiconductor substrate side.
A method for manufacturing a semiconductor device as described above.