JPH02271561A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH02271561A JPH02271561A JP9401789A JP9401789A JPH02271561A JP H02271561 A JPH02271561 A JP H02271561A JP 9401789 A JP9401789 A JP 9401789A JP 9401789 A JP9401789 A JP 9401789A JP H02271561 A JPH02271561 A JP H02271561A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- island
- semiconductor device
- metal thin
- internal lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000011347 resin Substances 0.000 claims abstract description 10
- 229920005989 resin Polymers 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 abstract description 5
- 230000008646 thermal stress Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a resin-sealed semiconductor device.
従来の樹脂封止型半導体装置は、第4図(a)。 A conventional resin-sealed semiconductor device is shown in FIG. 4(a).
(b)に示すように、アイランド1の周囲に内部リード
2を配列して設け、アイランド1の上に半導体チップ4
を搭載して半導体チップ4の電極と内部リード2との間
を金属細線5で接続し、アイランド1及び内部リード2
を含めて樹脂体6により封止している。As shown in (b), internal leads 2 are arranged and provided around the island 1, and a semiconductor chip 4 is placed on the island 1.
The electrodes of the semiconductor chip 4 and the internal leads 2 are connected by thin metal wires 5, and the island 1 and the internal leads 2 are mounted.
are sealed with a resin body 6.
上述した従来の樹脂封止型半導体装置は、内部リードの
形状がほぼ直線状になっているが、近年、半導体装置の
配線基板への実装方法として、V S P (vapo
r phase soldering )法や赤外線リ
フロー法が取り入れられており、この熱ストレスにより
金属細線と内部リードとの接合部にクラックが発生して
信頼性が低下するという問題点があった。In the conventional resin-sealed semiconductor device described above, the shape of the internal lead is almost linear, but in recent years, VSP (vapo
(rphase soldering) method and infrared reflow method have been adopted, but there is a problem in that this thermal stress causes cracks to occur at the joint between the thin metal wire and the internal lead, reducing reliability.
この、クラックの発生メカニズムとしては基板実装時の
加熱により半導体全体が210°C〜260℃程度の高
温に急激にさらされ、樹脂体のガラス転移点(160℃
前後)を越えてしまい樹脂の熱膨張率が急激に大きくな
ってしまう為、樹指体が変形してしまう。The crack generation mechanism is that the entire semiconductor is rapidly exposed to high temperatures of about 210°C to 260°C due to heating during board mounting, and the glass transition point of the resin body (160°C
(before and after) and the coefficient of thermal expansion of the resin increases rapidly, resulting in deformation of the resin.
そのため樹脂体の膨張方向へ金属細線も一緒に移動して
しまい変形する。しかし金属細線は内部リードと接合し
ている為、金属細線に応力が集中する。よって金属細線
の最も弱い部分にクラックが発生する。As a result, the thin metal wires also move in the direction of expansion of the resin body and are deformed. However, since the thin metal wire is connected to the internal lead, stress is concentrated on the thin metal wire. Therefore, cracks occur at the weakest part of the thin metal wire.
本発明の樹脂封止型半導体装置は、半導体素子を搭載す
るアイランドと、前記アイランドの周囲に設けた内部リ
ードと、前記半導体素子と前記内部リードを電気的に接
続する金属細線と、前記アイランド及び前記内部リード
を含んで封止する樹脂体とを有する樹脂封止型半導体装
置において、前記内部リードが両側面に設けた凹部を有
する。The resin-sealed semiconductor device of the present invention includes an island on which a semiconductor element is mounted, an internal lead provided around the island, a thin metal wire electrically connecting the semiconductor element and the internal lead, and a metal wire that electrically connects the semiconductor element and the internal lead. In a resin-sealed semiconductor device having a resin body that includes and seals the internal leads, the internal leads have recesses provided on both sides.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)、(b)は本発明の第1の実施例を示す一
部切欠平面図及びA−A’線断面図である。FIGS. 1(a) and 1(b) are a partially cutaway plan view and a sectional view taken along the line AA', showing a first embodiment of the present invention.
第1図(a)、(b)に示すように、中央部に設けたア
イランド1の周囲に配列して設けた内部リード2の両側
面に非対称的に凹部3を設けている0次に、アイランド
1の上に半導体チップ4を搭載し、半導体チップ4の電
極と内部リード2の先端部を金属細線5により接続する
0次に、アイランド1及び内部リード2を含んで樹脂体
6で封止し樹脂封止型半導体装置を構成する。As shown in FIGS. 1(a) and 1(b), the 0-order has recesses 3 asymmetrically provided on both sides of internal leads 2 arranged around an island 1 provided in the center. A semiconductor chip 4 is mounted on the island 1, and the electrodes of the semiconductor chip 4 and the tips of the internal leads 2 are connected by thin metal wires 5.Then, the island 1 and the internal leads 2 are sealed with a resin body 6. A resin-sealed semiconductor device is then constructed.
次に、従来の樹脂封止型半導体装置と本発明の樹脂封止
型半導体装置を使用して評価試験を行ない以下の結果を
得た。Next, an evaluation test was conducted using a conventional resin-sealed semiconductor device and a resin-sealed semiconductor device of the present invention, and the following results were obtained.
まず、従来及び本発明の樹脂封止型半導体装置を温度サ
イクル(−60°C〜+150’C)及び加湿(85℃
、85%)の条件下に置き、次に、配線基板への実装方
法である赤外線リフロー(210℃〜260℃)法を用
いた急加熱実装を行ない金属細線と内部リードの接合部
を観察した結果、従来技術では80%程度の確率で内部
リードと金属細線との接合部で金属細線にクラックを発
生していたが、本発明では、5%程度にクラック発生率
を低下させることができた。First, the resin-sealed semiconductor devices of the conventional and the present invention were subjected to temperature cycles (-60°C to +150'C) and humidification (85°C).
, 85%), and then we performed rapid heating mounting using the infrared reflow method (210°C to 260°C), which is a mounting method on a wiring board, and observed the joint between the thin metal wire and the internal lead. As a result, in the conventional technology, cracks occurred in the thin metal wire at the joint between the internal lead and the thin metal wire with a probability of about 80%, but with the present invention, the crack occurrence rate was able to be reduced to about 5%. .
第2図は本発明の第2の実施例を示す一部切欠平面図、
第3図(a)、(b)は本発明の第2の実施例の内部リ
ードの拡大平面図及びB−B’線断面図である。FIG. 2 is a partially cutaway plan view showing a second embodiment of the present invention;
FIGS. 3(a) and 3(b) are an enlarged plan view and a sectional view taken along the line BB' of an internal lead according to a second embodiment of the present invention.
第2図及び第3図(a)、(b)に示すように、内部リ
ード2の両側面に内部リード2の下面より内部リード2
の板厚の1/2程度の高さに左右交互に凹部3aを設け
た以外は第1の実施例と同一の構成を有しており、第1
の実施例に比べて内部リードの強度が上がり、リード2
が変形しにくくなる利点がある。As shown in FIGS. 2 and 3 (a) and (b), the internal lead 2 is attached to both sides of the internal lead 2 from the bottom surface of the internal lead 2.
It has the same structure as the first embodiment except that recesses 3a are provided alternately on the left and right sides at a height of about 1/2 of the plate thickness of the first embodiment.
The strength of the internal lead is increased compared to the example of
This has the advantage that it is less likely to deform.
以上説明したように本発明は半導体チップを搭載するア
イランドの周囲に配列した内部リードの両側面に左右交
互に凹部を設けることにより、回路基板上への実装時に
内部リードの接合部に加わる熱応力によって発生し易い
金属細線のクラックを防止することができ、半導体装置
の信頼性を向上させるという効果を有する。As explained above, the present invention provides recesses alternately on both sides of the internal leads arranged around the island on which the semiconductor chip is mounted, so that thermal stress is applied to the joints of the internal leads when mounted on a circuit board. This has the effect of preventing cracks in the thin metal wires that are likely to occur due to this, and improving the reliability of the semiconductor device.
第1図(a)、(b)は本発明の第1の実施例を示す一
部切欠平面図及びA−A’線断面図、第2図は本発明の
第2の実施例を示す一部切欠平面図、第3図(a)、(
b)は本発明の第2の実施例の内部リードの拡大平面図
及びB−B’線断面図、第4図(a)、(b)は従来の
樹脂封止型半導体装置−例を示す一部切欠平面図及びc
−c’線断面図である。
1・・・アイランド、2・・・内部リード、3・・・凹
部、4・・・半導体チップ、5・・・金属細線、6・・
・樹脂体、7・・・外部リード。1(a) and (b) are a partially cutaway plan view and a sectional view taken along the line A-A' showing a first embodiment of the present invention, and FIG. 2 is a diagram showing a second embodiment of the present invention. Partial cutaway plan view, Fig. 3(a), (
b) is an enlarged plan view and a sectional view taken along the line B-B' of the internal lead of the second embodiment of the present invention, and FIGS. 4(a) and 4(b) show an example of a conventional resin-sealed semiconductor device. Partially cutaway plan view and c
It is a sectional view taken along the line -c'. DESCRIPTION OF SYMBOLS 1... Island, 2... Internal lead, 3... Recessed part, 4... Semiconductor chip, 5... Metal thin wire, 6...
-Resin body, 7...external lead.
Claims (1)
周囲に設けた内部リードと、前記半導体素子と前記内部
リードを電気的に接続する金属細線と、前記アイランド
及び前記内部リードを含んで封止する樹脂体とを有する
樹脂封止型半導体装置において、前記内部リードが両側
面に設けた凹部を有することを特徴とする樹脂封止型半
導体装置。An island on which a semiconductor element is mounted, an internal lead provided around the island, a thin metal wire that electrically connects the semiconductor element and the internal lead, and a resin body that includes and seals the island and the internal lead. 1. A resin-sealed semiconductor device having a resin-sealed semiconductor device, wherein the internal lead has recesses provided on both sides.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9401789A JPH02271561A (en) | 1989-04-12 | 1989-04-12 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9401789A JPH02271561A (en) | 1989-04-12 | 1989-04-12 | Resin-sealed semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02271561A true JPH02271561A (en) | 1990-11-06 |
Family
ID=14098743
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9401789A Pending JPH02271561A (en) | 1989-04-12 | 1989-04-12 | Resin-sealed semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02271561A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5834837A (en) * | 1997-01-03 | 1998-11-10 | Lg Semicon Co., Ltd. | Semiconductor package having leads with step-shaped dimples |
WO2007043562A1 (en) * | 2005-10-14 | 2007-04-19 | Sharp Kabushiki Kaisha | Interconnector, solar battery string using such interconnector, method for manufacturing such solar battery string and solar battery module using such solar battery string |
WO2007119365A1 (en) * | 2006-04-14 | 2007-10-25 | Sharp Kabushiki Kaisha | Solar cell, solar cell string and solar cell module |
JP2007287861A (en) * | 2006-04-14 | 2007-11-01 | Sharp Corp | Solar cell, solar cell string, and solar cell module |
JP2008021831A (en) * | 2006-07-13 | 2008-01-31 | Sharp Corp | Solar battery, solar-battery string, and solar-battery module |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60177664A (en) * | 1984-02-24 | 1985-09-11 | Hitachi Ltd | Semiconductor device |
JPS60261161A (en) * | 1984-06-08 | 1985-12-24 | Hitachi Ltd | Semiconductor device |
-
1989
- 1989-04-12 JP JP9401789A patent/JPH02271561A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60177664A (en) * | 1984-02-24 | 1985-09-11 | Hitachi Ltd | Semiconductor device |
JPS60261161A (en) * | 1984-06-08 | 1985-12-24 | Hitachi Ltd | Semiconductor device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5834837A (en) * | 1997-01-03 | 1998-11-10 | Lg Semicon Co., Ltd. | Semiconductor package having leads with step-shaped dimples |
WO2007043562A1 (en) * | 2005-10-14 | 2007-04-19 | Sharp Kabushiki Kaisha | Interconnector, solar battery string using such interconnector, method for manufacturing such solar battery string and solar battery module using such solar battery string |
WO2007119365A1 (en) * | 2006-04-14 | 2007-10-25 | Sharp Kabushiki Kaisha | Solar cell, solar cell string and solar cell module |
JP2007287861A (en) * | 2006-04-14 | 2007-11-01 | Sharp Corp | Solar cell, solar cell string, and solar cell module |
US8440907B2 (en) | 2006-04-14 | 2013-05-14 | Sharp Kabushiki Kaisha | Solar cell, solar cell string and solar cell module |
JP2008021831A (en) * | 2006-07-13 | 2008-01-31 | Sharp Corp | Solar battery, solar-battery string, and solar-battery module |
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