JPS60134453A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPS60134453A
JPS60134453A JP58241909A JP24190983A JPS60134453A JP S60134453 A JPS60134453 A JP S60134453A JP 58241909 A JP58241909 A JP 58241909A JP 24190983 A JP24190983 A JP 24190983A JP S60134453 A JPS60134453 A JP S60134453A
Authority
JP
Japan
Prior art keywords
conductors
lead
lead frame
leads
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58241909A
Other languages
Japanese (ja)
Inventor
Toshihiro Yamada
山田　俊宏
Akiomi Kono
顕臣 河野
Motohiro Sato
佐藤　元宏
Akihiko Yamamoto
明彦 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58241909A priority Critical patent/JPS60134453A/en
Publication of JPS60134453A publication Critical patent/JPS60134453A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the reliability of joining by previously cladding the surfaces of a large number of lead frames by two layers of Al and Al-Si alloys when the lead frames are joined with a ceramic substrate. CONSTITUTION:Wiring conductors 11, one parts thereof are removed at the central section, are bonded with one surface of a ceramic substrate 1 while being mutually opposed, and a semiconductor elemen 5 is fixed to the internal end sections of the conductors by using solder balls 12. The element 5 including one parts of the conductors 11 are covered with a cap 13, and the substrate 1 sides of the cap 13 are bonded with the conductors 11 by using low melting-point glass 4. External leads 6 constituting a lead frame are each connected on the other end sides of the conductors 11, but clad layers consisting of double layers of Al foils 14 and Al-Si eutectic alloy foils 15 containing 9-11% Si are formed previously on one surface or both surfaces of the lead 6 composed of fernico, 42 alloy, Cu, etc. at that time. Accordingly, the tensile strength of the lead 6 is increased, and a space between the leads can also be narrowed.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置用リードフレームに係り、特にセラ
ミック基板に多数のリードを接合させるに好適な半導体
装置用リードフレームを提供することにある。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a lead frame for a semiconductor device, and particularly to provide a lead frame for a semiconductor device suitable for bonding a large number of leads to a ceramic substrate.

〔発明の背景〕[Background of the invention]

従来公知の半導体装置の一例を第１図および第２図に示
す。この半導体装置はベース部Ａとキャップ部Ｂからな
る。ベース部Ａは絶縁体板１、低融点ガラス２からなる
。キャップ部Ｂは同じく絶縁体板３と低融点ガラス４か
らなる。絶縁体板１にメタライズした金とシリコンの共
晶合金によす半導体素子５は絶縁体板１に接合される。An example of a conventionally known semiconductor device is shown in FIGS. 1 and 2. This semiconductor device consists of a base part A and a cap part B. The base portion A consists of an insulator plate 1 and a low melting point glass 2. The cap part B similarly consists of an insulator plate 3 and a low melting point glass 4. A semiconductor element 5 made of a eutectic alloy of gold and silicon metallized on the insulator plate 1 is bonded to the insulator plate 1.

ベース部ＡにＭ置した外部接続用リード６（以下、リー
ドと呼ぶ）と半導体素子５とは金もしくはＡＱなどのボ
ンディングワイヤー７で結合される。この後、ベース部
Ａとキャップ部Ｂは低融点ガラス２および４により接合
される。External connection leads 6 (hereinafter referred to as leads) placed on the base portion A are bonded to the semiconductor element 5 using bonding wires 7 made of gold, AQ, or the like. After this, the base part A and the cap part B are joined by the low melting glasses 2 and 4.

このような半導体装置に用いらＩｃるリード６の数は半
導体装置の大容量化の傾向からすでに一半導体装置当り
１００を越え、さらに増加する傾向にある。The number of leads 6 used in such semiconductor devices has already exceeded 100 per semiconductor device, and is on the rise, due to the trend toward larger capacities of semiconductor devices.

リード６の初期形状は第３図に示すようにリードフレー
ム８と呼ばれ全リードが一体結合した状態にある。リー
ド６のｒｖＪ隔９はリード間の絶縁およびワイヤーボン
ディングに必要な寸法などから決まる。このためリード
６の数が増加すると、リードフレーム８の内側空間１０
は大きくなる。また、半導体素子５の集積度が増加し発
熱量が増加すると、その放熱対策が必要となり、絶縁体
板１または絶縁体板１と絶縁体板３を通常使用されるア
ルミナ（ＡＱ２０９）から炭化ケイ素（Ｓｉｎ）に代え
ることが考えられている。この場合、炭化ケイ素のぬれ
性が悪く、通常の手法では炭化ケイ素から成る絶縁体板
１あるいは３とリード６を完全な形で接合することは困
難であった。The initial shape of the leads 6 is called a lead frame 8, as shown in FIG. 3, in which all the leads are integrally connected. The rvJ spacing 9 of the leads 6 is determined by the insulation between the leads and the dimensions required for wire bonding. Therefore, when the number of leads 6 increases, the inner space 10 of the lead frame 8
becomes larger. In addition, as the degree of integration of semiconductor elements 5 increases and the amount of heat generated increases, heat dissipation measures are required. (Sin) is being considered. In this case, silicon carbide has poor wettability, and it is difficult to completely join insulator plate 1 or 3 made of silicon carbide to lead 6 using normal techniques.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、リード数の多い大容量半導体装置にお
いて、リードの間隙を狭くすることができる半導体装置
用リードフレームを提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a lead frame for a semiconductor device in which the gap between the leads can be narrowed in a large-capacity semiconductor device with a large number of leads.

〔発明の概要〕[Summary of the invention]

本発明、の半導体装置用リードフレームはリードフレー
ムの表面にＡＱ及びＡΩ−８上台金の二層をクラッドし
たものである。The lead frame for a semiconductor device according to the present invention has two layers of AQ and AΩ-8 base metal clad on the surface of the lead frame.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を第４図〜第５図により説明する
。第４図は本発明の一実施例を説明するための半導体装
置の断面図である。絶縁体板１の表面に半導体素子５へ
の信号の入出力などに必要な数の配線導体１１を形成す
る。配線導体１１は絶縁体板１と接合しかつ７１０＝”
４２合金、銅合金などのリード材と直接もしくはインサ
ート材を介して間接的に接合可能な材質が望ましい。配
線導体１１の中央付近のパターンの端部位置は配線導体
１１に半田ボール９によって半導体素子５を接合するた
めに、半導体素子５の接合部の電極の配置と相対するよ
うに形成する。Embodiments of the present invention will be described below with reference to FIGS. 4 and 5. FIG. 4 is a sectional view of a semiconductor device for explaining one embodiment of the present invention. A number of wiring conductors 11 necessary for inputting and outputting signals to and from the semiconductor element 5 are formed on the surface of the insulator plate 1. The wiring conductor 11 is connected to the insulator plate 1 and 710="
A material that can be joined directly or indirectly to a lead material such as 42 alloy or copper alloy is desirable. The end position of the pattern near the center of the wiring conductor 11 is formed so as to be opposed to the arrangement of the electrodes at the joint portion of the semiconductor element 5 in order to join the semiconductor element 5 to the wiring conductor 11 with the solder ball 9.

また、配線導体１１の絶縁体板１の外側パターンはり−
ド６の絶縁体板１への接合部形状と一致するように形成
する。かかる準備の後、配線導体１１の外側のパターン
と一致させリード６を重ね合わせる。この後、高真空も
しくは不活性ガス中では線導体１１とり−ド６を拡散接
合により接合する。In addition, the outer pattern beam of the insulator plate 1 of the wiring conductor 11 is
It is formed to match the shape of the joint part of the board 6 to the insulator plate 1. After such preparation, the leads 6 are overlapped to match the outer pattern of the wiring conductor 11. Thereafter, the wire conductors 11 and the leads 6 are bonded by diffusion bonding in a high vacuum or an inert gas.

つぎに、半導体素子５を絶縁体板１の中央部の配線導体
１１の半導体素子５接合部に半田ボール１２により接合
する。最後にキャップ１３を半導体素子５を覆うように
イ氏融点ガラス４で絶縁体板ｌに接合する。Next, the semiconductor element 5 is bonded to the semiconductor element 5 bonding portion of the wiring conductor 11 in the center of the insulator plate 1 using the solder balls 12. Finally, the cap 13 is bonded to the insulating plate 1 using the melting point glass 4 so as to cover the semiconductor element 5.

上記の半導体装置において、絶縁体板１へのリード６の
接合は第５図に示すリードフレームを用いて拡散接合す
る。第５図は本発明のリードフレゴ ームの断面を示したもので、７エロ＝Ｖ、４２合金また
はＣｕなどから成るリード６上にはＡＱ箔１４及びＡＱ
−５ｉ共晶合金（９〜１１％Ｓｉ）箔１５の二層がクラ
ッドされている。本発明では、ＡＱ−８上共品合金ｆＩ
ｉ１５が絶縁体板１に接触させて設置し、真空炉中にて
加圧力０．５ｋｇｆ／ｍｎ２で加圧し、ＡＱ−８上共晶
合金箔５の共晶温度（５８０℃）とＡＱ箔１４（ＡＱ：
溶融温度６６０℃）の溶融温度の間の温度範囲に加熱し
て接合する。In the above semiconductor device, the leads 6 are bonded to the insulator plate 1 by diffusion bonding using a lead frame shown in FIG. FIG. 5 shows a cross section of the lead frame of the present invention, in which an AQ foil 14 and an AQ foil 14 and an AQ
Two layers of -5i eutectic alloy (9-11% Si) foil 15 are clad. In the present invention, AQ-8 upper alloy fI
i15 is installed in contact with the insulator plate 1, and is pressurized with a pressure of 0.5 kgf/m2 in a vacuum furnace, and the eutectic temperature (580°C) of the AQ-8 upper eutectic alloy foil 5 and the AQ foil 14 are (AQ:
The bonding is performed by heating to a temperature range between the melting temperature of 660°C (melting temperature: 660°C).

本発明のリードフレームの製作は次の方法で行コ う、まず、リード６の材料である７１０二と４２合金ま
たはＣｕなどを圧延する際に片面あるいは両面に、あら
かじめＡＱ箔１４とＡＱ−８ｉ共晶合金箔工５の二層を
クラッドして設置し、これらを同時に圧延することによ
って、中心部が７１０ゴ 二ビ４２合金あるいはＣｕで形成し表面がＡＱ１４およ
びＡ　Ｑ　−Ｓ　ｉ共晶合金１５でクラッドされたリー
ドフレーム素材を製作する。その後、プレスによる打抜
またはエツチングによって第３図の形状のリードフレー
ムを製作する。The lead frame of the present invention is manufactured by the following method. First, when rolling 7102 and 42 alloy or Cu, which are the materials of the lead 6, AQ foil 14 and AQ-8 By cladding and installing two layers of eutectic alloy foil work 5 and rolling them simultaneously, the center part is formed of 710 Gonibi 42 alloy or Cu, and the surface is made of AQ14 and AQ-S i eutectic alloy. 15. Manufacture the clad lead frame material. Thereafter, a lead frame having the shape shown in FIG. 3 is manufactured by punching with a press or etching.

本発明のリードフレームを用いて接合したり−ド６と絶
縁体板ｌとの引張強さは絶縁体Ｆｉ１の材料がアルミナ
（ＡＱｓ＋ｏｓ）の場合的２ｋｇ／ｍｍ”、炭化ケイ素
（ＳｉＣ）の場合、約１ｋｇ／＋＋ａ”となり。The tensile strength of the lead frame 6 and the insulator plate 1 bonded using the lead frame of the present invention is 2 kg/mm when the material of the insulator Fi1 is alumina (AQs+os), and when the material is silicon carbide (SiC). , approximately 1kg/++a".

従来技術の低融点ガラスに比べて著しく大きな値となる
。This value is significantly larger than that of conventional low melting point glasses.

〔発明の効果〕〔Effect of the invention〕

以上説明した本発明によれば、拡散接合でリードと絶縁
体板上の配線導体とを接合するため、接合部が限定でき
、結果としてリードの間隔を狭くすることが可能となる
という効果が得られ、その他リードと配線導体が金属結
合するため接合の信頼性があがるという効果も得られる
。According to the present invention described above, since the leads and the wiring conductor on the insulator board are bonded by diffusion bonding, the bonding area can be limited, and as a result, the gap between the leads can be narrowed. In addition, since the lead and the wiring conductor are metallurgically bonded, the reliability of the bonding is improved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体装置の平面図、第２図は第１図ａ
−ａの断面図、第３図はリードフレームの平面図、第４
図は本発明の詳細な説明するための半導体装置の断面図
、第５図は本発明のり−ドフレームの断面図である。 １・・・絶縁体板、２・・・低融点ガラス、３・・・絶
縁体板、４・・・低融点ガラス、５・・・半導体素子、
６・・・リード、７・・・ボンディングワイヤー、８・
・・リードフレーム、９・・・リードの間隔、１０・・
・リードフレームの内側空間、１１・・・配線導体、１
２・・・半田ボール、１３・・・キャップ、１４・・・
ＡΩ材、１５・・・ＡＡ−８ｉ共晶合金。 代理人　弁理士　高橋明夫 扇　１　図 カ　２　図Fig. 1 is a plan view of a conventional semiconductor device, and Fig. 2 is a plan view of a conventional semiconductor device.
-a is a cross-sectional view, Figure 3 is a plan view of the lead frame, and Figure 4 is a cross-sectional view of lead frame.
The figure is a cross-sectional view of a semiconductor device for explaining the present invention in detail, and FIG. 5 is a cross-sectional view of a board frame of the present invention. DESCRIPTION OF SYMBOLS 1... Insulator plate, 2... Low melting point glass, 3... Insulator plate, 4... Low melting point glass, 5... Semiconductor element,
6... Lead, 7... Bonding wire, 8...
...Lead frame, 9...Lead spacing, 10...
・Inner space of lead frame, 11...Wiring conductor, 1
2...Solder ball, 13...Cap, 14...
AΩ material, 15...AA-8i eutectic alloy. Agent Patent Attorney Akio Takahashi Ougi 1 Figure 2 Figure

Claims (1)

【特許請求の範囲】[Claims] 半導体装置用リードフレームにおいて、前記リードフレ
ーム表面をＡＱ及びＡＱ−８ｉ合金の二層によってクラ
ッドしたことを特徴とする半導体装置用リードフレーム
。1. A lead frame for a semiconductor device, characterized in that the surface of the lead frame is clad with two layers of AQ and AQ-8i alloys.
JP58241909A 1983-12-23 1983-12-23 Lead frame for semiconductor device Pending JPS60134453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58241909A JPS60134453A (en) 1983-12-23 1983-12-23 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58241909A JPS60134453A (en) 1983-12-23 1983-12-23 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPS60134453A true JPS60134453A (en) 1985-07-17

Family

ID=17081348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58241909A Pending JPS60134453A (en) 1983-12-23 1983-12-23 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPS60134453A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0556550A2 (en) * 1992-02-18 1993-08-25 International Business Machines Corporation Ceramic chip carrier with lead frame or edge clip
US11272822B2 (en) 2013-11-12 2022-03-15 Irobot Corporation Mobile floor cleaning robot with pad holder

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0556550A2 (en) * 1992-02-18 1993-08-25 International Business Machines Corporation Ceramic chip carrier with lead frame or edge clip
EP0556550A3 (en) * 1992-02-18 1994-04-06 Ibm
US11272822B2 (en) 2013-11-12 2022-03-15 Irobot Corporation Mobile floor cleaning robot with pad holder

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