JPS60134452A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60134452A
JPS60134452A JP58241907A JP24190783A JPS60134452A JP S60134452 A JPS60134452 A JP S60134452A JP 58241907 A JP58241907 A JP 58241907A JP 24190783 A JP24190783 A JP 24190783A JP S60134452 A JPS60134452 A JP S60134452A
Authority
JP
Japan
Prior art keywords
leads
semiconductor device
manufacturing
bonded
wiring conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58241907A
Other languages
Japanese (ja)
Inventor
Motohiro Sato
佐藤　元宏
Toshihiro Yamada
山田　俊宏
Akiomi Kono
顕臣 河野
Akihiko Yamamoto
明彦 山本
Kanji Otsuka
寛治 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58241907A priority Critical patent/JPS60134452A/en
Publication of JPS60134452A publication Critical patent/JPS60134452A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To narrow the spaces among leads even in a large-capacity semiconductor device having a large number of leads by diffusing and joining the leads and wiring conductors in a vacuum or an inert gas when a semiconductor element is fixed at the central section on one surface of an insulator board through solder balls positioned at both end sections of the surface, the wiring conductors are bonded with the insulator board while being brought into contact with the solder balls and the leads are fixed to the end sections. CONSTITUTION:A semiconductor element 5 is fixed at the central section of one surface of an insulator board 1 through solder balls 12 positined at both ends of the surface, and wiring conductors 11 consisting of fernico, 42 alloy, copper alloy, etc. are bonded with the insulator board 1 while being brought into contact with the solder balls 12. Leads 6 are each connected to both end sections of the wiring conductors 11 as follows. That is, the wiring conductors 11 and the leads 6 are stacked, and diffused and joined in a high vacuum or an inert gas. The element 5 is covered with a cap 13, and the edge sections of the cap are fixed to the conductors 11 by using low melting-point glass 4.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、半導体装置の製法に係り、特に多数のリード
を有する半導体装置に好適な製法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method suitable for manufacturing a semiconductor device having a large number of leads.

〔発明の背景〕[Background of the invention]

従来の半導体装置の一例を第１図および第２図に示す。 An example of a conventional semiconductor device is shown in FIGS. 1 and 2.

この半導体装置はベース部Ａとキャップ部３からなる。This semiconductor device consists of a base part A and a cap part 3.

ベース部Ａは絶縁体板１、低融点ガラス２からなる。キ
ャップ部Ｂは同じく絶縁体板３と低融点ガラス４からな
る。絶縁体板１にメタライズした金とシリコンの共晶合
金により了導体索子５は絶縁体板１に接合される。ベー
ス部Ａに設置した外部接続用リード６　（以下、リード
と呼ぶ）と半導体素子５とは金もしくはＡｊ）などのボ
ンディングワイヤー７で接合される。この後、ベース部
Ａとキャップ部Ｂは低融点ガラス２および４により接合
される。The base portion A consists of an insulator plate 1 and a low melting point glass 2. The cap part B similarly consists of an insulator plate 3 and a low melting point glass 4. The conductor cable 5 is joined to the insulator plate 1 by a eutectic alloy of gold and silicon which is metallized on the insulator plate 1. External connection leads 6 (hereinafter referred to as leads) installed on the base portion A and the semiconductor element 5 are bonded with a bonding wire 7 made of gold, Aj), or the like. After this, the base part A and the cap part B are joined by the low melting glasses 2 and 4.

このような半導体装置に用いられるリード６の数は半導
体装『の大容量化の傾向からすでに−・半導体装釘当り
１００を越え、さらに増加する傾向にある。The number of leads 6 used in such semiconductor devices has already exceeded 100 per semiconductor nail, and is on the rise, due to the trend toward larger capacities of semiconductor devices.

リード６の初期形状は第３図に示すようにり一部フレー
ｌ）８と呼ばれ全リードが一体結合した状態にある。リ
ード６の間隔９はリード間の絶縁およびワイヤーボンデ
ィングに必要な寸法などから決まる。このためリード６
の数が増加すると、リードフレー１１８の内側空間１０
は大きくなる。半導体素子５は結合部の数が増加しても
それほど大きくならず、したがってボンディングワイヤ
−７の長さも長くなり、ボンディングワイヤ−７同士の
接触により短絡する危険が大きくなる。As shown in FIG. 3, the initial shape of the lead 6 is called a partially flared shape 8, in which all the leads are integrally connected. The spacing 9 between the leads 6 is determined by the insulation between the leads and the dimensions required for wire bonding. For this reason, lead 6
As the number increases, the inner space 10 of the reed fly 118
becomes larger. Even if the number of bonding parts increases, the semiconductor element 5 does not become so large, and therefore the length of the bonding wires 7 also increases, increasing the risk of short-circuiting due to contact between the bonding wires 7.

このような半導体装置の構造的不具合を回避する　゛　
構造のものがあるが しかしこのような構造のものにおいては配線導体番とリ
ード番との接合に問題である。すなわち配線導体舎とり
一部呑を接合する場合、ｌ）はんだ付け、２）ロウ付け
、３）レーザー溶接、４）エレクトロンビーム溶接など
あるが１）、２）の方法においては配線導体側接合部形
状をリード側接合部形状より大きくしなければならず、
リード数が多い場合には不適である。また、３）、４）
はともにリードまたは配線導体を溶融する温度まで局部
加熱するために、接合後の冷却時に過大の熱ひずみが発
生し接合部及びその近傍の＃Ｉ縁板で破壊が生ずるなど
の欠点があった。To avoid such structural defects in semiconductor devices ゛
However, in such a structure, there is a problem in joining the wiring conductor number and the lead number. In other words, when joining a part of the wiring conductor housing, there are l) soldering, 2) brazing, 3) laser welding, 4) electron beam welding, etc., but in methods 1) and 2), the wiring conductor side joint The shape must be larger than the lead side joint shape,
It is unsuitable when the number of reads is large. Also, 3), 4)
In both cases, the leads or wiring conductors are locally heated to a temperature that melts them, so excessive thermal strain occurs during cooling after bonding, resulting in damage to the bonded portion and the #I edge plate in its vicinity.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、リード数の多い大容量半導体装置にお
いてリード間隔を狭くすることが可能な製法を提供する
ことにある。An object of the present invention is to provide a manufacturing method that can narrow the lead spacing in a large-capacity semiconductor device with a large number of leads.

〔発明の概要〕[Summary of the invention]

本発明は、大容量の半導体装置において配線導体とリー
ドの接合を小さな接合部でかつ接合時の熱ひずみを少な
くすることができる製法として拡散接合が最適であるこ
とに着目し、拡散接合を用いた新規な半導体装置の製法
にある。The present invention focuses on the fact that diffusion bonding is the most suitable manufacturing method for bonding wiring conductors and leads in large-capacity semiconductor devices with small joints and reducing thermal strain during bonding, and uses diffusion bonding. This is a new method for manufacturing semiconductor devices.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を第４図〜第６図により説明する
。第４図は本発明の一実施例を説明するための半導体装
置の断面図である。絶縁体板１の表面に半導体素子５へ
の信号の入出力などに必要な数の配線導体１１を形成す
、−・。配線導体１１は絶縁体板１と接合しかつフエロ
ニコ、４２合金、銅合金などのリード材と直接もしくは
インサート材を介して間接的に接合可能な材質が望まし
い。Embodiments of the present invention will be described below with reference to FIGS. 4 to 6. FIG. 4 is a sectional view of a semiconductor device for explaining one embodiment of the present invention. A number of wiring conductors 11 necessary for inputting and outputting signals to and from the semiconductor element 5 are formed on the surface of the insulator plate 1. The wiring conductor 11 is desirably made of a material that can be bonded to the insulator plate 1 and can be bonded directly or indirectly to a lead material such as Feronico, 42 alloy, or copper alloy through an insert material.

配線導体１１の中央イ」近のパターンの端部位置は配線
導体】１に半田ボール１′２．によって半導体素−子５
を接合するために、半導体素子５の接合部の電極の配置
と相対するように形成する。The end position of the pattern near the center of the wiring conductor 11 is the wiring conductor 1' and the solder ball 1'2. Semiconductor element 5
In order to bond the semiconductor element 5, it is formed so as to face the arrangement of the electrodes at the bonding portion of the semiconductor element 5.

また、配線導体１１の絶縁体板１の外側パターンはリー
ド６の絶縁体板１への接合部形状と一致するように形成
する。かかる準備の後、配線導体１１の外側のパターン
と一致させリード６を重ね合わせる。この後、高真空も
しくは不活性ガス中で配線導体１１とリード６を拡散接
合により接合する。Further, the outer pattern of the wiring conductor 11 on the insulator plate 1 is formed to match the shape of the joint portion of the lead 6 to the insulator plate 1. After such preparation, the leads 6 are overlapped to match the outer pattern of the wiring conductor 11. Thereafter, the wiring conductor 11 and the lead 6 are bonded by diffusion bonding in a high vacuum or inert gas.

つぎに、半導体素子５を配線導体１１に半田ボール１２
により接合する。最後にキャップ１３を半導体素子５を
覆うように低融点ガラス４で絶縁体板１に接合する。Next, the semiconductor element 5 is attached to the wiring conductor 11 using the solder balls 12.
Join by. Finally, the cap 13 is bonded to the insulator plate 1 with the low melting point glass 4 so as to cover the semiconductor element 5.

第５図は本発明の一実施例を説明するための他の半導体
装置の断面図である。第４図において半導体素子５を覆
ったキャップ１３を大きくし、絶縁体板１の外周に接合
したり一部６の一部もしくは全体を含むように低融点ガ
ラス４で接合する。FIG. 5 is a sectional view of another semiconductor device for explaining one embodiment of the present invention. In FIG. 4, the cap 13 covering the semiconductor element 5 is enlarged and bonded to the outer periphery of the insulator plate 1, or is bonded to the low melting point glass 4 so as to include part or all of the portion 6.

これらの半導体装置において、配線導体１１とり一部６
との拡散接合はつぎによる。第６図は、拡散接合部すな
わち配線導体１１とり一部６との接合部の断面図である
。第６図にＪＲいて配線導体１１の材質とし、て、Ａ　
ｕ　、　Ｍ　ｏ　、　Ｍ　ｎ　、　Ｗ　、　Ｃｕ　。In these semiconductor devices, the wiring conductor 11 and part 6
Diffusion bonding with is as follows. FIG. 6 is a cross-sectional view of the diffusion junction, that is, the junction between the wiring conductor 11 and the part 6. In Fig. 6, the material of the wiring conductor 11 for JR is A.
u, Mo, Mn, W, Cu.

ＡＱなどの金属があげられる。また、リード６の材質と
し、て、フエロニコ、４２合金、Ｃｕ合金などがあげら
れる。本実施例では配線導体１１をＣｕ、またリード６
をフエロニコとした。Examples include metals such as AQ. Further, examples of the material of the lead 6 include Ferronico, 42 alloy, and Cu alloy. In this embodiment, the wiring conductor 11 is made of Cu, and the lead 6
was named Fueronico.

このような材質の組合せにおいて、熱的影響を少なくす
るため、すなわち接合温度をできるだけ低くするために
は、インサート材１４を介して配線導体１１とリード６
は拡散接合される。インサート材１４は両面にＡＱ−３
ｔ共晶合金（８４゜９〜ｉｉ％）を１６〜１９μｍクラ
ッドしたＡＱ−８ｔブレージング材である。インサート
材１４の両面に形成されたＡＱ−３ｉ共晶合金層は、拡
散接合の際にＡ　Ｑ　−Ｓ　ｉ共晶温度（５８０℃）以
上の接合温度で液相となり、低圧力でリード６と配線導
体１１との接合面を容易に密着させて拡散を促、進させ
る。前記インサート材としてはＡＱ−８ｉブレージング
材に限定されず、ＡＱあるいはＡＱ金合金配線導体１１
あるいはり一部６の接合面に蒸着、溶射してもよい。In such a material combination, in order to reduce the thermal influence, that is, to lower the bonding temperature as much as possible, the wiring conductor 11 and the lead 6 must be connected through the insert material 14.
are diffusion bonded. Insert material 14 has AQ-3 on both sides.
This is an AQ-8t brazing material with a 16-19 μm cladding of t-eutectic alloy (84°9-ii%). The AQ-3i eutectic alloy layer formed on both sides of the insert material 14 becomes a liquid phase at a bonding temperature higher than the AQ-Si eutectic temperature (580°C) during diffusion bonding, and is bonded to the lead 6 under low pressure. The bonding surface with the wiring conductor 11 is easily brought into close contact to promote and advance diffusion. The insert material is not limited to AQ-8i brazing material, but may also be AQ or AQ gold alloy wiring conductor 11.
Alternatively, the bonding surface of the portion 6 may be vapor-deposited or thermally sprayed.

第１図で説明したように、配線導体１１とり−ド６を重
ね合わせたものを真空チャンバー内に設置し、°そのチ
ャンバー内を１　Ｑ　−’Ｔｏｒｒ台の真空度まで排気
した後に５８０℃〜６２０°Ｃの温度範囲内に加熱する
。ついで高真空、高温に保持した状態で接合部に両側か
ら加圧（約０．５ｋｇｆ／ｍｎ”　）　シ、等温、加圧
状態に所要時間（数分から３０分）保持しながら、リー
ド６と配線導体１１を拡散接合する。As explained in FIG. 1, the wiring conductors 11 and the leads 6 are placed in a vacuum chamber, and the chamber is evacuated to a vacuum level of 1 Q-' Torr, and then heated to 580 degrees Celsius. Heat to a temperature range of 620°C. Next, while maintaining high vacuum and high temperature, pressurize the joint from both sides (approximately 0.5 kgf/mn''), and while maintaining the isothermal and pressurized state for the required time (several minutes to 30 minutes), connect the lead 6 and wiring. The conductor 11 is diffusion bonded.

また、配線導体１１がＡＱでリード６が７エロ、：？ｂ
　Ｌ、　＜は４２合金の組合せにおいても前記インサー
ト材により拡散接合が可能であり、さらにリード６の接
合面側にＡ　Ｑ　−Ｓ　ｉ共晶合金を溶射して拡散接合
に供してもよい。Also, wiring conductor 11 is AQ and lead 6 is 7 erotic. b
Diffusion bonding is also possible with the combination of L and <42 alloys using the insert material, and furthermore, an AQ-Si eutectic alloy may be thermally sprayed on the bonding surface side of the lead 6 for diffusion bonding.

さらに、配線導体１１がＡＱでリード６がＣｕという材
料の組合せにおいてはインサート材を用いず、もしくは
Ａｇを用いることにより接合温度を、２００℃〜５００
℃の温度範囲とすることにより拡散接合が可能となる。Furthermore, in the combination of materials in which the wiring conductor 11 is AQ and the lead 6 is Cu, the bonding temperature can be lowered from 200°C to 500°C by not using an insert material or by using Ag.
Diffusion bonding becomes possible by setting the temperature to a temperature range of .degree.

〔発明の効果〕〔Effect of the invention〕

以上説明した本発明によれば拡散でリードと絶縁体板上
の配線導体とを接合するため、接合部が限定でき、結果
としてリードの間隔を狭ぐすることが可能となる。その
他、リードと配線導体が金属結合するため接合の信頼性
があり、リードの数の多い大容量半導体装置の製作が可
能どなるという効果も得らオしる。According to the present invention described above, since the leads and the wiring conductor on the insulator plate are bonded by diffusion, the bonding portion can be limited, and as a result, the spacing between the leads can be narrowed. In addition, since the lead and the wiring conductor are metallurgically bonded, the bonding is reliable, and it is possible to produce a large-capacity semiconductor device with a large number of leads.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体装置の平面図、第２図は第１図の
ａ−ａ断面図、第３図はリードフレーｌｓの平面図、第
４図、第５図は本発明の詳細な説明するだめの半導体装
置の断面図、第６図は拡散接合部の断面図である。 １・・・絶縁体板、２・・・低融点ガラス、３・・・絶
縁体板、４・・低融点ガラス、５・・・半導体素子、６
・・・リード、７・・・ボンディングワイヤー、８・・
・リードフレーム、９・・・リードの間隔、１０・・・
リードフレームの内側空間、１１　・配線導体、１２・
・２１′田ボール、１３・・・キャップ、１４・・・イ
ンサート材。 ′ｆＪＩｌｌｆｌ 築　３　回 ■　４　図 第　５　図 ′ｆＪ　ｚ　図FIG. 1 is a plan view of a conventional semiconductor device, FIG. 2 is a sectional view taken along line a-a in FIG. FIG. 6 is a cross-sectional view of a semiconductor device that is not to be explained, and is a cross-sectional view of a diffusion junction. DESCRIPTION OF SYMBOLS 1... Insulator plate, 2... Low melting point glass, 3... Insulator plate, 4... Low melting point glass, 5... Semiconductor element, 6
... Lead, 7... Bonding wire, 8...
・Lead frame, 9...Lead spacing, 10...
Inner space of lead frame, 11・Wiring conductor, 12・
・21' field ball, 13...cap, 14...insert material. 'fJIllfl Built 3 times ■ 4 Figure 5 Figure 'fJ z Figure

Claims (1)

【特許請求の範囲】 １、複数の電極を有する半導体素子と複数の配線導体を
配置した絶縁体板の配線導体に、半導体素子周囲の電極
が接合され、且つ上記半導体素子周囲の上記絶縁体板上
に外部接続用リードが配設された半導体装置において、
前記絶縁体板上に配置された配置導体と外部接続用リー
ドとを拡散接合により接続したことを特徴とする半導体
装置の製法。 ２、上記、半導体装置の製法において、配線導体と外部
接続用リードとの間にインサート材を挿入し、このイン
サート材の一部または全部を拡散接合の際に液相化する
ことにより、前記配線導体と外部接続用リードとを拡散
接合することを特徴とする特許請求の範囲第１項記載の
半導体装置の製法。 ３、上記インサート材として、ＡＱ−８ｔ共晶合金を主
成分としたブレージンク材またはＡＱ材を用いることを
特徴とする特許請求の範囲第１項または第２項記載の半
導体の製法。 ４、上記、半導体装置の製法において、ＡＱ−８ｉ共晶
合金もしくはＡＱを蒸着、溶射などにより表面に形成し
た配線導体または外部接続リードのいずれか一方もしく
は両方を用いたことを特徴とする特許請求の範囲第１項
記載の半導体装置の製法。[Claims] 1. An electrode around the semiconductor element is bonded to a wiring conductor of an insulator plate on which a semiconductor element having a plurality of electrodes and a plurality of wiring conductors are arranged, and the insulator plate around the semiconductor element In a semiconductor device on which external connection leads are arranged,
A method for manufacturing a semiconductor device, characterized in that the arrangement conductor arranged on the insulator plate and the external connection lead are connected by diffusion bonding. 2. In the above method for manufacturing a semiconductor device, an insert material is inserted between a wiring conductor and an external connection lead, and part or all of this insert material is liquefied during diffusion bonding, thereby forming the wiring. A method for manufacturing a semiconductor device according to claim 1, characterized in that the conductor and the external connection lead are diffusion bonded. 3. The method for manufacturing a semiconductor according to claim 1 or 2, wherein a brazing material or an AQ material containing AQ-8t eutectic alloy as a main component is used as the insert material. 4. A patent claim characterized in that, in the above method for manufacturing a semiconductor device, one or both of a wiring conductor and an external connection lead formed on the surface by vapor deposition, thermal spraying, etc. of AQ-8i eutectic alloy or AQ is used. A method for manufacturing a semiconductor device according to item 1.
JP58241907A 1983-12-23 1983-12-23 Manufacture of semiconductor device Pending JPS60134452A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58241907A JPS60134452A (en) 1983-12-23 1983-12-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58241907A JPS60134452A (en) 1983-12-23 1983-12-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60134452A true JPS60134452A (en) 1985-07-17

Family

ID=17081322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58241907A Pending JPS60134452A (en) 1983-12-23 1983-12-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60134452A (en)

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