JPH02270353A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPH02270353A
JPH02270353A JP9252089A JP9252089A JPH02270353A JP H02270353 A JPH02270353 A JP H02270353A JP 9252089 A JP9252089 A JP 9252089A JP 9252089 A JP9252089 A JP 9252089A JP H02270353 A JPH02270353 A JP H02270353A
Authority
JP
Japan
Prior art keywords
groove
chip
package
terminals
insulating plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9252089A
Other languages
Japanese (ja)
Inventor
Hironobu Hatakeyama
畠山　博伸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9252089A priority Critical patent/JPH02270353A/en
Publication of JPH02270353A publication Critical patent/JPH02270353A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

PURPOSE:To make equal the height of a semiconductor chip with the heights of electrode terminals and to make it possible to attain the length of the connection between the chip and the terminals, which is performed using gold wires, at the shortest distance by a method wherein a plurality of pieces of electrodes insulated from one another are formed on an insulating plate, a groove of a recessed part is provided in the insulating plate and a semiconductor chip is installed in the groove. CONSTITUTION:A plurality of pieces of electrodes 4a to 7a insulated from one another are formed on an insulating plate 8, a groove 9 of a recessed part is provided in the plate 8 and a semiconductor chip 1 is installed in the groove 9. For example, a groove 9 of a recessed part is provided in an insulating plate 8 and electrode terminals 4a to 7a are provided in the groove 9 as well to form a package 22. An FET chip 1 is installed in the groove 9 and the chip 1 and the terminals 4a to 7a are connected to each other by metal wires 3. Thereby, the height of the chip 1 and the heights of the terminals 4a to 7a become the same height and both of the chip 1 and the terminals 4a to 7a can be connected to each other at the shortest distance. Accordingly, an inductance component due to the gold wires becomes small and it becomes possible to bring out sufficiently the efficiency of the FET chip.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、高周波で使用される半導体装置用パッケー
ジに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for a semiconductor device used at high frequencies.

〔従来の技術〕[Conventional technology]

以下、ひ（砒）化ガリウム（ｃｈＡｓ）を用いて製造さ
れた電界効果トランジスタ（以下［ＦＥＴＪと略称する
）のチップを実装する半導体パッケージ（以下パッケー
ジと略称する）について説明する。Hereinafter, a semiconductor package (hereinafter referred to as a package) in which a field effect transistor (hereinafter referred to as FETJ) chip manufactured using gallium arsenide (chAs) is mounted will be described.

第３図は従来のパッケージにＦＥＴチップが装着された
状態を示す斜視図である。FIG. 3 is a perspective view showing a state in which an FET chip is attached to a conventional package.

図において、（１）はＦＥＴチップ、（２）はパッケー
ジ、（８）はＦＥＴチップ（１）とパッケージ（２）と
を接続するための金線、（４ａ）　、　（５ａ）　、　
（６ａ）　、　（７ａ）は電極端子、（８）は絶縁体で
ある。In the figure, (1) is the FET chip, (2) is the package, (8) is the gold wire for connecting the FET chip (1) and the package (2), (4a), (5a),
(6a) and (7a) are electrode terminals, and (8) is an insulator.

次に動作について説明する。ＦＥＴチップ（１）と電極
端子（４ａ）、　（５ａ）　、　（６ａ）　、　（７ａ
）とを金線（８）で接続するとき、ＦＥＴチップ（１）
の高き分だけ金線（８）が長くなり、使用する周波数帯
域が高くなればなる程無視できなくなる。す°なわち、
金線（８）がインダクタンスとしてまた抵抗成分として
働くため、極力金線（８）の長さを短くしなければなら
ない。Next, the operation will be explained. FET chip (1) and electrode terminals (4a), (5a), (6a), (7a
) with the gold wire (8), the FET chip (1)
The gold wire (8) becomes longer by the amount of height, and the higher the frequency band used, the more it cannot be ignored. That is,
Since the gold wire (8) acts as an inductance and a resistance component, the length of the gold wire (8) must be made as short as possible.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体装置用パッケージは以上のように構成され
ているので、金線の長さが周波数特性上重要になシ、金
線が長いとインダクタンスが大きくなり、ＦＥＴチップ
の性能を低下させてしまうため、極力その長さを短くし
なければならず、作業性が悪く極めて多くの労力を要し
ていた。Conventional semiconductor device packages are configured as described above, so the length of the gold wire is important in terms of frequency characteristics, and if the gold wire is long, the inductance will increase, reducing the performance of the FET chip. Therefore, it was necessary to shorten the length as much as possible, which resulted in poor workability and required an extremely large amount of labor.

この発明は上記のような問題点を解決するためになされ
たもので、半導体パッケージの一部に凹部の溝を設けた
パッケージを提供することを目的としている１゜ 〔課題を解決するための手段〕 この発明に係るパッケージは、ＦＥ’Ｉ’チップが入る
溝を設けたものである。This invention was made to solve the above-mentioned problems, and aims to provide a package in which a recessed groove is provided in a part of a semiconductor package. ] The package according to the present invention is provided with a groove into which the FE'I' chip is inserted.

〔作用〕[Effect]

この発明において溝内にＦＥＴチップを収納することに
より、Ｆｌ’Ｔ’チップと電極端子との高さが同一とな
り、金線による接続の長さが最短で接続できる。In this invention, by housing the FET chip in the groove, the Fl'T' chip and the electrode terminal are at the same height, and the connection length using the gold wire can be minimized.

〔実施例〕〔Example〕

第１図及び第２図はこの発明の一実施例に係るもので、
第１図はパッケージの斜視図、第２図は第１図のパッケ
ージにＦＥＴチップが装着された状況を示す斜視図であ
る。FIG. 1 and FIG. 2 are related to one embodiment of this invention.
FIG. 1 is a perspective view of the package, and FIG. 2 is a perspective view showing the package of FIG. 1 with an FET chip attached thereto.

図において（１）　、　（８１、Ｃ４ａ＞　、　（５ａ
）　、　（６ａ）　、　（７ａ）は第３図の従来例に示
したものと同等であるので説明を省略する。■はこの発
明に係るパッケージ、（９）は絶縁板（８）上に凹部の
溝を設け、電極端子（４ａ）　。In the figure (1), (81, C4a>, (5a
), (6a), and (7a) are the same as those shown in the conventional example of FIG. 3, so their explanations will be omitted. (2) is a package according to the present invention; (9) is a concave groove provided on an insulating plate (8), and an electrode terminal (4a);

（５ａ）　、　（６ａ）　、　（７ａ）を溝（９）にも
設ける。ＦＥＴチップ（１）は溝（９）内に装着される
。次に動作について説明する。ＦＥＴチップ（１）が溝
（９）に装着され、ＦＥＴチップ（１）と電極端子（４
ａ）　、　（５ａ）　、　（６ａ）　、　（７ａ）とは
同一高さとなり、それらとの接続には短い長さの金線（
８）で接続できる。(5a), (6a), and (7a) are also provided in the groove (9). The FET chip (1) is mounted within the groove (9). Next, the operation will be explained. The FET chip (1) is installed in the groove (9), and the FET chip (1) and the electrode terminal (4
a), (5a), (6a), and (7a) are at the same height, and a short length of gold wire (
8) to connect.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明によれば絶縁板上に溝を
設け、更に上記溝内にも電極を設けこの溝内にＦＥＴチ
ップを装着することにより、ＦＥＴチップと電極端子と
の高さが同一となり、最短距離で接続できるようになる
。これにより金線によるインダクタンス成分が小さくな
り、ＦＥＴチップの性能を十分引き出すことができるよ
うにな、る。また容易に配線の長さが短くできるため、
作業性が大幅に改善される効果が得られる。As explained above, according to the present invention, a groove is provided on the insulating plate, an electrode is further provided in the groove, and the FET chip is mounted in the groove, thereby increasing the height between the FET chip and the electrode terminal. They will be the same, allowing you to connect over the shortest distance. This reduces the inductance component due to the gold wire, making it possible to fully bring out the performance of the FET chip. Also, since the length of the wiring can be easily shortened,
The effect of significantly improving workability can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例を示すパッケージの斜視図
、第２図は第１図のパッケージにＦＥＴチップを装着し
た状況を示す斜視図、第３図は従来のパッケージにＦＥ
Ｔチップが装着された状況を示す斜視図である。 図において（１）はＦＥＴチップ、（８）は金線、（４
ａ）、　（５ａ）　、　（６ａ）　、　（７＆）は電極
端子、（８）は絶縁体、（９）は溝、■はパッケージで
ある。 なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a perspective view of a package showing an embodiment of the present invention, FIG. 2 is a perspective view showing a state in which an FET chip is mounted on the package of FIG. 1, and FIG.
FIG. 3 is a perspective view showing a state in which a T-chip is attached. In the figure, (1) is the FET chip, (8) is the gold wire, (4
a), (5a), (6a), and (7&) are electrode terminals, (8) is an insulator, (9) is a groove, and ■ is a package. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 絶縁板上に互いに絶縁して複数個の電極を形成し、上記
絶縁板上に凹部溝を設け、かつ上記溝内に半導体チップ
を装着したことを特徴とする半導体装置用パッケージ。A package for a semiconductor device, characterized in that a plurality of electrodes are formed on an insulating plate so as to be insulated from each other, a recessed groove is provided on the insulating plate, and a semiconductor chip is mounted in the groove.
JP9252089A 1989-04-11 1989-04-11 Package for semiconductor device Pending JPH02270353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9252089A JPH02270353A (en) 1989-04-11 1989-04-11 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9252089A JPH02270353A (en) 1989-04-11 1989-04-11 Package for semiconductor device

Publications (1)

Publication Number Publication Date
JPH02270353A true JPH02270353A (en) 1990-11-05

Family

ID=14056610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9252089A Pending JPH02270353A (en) 1989-04-11 1989-04-11 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPH02270353A (en)

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