JPH02312261A - Semiconductor device package - Google Patents

Semiconductor device package

Info

Publication number
JPH02312261A
JPH02312261A JP13321489A JP13321489A JPH02312261A JP H02312261 A JPH02312261 A JP H02312261A JP 13321489 A JP13321489 A JP 13321489A JP 13321489 A JP13321489 A JP 13321489A JP H02312261 A JPH02312261 A JP H02312261A
Authority
JP
Japan
Prior art keywords
chip
electrodes
fet chip
fet
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13321489A
Other languages
Japanese (ja)
Inventor
Hironobu Hatakeyama
畠山　博伸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13321489A priority Critical patent/JPH02312261A/en
Publication of JPH02312261A publication Critical patent/JPH02312261A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]

Abstract

PURPOSE:To enable a field effect transistor chip to display enough its performance by a method wherein one or more of electrodes formed as insulated from each other on an insulating board are made level with a semiconductor chip, and the electrodes concerned and the semiconductor chip are connected together through a gold wire or the like. CONSTITUTION:A device package of this design is composed of a field effect transistor (GaAs FET) chip 1 package main body 2, external lead electrodes 3a-6a, inner lead electrodes 3b-6b, gold wires 7 which connect a GaAs FET chip 1 with the package main body 2, and electrodes 8 which are provided through the intermediary of an insulating board and connected to the FET chip 1 through the gold wires 7, and the electrodes 8 provided through the intermediary of an insulating board and connected to the FET chip 1 are made level with the FET chip 1. Therefore, the gold wires 7 which connect them together can be made the shortest, so that the loss induced by the gold wires 7 can be minimized. By this setup, the performance of a GaAs FET chip can be displayed enough.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置用パッケージに関し、特に高周波
で使用されるパッケージに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for a semiconductor device, and particularly to a package used at high frequencies.

〔従来の技術〕[Conventional technology]

以下ヒ化ガリウムを用いて製造された電界効果トランジ
スタ（以下［ＧＩＡ＠ＦＥＴ　Ｊと略する）チップを実
装するパッケージについて説明する。A package for mounting a field effect transistor (hereinafter abbreviated as [GIA@FET J) chip manufactured using gallium arsenide will be described below.

第２図はＧａＡｓ　ＦＥＴチップが従来のパッケージに
装着された状態を示す斜視図である。FIG. 2 is a perspective view showing a GaAs FET chip mounted in a conventional package.

図において、ｆｉｌ＆’；ｔ　ＧａＡ＠ＦＥＴチップ、
（２）ハパッケージ本体、（３ｇ）（４ａ）（５ａ）（
６ａ）は外部リード電極、（３ｂ　）　（４ｂ　）　（
５１１）（６ｂ　）は内部リード電極、（７）はＧ１１
ｌ　ＦＥＴチップ１１＋とパッケージ本体（２１とを接
続する金線である。In the figure, fil&';t GaA@FET chip,
(2) Ha package body, (3g) (4a) (5a) (
6a) is the external lead electrode, (3b) (4b) (
511) (6b) is the internal lead electrode, (7) is G11
l This is a gold wire that connects the FET chip 11+ and the package body (21).

次に動作について説明する。ＧａＡ＠ＦＥＴチップ（１
）の厚み分だけパッケージ本体（２１より高くなる為、
金線け）の長さが長くなり、使用する周波１！２：帯域
が高くなる程インピーダンスが無視できなくなる。Next, the operation will be explained. GaA@FET chip (1
) is higher than the package body (21),
The longer the length of the gold wire (golden wire) becomes, and the higher the frequency 1 or 2 band used, the more the impedance cannot be ignored.

すなわち、金線（７）の長さがインダクタンスとして抵
抗成分として働く為そこＶｃ損失が生じ特性劣化が発生
する。That is, since the length of the gold wire (7) acts as an inductance and a resistance component, a Vc loss occurs there and characteristic deterioration occurs.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体用パッケージは以上のように構成されてい
るので、チップの厚み分だけ、Ｇ５Ａｓ　ＦＥＴチップ
とパッケージ本体との接続に長く配線しなければならず
、これにより高同波特性において、特性劣化が生じＧａ
Ａｓ　ＦＥＴチップの性能を十分に引き出すことが出来
なくなる。Since the conventional semiconductor package is configured as described above, the wiring between the G5As FET chip and the package body must be long enough to correspond to the thickness of the chip, which causes deterioration of high frequency characteristics. Produced Ga
As a result, the performance of the FET chip cannot be fully exploited.

この発明は以上のような間融点を解決する為になされた
もので、ＧｍＡｓ　ＦＥＴチップの厚み分だけパッケー
ジ本体内のリード電極を高くし、同一平面にした構造を
有す°る半導体装置用パッケージを提供することを目的
としている。This invention was made in order to solve the above-mentioned melting point problem, and provides a semiconductor device package having a structure in which the lead electrodes within the package body are raised by the thickness of the GmAs FET chip and are flush with each other. is intended to provide.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置用パッケージは内部リード電
極の高さをＧａＡ１　ＦＥＴチップと同一高さとし、　
ＧａＡｓ　ＦＥＴチップとの接続を最短で出来るように
したものである。In the semiconductor device package according to the present invention, the height of the internal lead electrode is the same as that of the GaA1 FET chip,
This allows connection to the GaAs FET chip to be made in the shortest possible time.

〔作用〕[Effect]

この発明における半導体装置用パッケージに、Ｇａ１ａ
　ＦＥＴチップとパッケージ本体との金線の距離が旬く
なるため、したがってインダクタンス成分が少なくなり
高周波特性がよくなる。In the semiconductor device package according to the present invention, Ga1a
Since the distance between the gold wire between the FET chip and the package body is shortened, the inductance component is reduced and high frequency characteristics are improved.

〔実施例〕〔Example〕

第１図はこの発明の一実施例による半導体装置用パッケ
ージを示す斜視図であジ、ＧａＡ＋　ＦＥＴチップが装
着された状況を示す。図において、（１）。FIG. 1 is a perspective view showing a semiconductor device package according to an embodiment of the present invention, and shows a state in which a GaA+ FET chip is mounted. In the figure, (1).

ｔ２１　、　（３ｍ）　〜（６ｇ）　、（３ｂ）　−（
５ｂ）　、　（６ｂ）　、　（７１Ｈ第２図の従来例に
示したものと同等であるので、説明の重複をさける。t21, (3m) ~ (6g), (3b) -(
5b), (6b), (71H Since it is equivalent to that shown in the conventional example shown in FIG. 2, duplication of explanation will be avoided.

（８）はセラミック等の絶縁板を介して設けられた電極
で、ＧａＡｓ　ＦＥＴチップ（！１と直接金線（７）で
接続される。(8) is an electrode provided through an insulating plate made of ceramic or the like, and is directly connected to the GaAs FET chip (!1) with a gold wire (7).

次に動作について説明する。Ｇ５Ａｓ　ＦＥＴチップ（
１）との接続は絶縁板を介して設けられた電極（８）と
は同一高さにあるため、金線（７）は最短に接続で森る
。この為、金線（７）による損失は最小ですみ、Ｇ■＾
ａ　ＦＥＴチップ（１）の性能を十分に引き出すことが
出来る。Next, the operation will be explained. G5As FET chip (
Since the connection with 1) is at the same height as the electrode (8) provided through the insulating plate, the gold wire (7) can be connected at the shortest possible height. For this reason, the loss due to gold wire (7) is minimal, and G■^
a The performance of the FET chip (1) can be fully brought out.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、絶縁板を介して設けら
れた電極の高さをＧａＡｓ　ＦＥＴチップと同一高さに
しているため、　ＧａＡａ　ＦＥＴチップとの接続には
最短で接続できるため、金線（７）の損失が最小に出来
、ＧａＡｓ　ＦＥＴチップの性能を十分に引き出せる。As described above, according to the present invention, since the height of the electrode provided through the insulating plate is the same as that of the GaAs FET chip, connection with the GaAa FET chip can be made in the shortest possible time. The loss of the line (7) can be minimized, and the performance of the GaAs FET chip can be fully brought out.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例による半導体装置用パッケ
ージの斜視図、第２図は従来の半導体装置用パッケージ
の斜視図を示す。 図において、（１）はＧａＡｖ　ＦＥＴチップ、（２１
はパッケージ本体、（３ａ）、（４ａ）　、（５ａ）、
（６ｇ）は外部リード電極、（３ｂ　）　、　（５ｂ）
　、　（６ｂ　）は内部リード電極、（７１は金線、（
８）はＰ３縁板を介して設けられた電極である。 なお、図中、同一符号は同一、又は相当部分全示す。FIG. 1 is a perspective view of a semiconductor device package according to an embodiment of the present invention, and FIG. 2 is a perspective view of a conventional semiconductor device package. In the figure, (1) is a GaAv FET chip, (21
are the package body, (3a), (4a), (5a),
(6g) is an external lead electrode, (3b), (5b)
, (6b) is an internal lead electrode, (71 is a gold wire, (
8) is an electrode provided through the P3 edge plate. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 絶縁板上に互いに絶縁して形成された複数個の電極を有
し、これら電極の１個又は複数個の電極の高さが半導体
チップと同一高さを有し、上記電極と半導体チップとが
金線等により結線されることを特徴とする半導体装置用
パッケージ。It has a plurality of electrodes formed on an insulating plate insulated from each other, one or more of these electrodes has the same height as the semiconductor chip, and the electrode and the semiconductor chip are connected to each other. A semiconductor device package characterized by being connected with gold wire or the like.
JP13321489A 1989-05-26 1989-05-26 Semiconductor device package Pending JPH02312261A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13321489A JPH02312261A (en) 1989-05-26 1989-05-26 Semiconductor device package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13321489A JPH02312261A (en) 1989-05-26 1989-05-26 Semiconductor device package

Publications (1)

Publication Number Publication Date
JPH02312261A true JPH02312261A (en) 1990-12-27

Family

ID=15099394

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13321489A Pending JPH02312261A (en) 1989-05-26 1989-05-26 Semiconductor device package

Country Status (1)

Country Link
JP (1) JPH02312261A (en)

Similar Documents

Publication Publication Date Title
JPH09321215A (en) Package for microwave circuit
JP2728322B2 (en) Semiconductor device
JPH02312261A (en) Semiconductor device package
JPH01216608A (en) Package for semiconductor device
JPS63202948A (en) Lead frame
JPS603781B2 (en) Assembly method of ultra-high frequency transistor device
JPH05326796A (en) Semiconductor device package
JPH05121458A (en) Semiconductor integrated circuit
JPH02270353A (en) Package for semiconductor device
JPH065849A (en) Structure of semiconductor device
JPH083011Y2 (en) Package for semiconductor device
JPS6142149A (en) Semiconductor device
JPS60178704A (en) Film circuit type semiconductor device
JPS6238604A (en) Piezoelectric oscillator
JP2596339B2 (en) Semiconductor device package
JPH0358461A (en) Semiconductor element case
JPH03138953A (en) High-frequency high-output-power transistor
JPH05299951A (en) Semiconductor device
JP2000091376A (en) Electronic circuit device
JPH04162729A (en) Field-effect transistor
JPS62193255A (en) Semiconductor device
JPS62188248A (en) Semiconductor device
JPH07142626A (en) Semiconductor device
JPH01173747A (en) Resin-sealed semiconductor device
JPH0595023A (en) Lead frame for semiconductor-integratedcircuit sealing device use