JPS62188248A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62188248A JPS62188248A JP61030080A JP3008086A JPS62188248A JP S62188248 A JPS62188248 A JP S62188248A JP 61030080 A JP61030080 A JP 61030080A JP 3008086 A JP3008086 A JP 3008086A JP S62188248 A JPS62188248 A JP S62188248A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- projection
- protrusion
- island
- fixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 238000007789 sealing Methods 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052802 copper Inorganic materials 0.000 abstract description 4
- 239000010949 copper Substances 0.000 abstract description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 3
- 239000010931 gold Substances 0.000 abstract description 3
- 229910052737 gold Inorganic materials 0.000 abstract description 3
- 239000003566 sealing material Substances 0.000 abstract description 3
- 230000017525 heat dissipation Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000428 dust Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
- H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野、１ 本発明は半導体装置に関する。[Detailed description of the invention] [Industrial application field, 1 The present invention relates to a semiconductor device.
従来、高周波トランジスタを有する半導体装置は第２図
（ａ＞、（ｂ）に示すように、リードフレームのアイラ
ンド部３に固着されたアルミナ等の絶縁板９上に半導体
チップ６が固着され、半導体チ・ツブ６の接地電極は、
Ａ ＩＩ等の金属細線５により絶縁板９上に形成され外
部リード７に接続されたメタライズ部８に接続されてい
た。そして半導体チップ６は絶縁性の容器１により気密
封止されていた。Conventionally, a semiconductor device having a high-frequency transistor has a semiconductor chip 6 fixed on an insulating plate 9 made of alumina or the like fixed to an island portion 3 of a lead frame, as shown in FIGS. The ground electrode of Chi-tubu 6 is
It was connected to a metallized portion 8 formed on an insulating plate 9 and connected to an external lead 7 by a thin metal wire 5 such as A II. The semiconductor chip 6 was hermetically sealed in the insulating container 1.
上述した従来の高周波トランジスタを有する半導体装置
においては、熱伝導率の良くないアルミナ等の絶縁板９
にメタライズ層を介して半導体チップ６が固着されてい
たため半導体チ・ツブ裏面から空気中までの熱抵抗が高
く消費電力が１０１０１ｉ程度しか許容できないという
問題点があった。また容器を構成するアイランド３とメ
タライズ部８の間に絶縁板９が固着されているため容量
が増加し高周波特性を劣化させていた。更に半導体チッ
プの電極から金属細線を含めて外部リードの根元までの
距離が長いため、特に接地電極の場合接地インダクタン
スが大きく高周波利得を低下させるという問題点らあっ
た。In the above-mentioned conventional semiconductor device having a high frequency transistor, an insulating plate 9 made of alumina or the like having poor thermal conductivity is used.
Since the semiconductor chip 6 was fixed to the semiconductor chip through the metallized layer, there was a problem in that the thermal resistance from the back surface of the semiconductor chip to the air was high and the power consumption could only be allowed to be about 10101i. Furthermore, since the insulating plate 9 is fixed between the island 3 and the metallized portion 8 that constitute the container, the capacitance increases and the high frequency characteristics deteriorate. Furthermore, since the distance from the electrode of the semiconductor chip to the root of the external lead including the thin metal wire is long, there is a problem in that, especially in the case of a ground electrode, the ground inductance is large and reduces the high frequency gain.
本発明の目的は、熱抵抗が低く高周波利得の向上した半
導体装置を提供するこにある。An object of the present invention is to provide a semiconductor device with low thermal resistance and improved high frequency gain.
本発明の半導体装置は、突起部を有する金属製アイラン
ドと、前記突起部に固着された半導体チップと、該半導
体チップの接地電極と前記突起部とを接続する金属細線
と、前記半導体チップを気密封止する絶縁性容器とを含
んで構成される。The semiconductor device of the present invention includes a metal island having a protrusion, a semiconductor chip fixed to the protrusion, a thin metal wire connecting a ground electrode of the semiconductor chip and the protrusion, and a metal wire connecting the semiconductor chip to the protrusion. and an insulating container to be sealed.
〔実施例：１
次に、本発明の実施例について図面を参照して説明する
。[Example: 1 Next, an example of the present invention will be described with reference to the drawings.
第１図（ａ、）、（ｌ））は本発明の一実施例の平面図
及びＡ−Ａ゛線断面図である。尚第１図（ａ）の平面図
においては容器１の上部を略しである。FIGS. 1(a) and 1(l)) are a plan view and a sectional view taken along the line A--A' of an embodiment of the present invention. In the plan view of FIG. 1(a), the upper part of the container 1 is omitted.
第１図（ａ）、（ｂ）において、銅等からなる金属製の
アイランド部３には突起部３Ａが形成されており、この
突起部３Ａ上にはＡｕ Ｓ ｎ等の固着材により半導体
チップ６が固着されている。そして半導体チップ６上の
接地電極と突起部３Ａとは金等からなる金属細線５によ
り接続されている。In FIGS. 1(a) and 1(b), a protrusion 3A is formed on a metal island 3 made of copper or the like, and a semiconductor chip is mounted on the protrusion 3A using a bonding material such as AuSn. 6 is fixed. The ground electrode on the semiconductor chip 6 and the protrusion 3A are connected by a thin metal wire 5 made of gold or the like.
更に半導体チップ６はアイランド部３と絶縁性の容器１
とにより封止材２を介して気密に封止されている。尚、
第１図（ａ）、（ｂ）において、・′１はソルダスト・
ソバ、７は外部リード、８はメタライズ部である、
このように構成全れな本実施例においては、半導体チ・
ソア６が金属製の突起部３Ａに固着されている為、半導
体チ・ツブ６の裏面からの熱放散は大きくなる。又半導
体チツア６上の接地電極ら金属細線５により突起部３Ａ
に接続されている為、従来構造のものに比べて寄生容置
及びインダクタンスは小さいものとなる。Further, the semiconductor chip 6 is connected to the island portion 3 and the insulating container 1.
It is hermetically sealed with the sealing material 2 interposed therebetween. still,
In Figures 1(a) and (b), ・′1 is solder dust・
7 is an external lead, and 8 is a metallized part.In this embodiment with the complete structure, the semiconductor chip
Since the soar 6 is fixed to the metal protrusion 3A, heat dissipation from the back surface of the semiconductor chip 6 becomes large. Further, the protrusion 3A is connected to the ground electrode on the semiconductor chip 6 by the thin metal wire 5.
, the parasitic capacitance and inductance are smaller than those of the conventional structure.
以上説明したように本発明は、銅等の熱伝導性の良い金
属からなるアイランドの突起部に半導体チップを固着し
、更に半導体チップの接地電極を金属細線により突起部
に接続することにより、半導体装置の熱抵抗を低くし高
周波利得を向上させ得る効果がある。As explained above, the present invention fixes a semiconductor chip to the protrusion of an island made of a metal with good thermal conductivity such as copper, and further connects the ground electrode of the semiconductor chip to the protrusion with a thin metal wire. This has the effect of lowering the thermal resistance of the device and improving the high frequency gain.
第１図（ａ＞、（ｂ）は本発明の一実施例の平面図及び
Ａ−Ａ’線断面図、第２図（ａ）、（ｂ）は従来の半導
体装置の一例の平面図及びＢ−Ｂ’線断面図である。
】・・・容器、２・・・封止材、３・・・アイランド部
、３Ａ・・・突起部、４・・・ソルダス１〜ツバ、５・
・・金属細線、６・・・半導体チップ、７・・・外部リ
ード、８・・・メタライズ部、９・・・絶縁板。
寮１０FIGS. 1(a) and (b) are a plan view and a sectional view taken along the line A-A' of an embodiment of the present invention, and FIGS. 2(a) and (b) are a plan view and an example of a conventional semiconductor device. It is a sectional view taken along the line B-B'.]...Container, 2...Sealing material, 3...Island portion, 3A...Protrusion portion, 4...Solder 1 to collar, 5...
. . . Thin metal wire, 6. Semiconductor chip, 7. External lead, 8. Metallized portion, 9. Insulating plate. Dormitory 10
Claims (1)
された半導体チップと、該半導体チップの接地電極と前
記突起部とを接続する金属細線と、前記半導体チップを
気密封止する絶縁性容器とを含むことを特徴とする半導
体装置。A metal island having a protrusion, a semiconductor chip fixed to the protrusion, a thin metal wire connecting a ground electrode of the semiconductor chip to the protrusion, and an insulating container hermetically sealing the semiconductor chip. A semiconductor device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61030080A JPS62188248A (en) | 1986-02-13 | 1986-02-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61030080A JPS62188248A (en) | 1986-02-13 | 1986-02-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62188248A true JPS62188248A (en) | 1987-08-17 |
Family
ID=12293817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61030080A Pending JPS62188248A (en) | 1986-02-13 | 1986-02-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62188248A (en) |
-
1986
- 1986-02-13 JP JP61030080A patent/JPS62188248A/en active Pending
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