JPS6142149A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6142149A JPS6142149A JP16355184A JP16355184A JPS6142149A JP S6142149 A JPS6142149 A JP S6142149A JP 16355184 A JP16355184 A JP 16355184A JP 16355184 A JP16355184 A JP 16355184A JP S6142149 A JPS6142149 A JP S6142149A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- conductor
- electrode
- terminal
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
Description
【発明の詳細な説明】
（１）発明の属する技術分野の説明
本発明杜牛導体装置、とくにそのパッケージ構造に関す
る。DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to a Dogyu conductor device, particularly to its package structure.
（２）従来技術の説明
従来、集積回路チップはパッケージにマウントシ、ワイ
ヤボンディングによって端子引き出し線に接続する構造
であった。この構造ではパッケージ端子とチップ電極間
にワイヤが存在する丸め、高周波領域においては、ＩＣ
回路と外部回路のインピーダンスマツチングをとること
が非常に困難となり、ワイヤ部でミスマツチングを生じ
る。そのため、チップ単体の特性はパッケージに実装す
ることによって劣化していた。(2) Description of the Prior Art Conventionally, an integrated circuit chip has a structure in which it is mounted in a package and connected to terminal lead lines by wire bonding. In this structure, there is a wire between the package terminal and the chip electrode, and in the high frequency region, the IC
It becomes very difficult to match the impedance between the circuit and the external circuit, and mismatching occurs in the wire section. Therefore, the characteristics of a single chip deteriorate when it is mounted in a package.
特に超高周波領域においては、ボンディングワイヤの形
状によってインダクタンスが異なり、個々のＩＣ間の特
性のバラツキの原因となる。Particularly in the ultra-high frequency region, the inductance varies depending on the shape of the bonding wire, causing variations in characteristics between individual ICs.
一方、高密度実装の必要性から、ケースレス形実装法と
してボンディングワイヤを使用せず゛ビームリード構造
等ＩＣチップを基板上に直接搭載する方法もあるが、一
般にＩＣの運搬、取シ扱い性、チップの保護を考えると
パッケージ実装に比べ不利である。On the other hand, due to the need for high-density mounting, there is a caseless mounting method in which the IC chip is mounted directly on the board using a beam lead structure without using bonding wires, but in general, it is easy to transport and handle the IC. , it is disadvantageous compared to package mounting when considering the protection of the chip.
（３）発明の詳細な説明
本発明はＩＣチップとＩＣ外部回路とのインピーダンス
不整合を軽減したパッケージ構造を有する半導体装置を
提供することを目的とするものである。(3) Detailed Description of the Invention An object of the present invention is to provide a semiconductor device having a package structure in which impedance mismatch between an IC chip and an IC external circuit is reduced.
（４）発明の構成
本発明は、集積回路チップを収納するパッケージにおい
て、パッケージに実装されるＩＣテ、プの電極とパッケ
ージの外部端子間を結ぶ端子引き出し線を一部インピー
ダンスをもつストリップライン構造とし、該端子引き出
し線のチ、プ電極との接続部の位置を実装されるＩＣチ
、プの電極位置と重なる位置に配置したことを特徴とす
る。(4) Structure of the Invention The present invention provides a package for storing an integrated circuit chip, in which a terminal lead wire connecting an electrode of an IC chip mounted on the package and an external terminal of the package has a strip line structure with a partial impedance. The device is characterized in that the connection portion of the terminal lead wire with the chip electrode is arranged at a position overlapping with the electrode position of the IC chip to be mounted.
（５）発明の詳細な説明 次に本発明の実施例について図面を参照して説明する。(5) Detailed description of the invention Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の断面〜、第２図はその平面
図で６！Ｄ、ＩＣチ、プ電極５と外部端子６０間を結ぶ
端子引き出しｌｌｌ１！１の下部に、誘電体２を介して
導電体３を設け、この導電体３を接地することにより、
端子引き出し線１と導電体３とでストリップラインを構
成する。このマイクロストリップラインのインピーダン
スは、端子引き出し線１の巾（Ｗ）、及び誘電体２の厚
さくｈ）、材質（Ｚ）によって、ＩＣの所要の入出力イ
ンピーダンスに適合するよう決める。Fig. 1 is a cross section of one embodiment of the present invention, and Fig. 2 is a plan view thereof. D. By providing a conductor 3 via a dielectric 2 at the bottom of the terminal drawer lll1!1 that connects the IC chip electrode 5 and the external terminal 60, and grounding this conductor 3,
The terminal lead wire 1 and the conductor 3 constitute a strip line. The impedance of this microstrip line is determined by the width (W) of the terminal lead wire 1, the thickness (h), and the material (Z) of the dielectric 2 to match the required input/output impedance of the IC.
例えば、誘電体２にアルミナセラミックを使用し、特性
インピーダンス５０Ωのストリップラインを構成するた
めにはｗ／ｈ＝ｌとすればよい。For example, in order to use alumina ceramic for the dielectric 2 and configure a strip line with a characteristic impedance of 50Ω, it is sufficient to set w/h=l.
また、端子引き出し線１は、チップ電極との接続部が実
装されるＩＣチップ４の電極５の位置に重なるように配
置し、チップ実装時には、端子引き出し線１上に、ＩＣ
チップ４の電極５を直接はんだ等で接着する。Further, the terminal lead wire 1 is arranged so that the connection portion with the chip electrode overlaps the position of the electrode 5 of the IC chip 4 to be mounted, and when the chip is mounted, the IC
The electrodes 5 of the chip 4 are directly bonded with solder or the like.
（６）発明の詳細な説明
本発明は以上説明したように、端子引き出し線をストリ
ップライン構成にし、ボンディング線を使用せず、チッ
プ電極を直接該端子引き出し線上に接着することＫより
、ＩＣチップと外部回路のインピーダンス不整合による
特性劣化を軽減する効果がある。(6) Detailed Description of the Invention As explained above, the present invention provides a method for forming an IC chip by forming a terminal lead-out line in a strip line configuration and bonding a chip electrode directly onto the terminal lead-out line without using a bonding line. This has the effect of reducing characteristic deterioration due to impedance mismatch between the external circuit and the external circuit.
第１図は本発明の実施例を示すＩＣパッケージの断面図
であり、第２図はその平面図の一部である。
１・・・・・・端子引き出し線、２・・・・・・誘電体
、３・・・・・・導電体、４・・・・・・ＩＣチップ、
５・・・・・・チップ電極、６・−・・・・外部端子。FIG. 1 is a sectional view of an IC package showing an embodiment of the present invention, and FIG. 2 is a partial plan view thereof. 1... terminal lead wire, 2... dielectric, 3... conductor, 4... IC chip,
5... Chip electrode, 6... External terminal.
Claims (1)
ぶ端子引き出し線を所定のインピーダンスをもつストリ
ップライン構造とし、該端子引き出し線の上に実装され
るＩＣチップの電極を直接接続したことを特徴とする半
導体装置。The terminal lead wire connecting the electrodes of the integrated circuit chip and the external terminals of the package has a strip line structure with a predetermined impedance, and the electrodes of the IC chip mounted on the terminal lead wire are directly connected. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16355184A JPS6142149A (en) | 1984-08-03 | 1984-08-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16355184A JPS6142149A (en) | 1984-08-03 | 1984-08-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6142149A true JPS6142149A (en) | 1986-02-28 |
Family
ID=15776043
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16355184A Pending JPS6142149A (en) | 1984-08-03 | 1984-08-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6142149A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01253246A (en) * | 1988-03-31 | 1989-10-09 | Toshiba Corp | Semiconductor integrated circuit mounting substrate, manufacture thereof and semiconductor integrated circuit device |
-
1984
- 1984-08-03 JP JP16355184A patent/JPS6142149A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01253246A (en) * | 1988-03-31 | 1989-10-09 | Toshiba Corp | Semiconductor integrated circuit mounting substrate, manufacture thereof and semiconductor integrated circuit device |
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