JPS6016453A - Package for integrated circuit device - Google Patents
Package for integrated circuit deviceInfo
- Publication number
- JPS6016453A JPS6016453A JP12451283A JP12451283A JPS6016453A JP S6016453 A JPS6016453 A JP S6016453A JP 12451283 A JP12451283 A JP 12451283A JP 12451283 A JP12451283 A JP 12451283A JP S6016453 A JPS6016453 A JP S6016453A
- Authority
- JP
- Japan
- Prior art keywords
- case
- integrated circuit
- lead terminals
- lead
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49534—Multi-layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は、集積回路装置用パンケージに係り、特に、集
積回路装置の高集積化に対応するためのパンケージの構
成に関す。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a pancage for an integrated circuit device, and more particularly to a structure of a pancage to accommodate higher integration of integrated circuit devices.
(bl 技術の背景
集積回路装置におけるリード端子導出の形態は、所謂D
IP型と言われてぃて、矩形をした該集積回路装置のパ
ンケージケースの相対する二辺のそれぞれから、複数の
リード端子が導出されているものが一般的である。集積
化素子の高集積化が進むに従ってリード端子数が多くな
ると、従来のDIP型では該ケースを大形にしてそのリ
ード端子を収容するようにしているが、該集積回路装置
の 2搭載所要面積が大きくなり実装密度から見ると、
折角の高集積化が充分に生かされない恨みがあり、また
高速動作の観点からみると該集積回路装置の内外におけ
る配線の長さが長くなり好ましいものではない。(bl Background of the Technology The form of lead terminal derivation in integrated circuit devices is the so-called D
It is called an IP type, and generally has a plurality of lead terminals led out from each of two opposing sides of a rectangular pan cage case of the integrated circuit device. As the number of lead terminals increases as the degree of integration of integrated devices progresses, the case of conventional DIP type is made larger to accommodate the lead terminals. becomes larger, and from the viewpoint of mounting density,
There is a regret that the high degree of integration has not been fully utilized, and from the viewpoint of high-speed operation, the length of wiring inside and outside the integrated circuit device becomes long, which is not desirable.
このような事情から、パッケージケースの四辺のそれぞ
れから複数のリード端子を導出した集積回路装置が出現
して来ている。Under these circumstances, integrated circuit devices have appeared in which a plurality of lead terminals are led out from each of the four sides of a package case.
[C) 従来技術と問題点
第1図(Mlは従来の集積回路装置用パッケージの一例
の斜視図、第1図(b)はその一つのリード端子の導出
構成を示した図で、■はケース、2は内部配線、3はリ
ード端子、4は接続点をそれぞれ示す。[C] Prior art and problems Figure 1 (Ml is a perspective view of an example of a conventional integrated circuit device package, Figure 1 (b) is a diagram showing the lead-out configuration of one of the lead terminals, and ■ is a perspective view of an example of a conventional integrated circuit device package. 2 indicates internal wiring, 3 indicates lead terminals, and 4 indicates connection points.
ケース四辺のそれぞれから複数のリード端子を導出して
いる通常の集積回路装置用パンケージは、第1図(a)
のように絶縁体(例えばセラミ’7り)でなるケース1
の内部にあって集積回路素子に接続される複数の内部配
線2は一平面に配置゛され、そのそれぞれに接続された
複数のリード端子3が、ケース1の四辺から四方に導出
されてなっていて、内部配線2とリード端子3との接続
部の構成は第1図tb+のようで、4がその接続点であ
る。Figure 1(a) shows a typical integrated circuit device pancage in which a plurality of lead terminals are led out from each of the four sides of the case.
Case 1 made of an insulator (e.g. ceramic) as shown in
A plurality of internal wirings 2 inside the case 1 and connected to the integrated circuit elements are arranged on one plane, and a plurality of lead terminals 3 connected to each of them are led out in all directions from the four sides of the case 1. The structure of the connecting portion between the internal wiring 2 and the lead terminal 3 is as shown in FIG. 1 tb+, and 4 is the connecting point.
この構成でなる集積回路装置用パンケージは、集積回路
素子の集積度が上がって導出線数が増加した場合、内部
配線2を微細化することは比較的に容易であるが、リー
ド端子3は、ケース1から外部に導出されるため、細く
したり隣のリード端子3との間隔を狭めたりすることに
は自ずと限度があり、その範囲を越える場合にはケース
1を大きくせざるを得す、実質的な実装密度を低下させ
る欠点がある。In the integrated circuit device pancase having this configuration, when the degree of integration of integrated circuit elements increases and the number of lead-out wires increases, it is relatively easy to miniaturize the internal wiring 2, but the lead terminals 3 Since it is led out from the case 1, there is a limit to making it thinner or narrowing the distance between the adjacent lead terminals 3, and if it exceeds this range, the case 1 must be made larger. This has the disadvantage of lowering the actual packaging density.
(dl 発明の目的
本発明の目的は上記従来の欠点に鑑み、ケースを大きく
することなく、該ケースから導出させるリード端子数の
増大を可能にした集積回路装置用パッケージを提供する
にある。(dl) OBJECTS OF THE INVENTION In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a package for an integrated circuit device that makes it possible to increase the number of lead terminals led out from the case without increasing the size of the case.
(e) 発明の構成
上記目的は、絶縁体でなるケースの内部配線にそれぞれ
独立して接続されている二本のリード端子が、一対にな
り互いに電気的に絶縁されて合体し、該ケースの一個所
から導出されていることを特徴とする本発明の集積回路
装置用パンケージによって達成される。(e) Structure of the Invention The above object is to combine two lead terminals, which are each independently connected to internal wiring of a case made of an insulator, into a pair and are electrically insulated from each other, This is achieved by the package for an integrated circuit device of the present invention, which is characterized in that it is led out from a single location.
前記互いに電気的に絶縁されて合体した二本のリード端
子は、一本のピン状になるので、外観上は従来の集積回
路装置用パンケージの一つのリード端子に対応するので
、本発明による集積回路装置用パッケージは、ケースを
大きくすることなしに、従来に比較して二倍数のリード
端子を導出することが出来、高集積化により導出線数が
多くなった集積回路素子を収容することが可能になる。The two lead terminals that are electrically insulated from each other and combined form a single pin shape, and thus correspond in appearance to one lead terminal of a conventional pancage for an integrated circuit device. Packages for circuit devices can have twice the number of lead terminals compared to conventional methods without increasing the size of the case, and can accommodate integrated circuit elements with a larger number of lead terminals due to higher integration. It becomes possible.
ff) 発明の実施例 以下本発明の一実施例を図により説明する。ff) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.
第2図1alは本発明の構成による集積回路装置用パン
ケージの一例の斜視図、第2図(blはその一対のリー
ド端子の導出構成を示した図で、1aはケース、2a・
2bは内部配線、3a・3bはリード端子、4a・4b
は接続点、5は絶縁層をそれぞれ示す。FIG. 2 1al is a perspective view of an example of a pancase for an integrated circuit device according to the structure of the present invention, and FIG.
2b is internal wiring, 3a and 3b are lead terminals, 4a and 4b
5 indicates a connection point, and 5 indicates an insulating layer.
第2図(a)において、ケース1aは例えば第2図1a
lにおけるケース1と同じ大きさであるが、内部配線は
細幅化されて二つの内部配線配線2a・2bが一対を構
成して、その配線面に対する投影は、従来の内部配線2
のスペースに収容されている。In FIG. 2(a), case 1a is, for example, FIG.
The size is the same as case 1 in case 1, but the internal wiring is narrowed and the two internal wirings 2a and 2b form a pair, and the projection on the wiring surface is similar to that of the conventional internal wiring 2.
It is housed in a space of
第2図(b)は、これらの内部配線2a・2bをそれぞ
れ独立してリード端子3a・3bにより外部に導出する
構成を示している。従来と同様に平面に配置されている
内部配線2aと、リード端子3bとの接続部で高い位置
に持ち上げられて配置されている内部配線2bとで一対
を構成し、このそれぞれに接続点4a・4bで接続され
ているリード端子3a・3bが、一対となり電気的に絶
縁する絶縁層5を挾んで合体し一本のピンを形成して、
ケースの一個所から導出されている。FIG. 2(b) shows a configuration in which these internal wirings 2a and 2b are led out to the outside through lead terminals 3a and 3b, respectively. The internal wiring 2a, which is arranged on a flat surface as in the past, and the internal wiring 2b, which is raised and arranged at a high position at the connection part with the lead terminal 3b, form a pair, and each of them has a connection point 4a. Lead terminals 3a and 3b connected by 4b form a pair and combine with an electrically insulating insulating layer 5 in between to form one pin.
It is derived from one part of the case.
従って、リード端子3a・3bは、その個々の厚さは従
来のものと比較して薄くはなる力是、幅は従来のままで
一対をなし互いに電気的に絶縁されて合体し一本のピン
状になってリード端子強度を充分に確保し、外観上は従
来の集積回路装置用パッケージの一つのリード端子に対
応しするので、本構成による集積回路装置用パンケージ
は、ケースを大きくすることなしに、従来に比較して二
倍数のリード端子を導出することが出来、高密度化によ
く
り導出線数が多入なった集積回路素子を収容することが
可能になる。Therefore, the lead terminals 3a and 3b are made into a pair, electrically insulated from each other, and combined into a single pin, although their individual thicknesses are thinner than conventional ones, and the width remains the same as before. This structure ensures sufficient lead terminal strength, and the appearance corresponds to one lead terminal of a conventional package for integrated circuit devices, so the pancage for integrated circuit devices with this configuration does not require an increase in the size of the case. In addition, it is possible to lead out twice as many lead terminals as in the past, and it is possible to accommodate integrated circuit elements with a large number of lead-out wires, which is good for high density.
(g) 発明の効果
以上に説明したように、本発jjJ]4こよる構成によ
れば、ケースを大きくすることなく、該ケースから導出
させるリード端子数の増大を可能にした集積回路装置用
パッケージを提供することが出来、高集積化により導出
線数が多くなった集積回路素子を収容し実装密度の向上
を可能にさせる効果がある。(g) Effects of the Invention As explained above, the structure according to the present invention enables an increase in the number of lead terminals led out from the case without increasing the size of the case for an integrated circuit device. It is possible to provide a package, which has the effect of accommodating an integrated circuit element whose number of lead-out lines has increased due to high integration, and making it possible to improve the packaging density.
第1図(a)は従来の集積回路装置用バノ゛ケージの一
例の斜視図、第1図(blはその一つのり−1” NM
子の導出構成を示した図、第2図(a)は本発明の構成
による集積回路装置用パンケージの一例の斜視図、第2
図(blはその一対のリード端子の導出構成を示した図
である。
図面において、1・1aはケース、2・2a・2bは内
部配線、3・3a・3bはリード端子、4・4a・4b
は接続点、5は絶縁層をそれぞれ示す。FIG. 1(a) is a perspective view of an example of a conventional bunkage for an integrated circuit device.
FIG. 2(a) is a perspective view of an example of a pancake for an integrated circuit device according to the structure of the present invention.
Figure (bl is a diagram showing the lead-out configuration of the pair of lead terminals. In the drawing, 1 and 1a are the case, 2, 2a, and 2b are internal wiring, 3, 3a, and 3b are lead terminals, and 4, 4a, and 4b
5 indicates a connection point, and 5 indicates an insulating layer.
Claims (1)
されている二本のリード端子が、一対になり互いに電気
的に絶縁されて合体し、該ケースの一個所から導出され
ていることを特徴とする集積回路装置用パッケージ。It is characterized by two lead terminals that are each independently connected to the internal wiring of a case made of an insulating material, combined into a pair, electrically insulated from each other, and led out from one point of the case. Packages for integrated circuit devices.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12451283A JPS6016453A (en) | 1983-07-08 | 1983-07-08 | Package for integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12451283A JPS6016453A (en) | 1983-07-08 | 1983-07-08 | Package for integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6016453A true JPS6016453A (en) | 1985-01-28 |
Family
ID=14887319
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12451283A Pending JPS6016453A (en) | 1983-07-08 | 1983-07-08 | Package for integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6016453A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6141869A (en) * | 1998-10-26 | 2000-11-07 | Silicon Bandwidth, Inc. | Apparatus for and method of manufacturing a semiconductor die carrier |
US6339191B1 (en) * | 1994-03-11 | 2002-01-15 | Silicon Bandwidth Inc. | Prefabricated semiconductor chip carrier |
JP2009242111A (en) * | 2009-07-23 | 2009-10-22 | Seiko Epson Corp | Printer |
-
1983
- 1983-07-08 JP JP12451283A patent/JPS6016453A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6339191B1 (en) * | 1994-03-11 | 2002-01-15 | Silicon Bandwidth Inc. | Prefabricated semiconductor chip carrier |
US6828511B2 (en) | 1994-03-11 | 2004-12-07 | Silicon Bandwidth Inc. | Prefabricated semiconductor chip carrier |
US6977432B2 (en) | 1994-03-11 | 2005-12-20 | Quantum Leap Packaging, Inc. | Prefabricated semiconductor chip carrier |
US6141869A (en) * | 1998-10-26 | 2000-11-07 | Silicon Bandwidth, Inc. | Apparatus for and method of manufacturing a semiconductor die carrier |
US6857173B1 (en) | 1998-10-26 | 2005-02-22 | Silicon Bandwidth, Inc. | Apparatus for and method of manufacturing a semiconductor die carrier |
JP2009242111A (en) * | 2009-07-23 | 2009-10-22 | Seiko Epson Corp | Printer |
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