JPH02264927A - Thin film transistor array - Google Patents

Thin film transistor array

Info

Publication number
JPH02264927A
JPH02264927A JP1087704A JP8770489A JPH02264927A JP H02264927 A JPH02264927 A JP H02264927A JP 1087704 A JP1087704 A JP 1087704A JP 8770489 A JP8770489 A JP 8770489A JP H02264927 A JPH02264927 A JP H02264927A
Authority
JP
Japan
Prior art keywords
thin film
electrode
transistor array
transparent conductive
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1087704A
Other languages
Japanese (ja)
Inventor
Ryuichi Kawase
川瀬 龍一
Akihiro Hoshino
昭裕 星野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP1087704A priority Critical patent/JPH02264927A/en
Publication of JPH02264927A publication Critical patent/JPH02264927A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To execute a display of a high duty ratio and to suppress a defect caused by the influence of dust and a pin hole by forming a gate electrode and a conductive layer on the same plane. CONSTITUTION:On a glass substrate 21, a gate electrode 24 is formed into a pattern, and a transparent conductive film 23 is brought to pattern formation. Both of them are on the same plane, and do not intersect with each other. Subsequently, an insulating film 22 and a semiconductor layer 26 are formed, and formed into a pattern. Next, a picture element electrode 25 is formed. In a part in which a wiring of a transparent conductive film 42 is extended to the outside peripheral part of a thin film transistor array, an insulating film opening part 43 is provided, a source electrode 28, a drain electrode 27 and a wiring part are made, and simultaneously, a transparent conductive film outside take-out electrode 44 is formed. As a result, the film 42 can be connected to the outside. By constituting a thin film capacitor of the picture element electrode 25, the insulating film 22 and the transparent conductive film 23, a holding characteristic of a voltage is improved. Thereafter, a counter electrode 29 is formed on the substrate 30, and a liquid crystal 31 is enclosed between the transistor array and the substrate 30.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、例えば液晶表示装置の表示駆動用素子等とし
て利用される薄膜トランジスタアレイの構造および作製
方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to the structure and manufacturing method of a thin film transistor array used, for example, as a display driving element of a liquid crystal display device.

〈発明の技術的背景〉 液晶表示素子(以下LCDという)は、薄型、軽量、低
駆動電圧等の優れた特長を持ち、近年では、パソコン、
ワープロ等のOA機器のデイスプレィ、さらには小型テ
レビが実用化され、その応用範囲は、民生用、産業用を
問わず、ますます拡大している。そして、現在では、高
密度化、大画面化、高画質化、低コスト化へ向けて活発
な開発が行われている。特に、アモルファスシリコン薄
膜トランジスタ(以下a−5i TPTという)を表示
駆動用素子として用いたLCDは、マトリックス状に配
列された絵素を選択してマトリックス表示を行うことが
できることが知られている。
<Technical Background of the Invention> Liquid crystal display elements (hereinafter referred to as LCDs) have excellent features such as thinness, light weight, and low driving voltage.
2. Description of the Related Art Displays for office automation equipment such as word processors and even small televisions have been put into practical use, and the scope of their applications is expanding, whether for consumer use or industrial use. Currently, active development is underway to achieve higher density, larger screens, higher image quality, and lower costs. In particular, it is known that an LCD using an amorphous silicon thin film transistor (hereinafter referred to as a-5i TPT) as a display driving element can perform matrix display by selecting picture elements arranged in a matrix.

a−3ITFTを用いたLCDにおいて、高い表示コン
トラスト特性を有し、大容量表示を行うために有効な駆
動方式としては、各絵素にスイッチング素子として動作
するTPTはもちろんであるが、電荷保持用の’iiJ
 II9コンデンサを付加する方式である。この薄膜コ
ンデンサーは、表示信号電圧の保持特性を向上させると
ともに、TPT特性のばらつきに対して設計上の余裕を
持たせることができる。
In LCDs using a-3 ITFT, effective driving methods for achieving high display contrast characteristics and large-capacity display include TPT, which operates as a switching element for each pixel, as well as TPT for charge retention. 'iiJ
This is a method that adds a II9 capacitor. This thin film capacitor can improve the display signal voltage retention characteristics and provide design margin for variations in TPT characteristics.

〈発明が解決しようとする!1題〉 しかし、このa−3jTPTを用いたLCDは、大面積
において、欠陥がOでなければならない為、できるだけ
工程を簡略化する必要があり、′iil膜コンデンサを
付加する際にも、構造を考慮しなければならない、従来
のmtl*コンデンサ萎付加したa−3iTFTの構造
およびプロセスを第1図を参照しながら説明する。まず
、ガラス基板1上に、ITO等の透明導tM4を、堆積
しバターニングする0次にP−CVD法等により、Si
Nx、S10、等の第1絶縁膜2を形成する。続いてゲ
ート電極5をCr等により形成する0次に、P−CVD
法により、SiNx等の第2絶縁膜3、a−S+半導体
層7を連続堆積する。その後、半導体層7を、島状にバ
ターニングし、ITO等の透明導電膜を用いて、画素電
極6を形成する。この画素電極6と、第1絶縁膜2、第
2絶縁膜3および透明導電膜4により、薄膜コンデンサ
が形成される0次に、Ai等の導電膜により、ドレイン
電極8、ソース電極9を形成して、a−3iTFTアレ
イが作製される。
<Invention tries to solve! Problem 1> However, since the LCD using this A-3J TPT has to have O defects in a large area, it is necessary to simplify the process as much as possible, and even when adding a 'III film capacitor, the structure The structure and process of a conventional a-3i TFT with an mtl* capacitor, which must be taken into account, will be explained with reference to FIG. First, on a glass substrate 1, a transparent conductive material such as ITO is deposited and patterned using a zero-order P-CVD method, etc.
A first insulating film 2 of Nx, S10, etc. is formed. Subsequently, the gate electrode 5 is formed using Cr, etc., by P-CVD.
A second insulating film 3 such as SiNx and an a-S+ semiconductor layer 7 are successively deposited by a method. Thereafter, the semiconductor layer 7 is patterned into an island shape, and the pixel electrode 6 is formed using a transparent conductive film such as ITO. A thin film capacitor is formed by this pixel electrode 6, the first insulating film 2, the second insulating film 3, and the transparent conductive film 4. Next, a drain electrode 8 and a source electrode 9 are formed by a conductive film such as Ai. In this way, an a-3i TFT array is produced.

このようなプロセスを用いた場合、特に第1絶縁膜2を
P−CVD法等で堆積した場合の粉塵やピンホールが、
ゲート電極5の形成時に欠陥の原因となり易く、又、第
1、第2絶縁膜と2回も薄膜堆積を行う為、プロセスが
長くなる。
When such a process is used, dust and pinholes, especially when the first insulating film 2 is deposited by the P-CVD method, etc.
This tends to cause defects during the formation of the gate electrode 5, and the process becomes long because the thin film is deposited twice for the first and second insulating films.

く課題を解決するための手段〉 本発明は、薄膜トランジスタに連結され、表示駆動用電
圧が印加される画素電極に絶縁膜を介して対向する導電
膜層を設けることで電荷保持機能を持たせた′is膜ト
ランジスタアレイにおいて、薄膜トランジスタのゲート
電極と、該導電II! Jiを同一平面上に形成するこ
とを特徴とし、該導電膜層の外部への接続を薄膜トラン
ジスタアレイ外周部の絶縁膜開口部を介して行うこ七を
特徴とする薄膜トランジスタアレイである。
Means for Solving the Problems> The present invention provides a pixel electrode connected to a thin film transistor and to which a display driving voltage is applied, a conductive film layer facing each other with an insulating film interposed therebetween, thereby imparting a charge retention function. 'is film transistor array, the gate electrode of the thin film transistor and the conductive II! This thin film transistor array is characterized in that the conductive film layers are formed on the same plane, and that the conductive film layer is connected to the outside through an insulating film opening at the outer periphery of the thin film transistor array.

〈発明の実施例〉 本発明薄11!トランジスタアレイの実施例を第2図、
第3図を用いて詳細に述べる。第2図は本発明の薄膜ト
ランジスタアレイの断面図である。まずガラス基板21
上にCr等の導電膜を用いて、ゲート71t4fi24
を形成バターニングした0次に、1′rO等の透明導電
膜23を形成バターニングする。ゲート電8i24と透
明導電膜23は、同一平面上にあり、又、互いに交わる
ことなく配線した。kttいて、絶縁膜22、半導体層
26をP−CVD法により形成した。絶縁膜22は5k
Nx等で、膜厚は2900人〜5000人で薄膜トラン
ジスタの特性と薄膜コンデンサの実効的誘電、率の関係
で決定できる0次に、半導体層26と絶縁11!22を
島状にドライエツチングでバターニングした。絶縁膜2
2の膜厚は、このドライエツチングにより、可変でき、
任意の選択ができる0次に、[TO等の透明導電膜を用
い、画素型8i25を形成バターニングした。
<Embodiments of the invention> Thin according to the invention 11! Figure 2 shows an example of a transistor array.
This will be described in detail using FIG. FIG. 2 is a cross-sectional view of the thin film transistor array of the present invention. First, the glass substrate 21
A conductive film such as Cr is used on the gate 71t4fi24.
Next, a transparent conductive film 23 such as 1'rO is formed and patterned. The gate electrode 8i24 and the transparent conductive film 23 are on the same plane and are wired without crossing each other. Then, the insulating film 22 and the semiconductor layer 26 were formed by the P-CVD method. The insulation film 22 is 5k
The semiconductor layer 26 and the insulators 11 and 22 are dry-etched in the form of islands using butter. I did a ning. Insulating film 2
The film thickness of 2 can be varied by this dry etching.
A pixel type 8i25 was formed and patterned using a transparent conductive film such as [TO].

その後、第3図に示したように、透明導電11142の
配線が薄膜トランジスタアレイ外周部まで延長された部
分で絶縁膜開口部43をドライエツチングにより設け、
続いて、ソース電fi28、ドレイン電極27、および
配線部をAf等の導電膜で作製した際に、透明導TL膜
外部取り出し電極44も同時に形成した。これにより、
透明導電IIfi42は外部への接続が可能となった。
Thereafter, as shown in FIG. 3, an insulating film opening 43 is formed by dry etching at a portion where the wiring of the transparent conductor 11142 extends to the outer periphery of the thin film transistor array.
Subsequently, when the source electrode fi 28, the drain electrode 27, and the wiring portion were made of a conductive film such as Af, the transparent conductive TL film external extraction electrode 44 was also formed at the same time. This results in
The transparent conductive IIfi42 can now be connected to the outside.

又、画素電極25、絶縁膜22、透明導電膜23により
薄膜コンデンサを形成することにより駆動時の1フイ一
ルド期間の信号、電圧保持特性を向上させ、TPT特性
のばらつきに対して、設計上の裕度をもたせられた。又
、透明導電膜23を外部へ配線することにより、この薄
膜コンデンサの電気容量を調整できる。
In addition, by forming a thin film capacitor with the pixel electrode 25, the insulating film 22, and the transparent conductive film 23, the signal and voltage holding characteristics during one field period during driving are improved, and variations in TPT characteristics are improved by design. was given the freedom of Furthermore, by wiring the transparent conductive film 23 to the outside, the capacitance of this thin film capacitor can be adjusted.

以上のように薄膜トランジスタアレイを作製した後にガ
ラス基板30に対向電極29をバターニングし、薄膜ト
ランジスタアレイとガラス基板30間に液晶31を封入
し、薄膜トランジスタパネルを作製した。
After producing the thin film transistor array as described above, the counter electrode 29 was patterned on the glass substrate 30, liquid crystal 31 was sealed between the thin film transistor array and the glass substrate 30, and a thin film transistor panel was produced.

該薄膜トランジスタプレイは、画素電極は、表示面全体
にわたって、ガラス基板21上にマトリックス状に正規
配列され、これに対応してTPTもマトリックス配置さ
れる。TPTのゲート電極24と、ソース電極28は行
列方向に共通連結されて、外部駆動回路に接続される。
In the thin film transistor display, the pixel electrodes are regularly arranged in a matrix on the glass substrate 21 over the entire display surface, and the TPTs are also arranged in a matrix corresponding to this. The gate electrode 24 and source electrode 28 of the TPT are commonly connected in the row and column direction and connected to an external driving circuit.

ソース電極28に信号電圧を印加し、ゲート電極24に
スイッチング電圧を印加してTPTを選択的にオンオフ
動作させ、ソース電極28を介して画素電極25に電圧
印加し、画素電極25と対向電極29との間で印加され
る電界によって、液晶が電気光学特性を示し、任意の画
素表示が行なわれる。
A signal voltage is applied to the source electrode 28, a switching voltage is applied to the gate electrode 24 to selectively turn on and off the TPT, a voltage is applied to the pixel electrode 25 via the source electrode 28, and a voltage is applied to the pixel electrode 25 and the counter electrode 29. The liquid crystal exhibits electro-optical characteristics due to the electric field applied between the two, and arbitrary pixel display is performed.

く作用〉 画素電極25に電圧が印加された際に、画素1Xfiと
透明導電11g23との間で形成される薄膜コンデンサ
に電荷が蓄積される。この電荷はT P Tのオフ時に
開放されるが、Fjl I11!コンデンサで電荷が保
持されるため、オフ動作後も一定期間電界が印加され、
TPTのオン状態が接続され、液晶は電気光学特性を持
続する。従って、高コントラストの表示が可能となる。
Function> When a voltage is applied to the pixel electrode 25, charge is accumulated in the thin film capacitor formed between the pixel 1Xfi and the transparent conductor 11g23. This charge is released when T P T is turned off, but Fjl I11! Since the charge is retained in the capacitor, an electric field is applied for a certain period of time even after the OFF operation.
The on state of TPT is connected and the liquid crystal maintains its electro-optical properties. Therefore, high contrast display is possible.

又、プロセスが簡略化され、P−CVD法等の工程後に
ゲート電極のバターニングをする必要がないので、ゲー
ト電極の欠陥がなく、他の配線等の欠陥の少なく、かつ
容量性を有する回路素子機能を持つ薄膜トランジスタア
レイの作製が可能となった・ 〈発明の効果〉 以上のように本発明の薄膜トランジスタアレイは、電荷
保持機能を持ち、高デユーテイ比の表示駆動を行えると
共に、従来まで問題が多かったプロセスの増加、P−C
VD等の堆積等の粉塵やとンホールの影響による欠陥を
極力抑えることができ、欠陥の非常に少ない液晶パネル
による画素表示が可能となった。
In addition, the process is simplified and there is no need to pattern the gate electrode after a process such as the P-CVD method, so there is no defect in the gate electrode, there are few defects in other wiring, etc., and the circuit has capacitance. It has become possible to fabricate a thin film transistor array with element functions. <Effects of the Invention> As described above, the thin film transistor array of the present invention has a charge retention function and can drive a display at a high duty ratio, and also solves the problems that existed in the past. Increase in the number of processes, P-C
Defects caused by dust such as VD deposits and holes can be suppressed as much as possible, making it possible to display pixels on a liquid crystal panel with very few defects.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来の電荷保持機能を持たせた薄膜トランジ
スタアレイの一例の断面図であり、第2図は、本発明に
よる薄膜トランジスタアレイの一実施例を説明する′g
III!トランジスタアレイの断面図であり、第3図は
、本発明薄膜トランジスタアレイの外周部を説明する平
面図である。 1.11・・・ガラス基板  2・・・第1に@縁膜3
・・・第2絶縁膜    4・・・透明導電膜5・・・
ゲート電極    6・・・画素電極7・・・半導体層 9・・・ソース電極 12・・・液晶 22・・・絶縁膜 24・・・ゲート電極 26・・・半導体層 28・・・ソース電極 31・・・液晶 41・・・画素電極 43・・・絶縁膜開口部 8・・・ドレイン電極 IO・・・対向電極 2130・・・ガラス基1反 23・・・透明導電11り 25・・・画素電極 27・・・ドレイン電極 29・・・対向電極 42・・・透明導電膜 44・・・取り出し:i極 第1図 特 許 凸 代 版 表 出 印 者 願 刷 株 鈴 人 式
FIG. 1 is a cross-sectional view of an example of a conventional thin film transistor array having a charge retention function, and FIG. 2 is a cross-sectional view of an example of a thin film transistor array according to the present invention.
III! FIG. 3 is a cross-sectional view of the transistor array, and FIG. 3 is a plan view illustrating the outer periphery of the thin film transistor array of the present invention. 1.11...Glass substrate 2...First @edge film 3
...Second insulating film 4...Transparent conductive film 5...
Gate electrode 6... Pixel electrode 7... Semiconductor layer 9... Source electrode 12... Liquid crystal 22... Insulating film 24... Gate electrode 26... Semiconductor layer 28... Source electrode 31 ...Liquid crystal 41...Pixel electrode 43...Insulating film opening 8...Drain electrode IO...Counter electrode 2130...Glass base 1 23...Transparent conductor 11 25... Pixel electrode 27...Drain electrode 29...Counter electrode 42...Transparent conductive film 44...Removal: i-pole Figure 1 Patent letterpress representative edition Printer's application printing Suzuto style

Claims (2)

【特許請求の範囲】[Claims] (1)薄膜トランジスタに連結され、表示駆動用電圧が
印加される画素電極に絶縁膜を介して対向する導電膜層
を設けることで電荷保持機能を持たせた薄膜トランジス
タアレイにおいて、ゲート電極と該導電膜層を同一平面
上に形成することを特徴とする薄膜トランジスタアレイ
(1) In a thin film transistor array that has a charge retention function by providing a conductive film layer facing the pixel electrode connected to the thin film transistor and to which a display driving voltage is applied via an insulating film, the gate electrode and the conductive film A thin film transistor array characterized in that layers are formed on the same plane.
(2)導電膜層の外部への接続を、薄膜トランジスタア
レイ外周部の絶縁膜開口部を介して行うことを特徴とす
る請求項(1)記載の薄膜トランジスタアレイ。
(2) The thin film transistor array according to claim 1, wherein the conductive film layer is connected to the outside through an opening in the insulating film at the outer periphery of the thin film transistor array.
JP1087704A 1989-04-06 1989-04-06 Thin film transistor array Pending JPH02264927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1087704A JPH02264927A (en) 1989-04-06 1989-04-06 Thin film transistor array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1087704A JPH02264927A (en) 1989-04-06 1989-04-06 Thin film transistor array

Publications (1)

Publication Number Publication Date
JPH02264927A true JPH02264927A (en) 1990-10-29

Family

ID=13922306

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1087704A Pending JPH02264927A (en) 1989-04-06 1989-04-06 Thin film transistor array

Country Status (1)

Country Link
JP (1) JPH02264927A (en)

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